Electronics: circuits and components Books
Taylor & Francis Ltd Basic Electrical Installation Work
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£36.99
Taylor & Francis Inc Electronics
Book SynopsisElectronics: Basic, Analog, and Digital with PSpice does more than just make unsubstantiated assertions about electronics. Compared to most current textbooks on the subject, it pays significantly more attention to essential basic electronics and the underlying theory of semiconductors.In discussing electrical conduction in semiconductors, the author addresses the important but often ignored fundamental and unifying concept of electrochemical potential of current carriers, which is also an instructive link between semiconductor and ionic systems at a time when electrical engineering students are increasingly being exposed to biological systems. The text presents the background and tools necessary for at least a qualitative understanding of new and projected advances in microelectronics. The author provides helpful PSpice simulations and associated procedures (based on schematic capture, and using OrCAD 16.0 Demo software), which are availaTable of ContentsBasic Diode Circuits. Basic Principles of Semiconductors. pn Junction and Semiconductor Diodes. Semiconductor Fabrication. Field Effect Transistors. Bipolar Junction Transistor. Two-Port Circuits, Amplifiers, and Feedback. Single-Stage Transistor Amplifiers. Multistage and Feedback Amplifiers. Differential and Operational Amplifiers. Power Amplifiers and Switches. Basic Elements of Digital Circuits. Digital Logic Circuit Families.
£48.96
Taylor & Francis Inc Communication Architectures for SystemsonChip
Book SynopsisA presentation of state-of-the-art approaches from an industrial applications perspective, Communication Architectures for Systems-on-Chip shows professionals, researchers, and students how to attack the problem of data communication in the manufacture of SoC architectures. With its lucid illustration of current trends and research improving the performance, quality, and reliability of transactions, this is an essential reference for anyone dealing with communication mechanisms for embedded systems, systems-on-chip, and multiprocessor architecturesor trying to overcome existing limitations. Exploring architectures currently implemented in manufactured SoCsand those being proposedthis book analyzes a wide range of applications, including: Well-established communication buses Less common networks-on-chip Modern technologies that include the use of carbon nanotubes (CNTs) Optical lTable of ContentsIntroduction. Communication Buses. NoC Architectures. Quality-of-Service in NoCs. Emerging Interconnect Technologies. HeTERO: Hybrid Topology Exploration for RF based On Chip Networks. Intra-/Inter-Chip Optical Communications. Security Issues in SoC Communication.
£195.00
APress Embedded Software Design
Book SynopsisDesign higher-quality embedded software from concept through production. This book assumes basic C and microcontroller programming knowledge and is organized into three critical areas: Software Architecture and Design; Agile, DevOps, and Processes; and Development and Coding Skills.You''ll start with a basic introduction to embedded software architecture and the considerations for a successful design. The book then breaks down how to architect an RTOS-based application and explore common design patterns and building blocks. Next, you''ll review embedded software design processes such as TDD, CI/CD, modeling, and simulation that can be used to accelerate development. Finally, the book will examine how to select a microcontroller, write configurable code, coding strategies, techniques, and tools developers can''t live without. Embedded systems are typically designed using microcontrollers to build electronic systems wTable of ContentsPart 1 - Software Architecture DesignEmbedded System Design Philosophy⁃ Challenges Facing Embedded Developers⁃ Traditional Embedded Software Development⁃ The Age of Modeling, Simulation and Off-chip Development⁃ SOLID Design Principles⁃ Test Driven Development (TDD)⁃ Why Best Practices?Embedded Software Architecture Design⁃ Architect First, Code Second⁃ Architectural Layers⁃ Single vs Multicore Architectures⁃ Application Domain Decomposition⁃ Interface Design Principles⁃ Architectural LanguagesRTOS Application Design⁃ Tasks, Threads and Processes⁃ Task Decomposition Techniques⁃ Task Scheduling Algorithms⁃ Setting Task Priorities⁃ Schedule-ability using Rate Monotonic Analysis⁃ Designing Application Data Flow⁃ Producer, Consumer, Processor and Transfer MechanismsSecure Application Design⁃ Platform Security Architecture (PSA)⁃ Security through Isolation⁃ TrustZone⁃ Memory map design⁃ Memory Protection Units (MPUs)⁃ Secure boot⁃ Secure bootloaders and OTAsDesign Patterns⁃ pub / sub⁃ Rtos patterns⁃ Handling interrupts⁃ State machines⁃ Active objectsPart 2 - Development ProcessesSoftware Quality⁃ Coding Standards⁃ Code Reviews⁃ Code Metrics⁃ Code Analysis (static vs dynamic)Software Testing and Verification⁃ Integration Testing⁃ Performance Testing⁃ Regression Testing Software Verification Results⁃ Testing of executable object code⁃ Code coverage analysis⁃ Test ReportsApplication Modeling and Simulation⁃ Modeling Methodologies⁃ Simulations Role⁃ wxWidgets⁃ ExampleTest Driven Development⁃ Overview⁃ Test Harnesses⁃ Code Coverage⁃ Test DesignContinuous Integration / Continuous Deployment⁃ Process Overview⁃ Docker⁃ Jenkins⁃ Git Integrations⁃ Merge Process⁃ DeploymentPart 3 - Where the Bits hit the SiliconSelecting a Microcontroller⁃ Traditional Techniques⁃ Modern Selection Process⁃ Selection Considerations⁃ KT Matrix Design and UseCode Implementation Techniques⁃ Interfaces⁃ Command Processing⁃ Task initialization⁃ Assertions⁃ TelemetryDiagnostic and Fault Handling⁃ Design failure mode and effect analysis (DFMEA)⁃ Fault Handling Strategies⁃ Diagnostic Tasks⁃ Error Checking Code (ECC)⁃ WatchdogsApplication Optimization⁃ Models and Simulation versus Reality⁃ Scalability⁃ Maintenance⁃ Code size versus speed⁃ Compilation Settings⁃ Memory managementThe Right Tool for the Job⁃ Tracing⁃ Code Analyzers⁃ Protocol analysis⁃ Metric tools⁃ Open source versus commercial
£40.49
Raspberry Pi Press Design an RP2040 board with KiCad
Book Synopsis
£14.99
Springer Nature Switzerland AG Physical Design and Mask Synthesis for Directed Self-Assembly Lithography
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£80.99
Springer Nature Switzerland AG A Synergistic Framework for Hardware IP Privacy and Integrity Protection
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£79.20
Springer Nature Switzerland AG Plasma and Spot Phenomena in Electrical Arcs
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£134.99
Springer Nature Switzerland AG Embedded System Design: Embedded Systems
Book SynopsisA unique feature of this open access textbook is to provide a comprehensive introduction to the fundamental knowledge in embedded systems, with applications in cyber-physical systems and the Internet of things. It starts with an introduction to the field and a survey of specification models and languages for embedded and cyber-physical systems. It provides a brief overview of hardware devices used for such systems and presents the essentials of system software for embedded systems, including real-time operating systems. The author also discusses evaluation and validation techniques for embedded systems and provides an overview of techniques for mapping applications to execution platforms, including multi-core platforms. Embedded systems have to operate under tight constraints and, hence, the book also contains a selected set of optimization techniques, including software optimization techniques. The book closes with a brief survey on testing. This fourth edition has been updated and revised to reflect new trends and technologies, such as the importance of cyber-physical systems (CPS) and the Internet of things (IoT), the evolution of single-core processors to multi-core processors, and the increased importance of energy efficiency and thermal issues.Table of ContentsChapter 1. Introduction.- Chapter 2. Specifications and Modeling.- Chapter 3. Embedded System Hardware.- Chapter 4. System Software.- Chapter 5. Evaluation and Validation.- Chapter 6. Application Mapping.- Chapter 7. Optimization.- Chapter 8. Test.
£40.49
Springer Nature Switzerland AG Silicon Sensors and Actuators: The Feynman
Book SynopsisThis book thoroughly reviews the present knowledge on silicon micromechanical transducers and addresses emerging and future technology challenges. Readers will acquire a solid theoretical and practical background that will allow them to analyze the key performance aspects of devices, critically judge a fabrication process, and then conceive and design new ones for future applications. Envisioning a future complex versatile microsystem, the authors take inspiration from Richard Feynman’s visionary talk “There is Plenty of Room at the Bottom” to propose that the time has come to see silicon sensors as part of a “Feynman Roadmap” instead of the “More-than-Moore” technology roadmap. The sharing of the author’s industrially proven track record of development, design, and manufacturing, along with their visionary approach to the technology, will allow readers to jump ahead in their understanding of the core of the topic in a very effective way. Students, researchers, engineers, and technologists involved in silicon-based sensor and actuator research and development will find a wealth of useful and groundbreaking information in this book.Table of Contents1. Silicon as Sensor Material2. Epitaxial Growth3. Thin Film Deposition4. Thin Films Characterization & Metrology5. Dry silicon etch 6. Lithography7. HF Release 8. Galvanic growth9. Wet Etch and Cleaning 10. Piezoelectric materials 11. Wafer to wafer Bonding12. Linear and non linear mechanichs in MEMS 13. Inertial sensors 14. Magnetometer15. MEMS microphones 16. Pressure Sensors17. Enviromental Sensors18. Mirror19. Piezo ink jet printers20. Speakers21. Autofocus22. Electronic sensors front-end23. Electronic Interfaces for actuators24. Package25. Testing26. Reliability27. The future of sensor and actuators
£66.49
Springer Nature Switzerland AG Theory and Practice of Thermal Transient Testing
Book SynopsisThis book discusses the significant aspects of thermal transient testing, the most important method of thermal characterization of electronics available today. The book presents the theoretical background of creating structure functions from the measured results with mathematical details. It then shows how the method can be used for thermal qualification, structure integrity testing, determining material parameters, and calibrating simulation models. General practical questions about measurements are discussed to help beginners carry out thermal transient testing. The particular problems and tricks of measuring with various electronic components, such as Si diodes, bipolar transistors, MOS transistors, IGBT devices, resistors, capacitors, wide bandgap materials, and LEDs, are covered in detail with the help of various use cases. This hands-on book will enable readers to accomplish thermal transient testing on any new type of electronics and provides the theoretical details needed to understand the opportunities and limitations offered by the methodology. The book will be an invaluable reference for practicing engineers, students, and researchers.Table of ContentsIntroduction: the Importance and Motivation.- Theoretical Background: History, the Network Identification by Deconvolution (NID) Method, Structure Functions, the Thermal Signature.- The Use of Thermal Transient Testing.- General Practical Questions and the Flow of Thermal Transient Measurements.- On the Accuracy and Repeatability of Thermal Measurements.
£67.49
Springer Nature Switzerland AG Advanced X-Ray Radiation Detection:: Medical
Book SynopsisThis book offers readers an overview of some of the most recent advances in the field of technology for X-ray medical imaging. Coverage includes both technology and applications in SPECT, PET and CT, with an in-depth review of the research topics from leading specialists in the field. Coverage includes conversion of the X-ray signal into analogue/digital value, as well as a review of CMOS chips for X-ray image sensors. Emphasis is on high-Z materials like CdTe, CZT and GaAs, since they offer the best implementation possibilities for direct conversion X-ray detectors. The discussion includes material challenges, detector operation physics and technology and readout integrated circuits required to detect signals processes by high-Z sensors. Authors contrast these emerging technologies with more established ones based on scintillator materials. This book is an excellent reference for people already working in the field as well as for people wishing to enter it.Table of ContentsX-ray Detectors in Medical Imaging.- Modelling spectroscopic performance of pixelated semiconductor detectors through Monte-Carlo simulation.- Status of DEXA Instrumentation Using Direct and Indirect Detectors.- CZT Detectors for Nuclear Medicine.- Positron Emission Tomography (PET) Imaging Based on Sub-Millimeter Pixelated CdZnTe Detectors.- Medical Photon-Counting CT – Status and Clinical Applications Review.- Multi-material decomposition (m-MD) based spectral imaging in photon-counting CT.- X-ray Multispectral CT Imaging by Projection Sequences Blind Separation based on Basis-effect or Basis-material decomposition.- Direct Iterative Basis Image Reconstruction Based on MAP-EM Algorithm for Spectral CT.- Linearly Polarized X-ray Fluorescence Computed Tomography with a Photon Counting Detector.- Detector shift iteration method for improving spatial resolution and suppressing pixel value distortion in direct and indirect X-ray detectors.- A new method of estimating incident x-ray spectra with photon counting detectors using a limited number of energy bins with dedicated clinical x-ray imaging systems.
£56.24
Springer Nature Switzerland AG Security of Biochip Cyberphysical Systems
Book SynopsisThis book provides readers with a valuable guide to understanding security and the interplay of computer science, microfluidics, and biochemistry in a biochip cyberphysical system (CPS). The authors uncover new, potential threat and trust-issues to address, as this emerging technology is poised to be adapted at a large scale. Readers will learn how to secure biochip CPS by leveraging the available resources in different application contexts, as well as how to ensure intellectual property (IP) is protected against theft and counterfeits. This book enables secure biochip CPS design by helping bridge the knowledge gap at the intersection of the multi-disciplinary technology that drives biochip CPS.Table of ContentsIntroduction.- Threat landscape.- Architecture for Security.- Tools for Security.- Watermarking of Bio-IP.- Obfuscation of Bio-IP.- Conclusion.
£49.49
Springer Nature Switzerland AG Computer Systems: Digital Design, Fundamentals of
Book SynopsisThis updated textbook covers digital design, fundamentals of computer architecture, and ARM assembly language. The book starts by introducing computer abstraction, basic number systems, character coding, basic knowledge in digital design, and components of a computer. The book goes on to discuss information representation in computing, Boolean algebra and logic gates, and sequential logic. The book also presents introduction to computer architecture, Cache mapping methods, and virtual memory. The author also covers ARM architecture, ARM instructions, ARM assembly language using Keil development tools, and bitwise control structure using C and ARM assembly language. The book includes a set of laboratory experiments related to digital design using Logisim software and ARM assembly language programming using Keil development tools. In addition, each chapter features objectives, summaries, key terms, review questions, and problems.Table of ContentsChapter1: Signal and number systems.- Chapter2: Boolean Logics and Logic Gates.- Chapter3: Minterms, Maxterms, Karnaugh Map (K-Map), and Universal Gates.- Chapter4: Combinational Logic.- Chapter5: Synchronous Sequential Logic.- Chapter6: Introduction to Computer Architecture.- Chapter7: Memory.- Chapter8: Assembly Language and ARM Instructions Part I.- Chapter9: ARM Assembly Language Programming Using Keil Development Tools.- Chapter10: ARM Instructions Part II and Instraction Formats.- Chapter11: Bitwise and Control Structures Used for Programming with C and ARM Assembly Language.
£44.99
Springer Nature Switzerland AG Mapping Innovation: The Discipline of Building
Book SynopsisThis book is an eye-opener for businesses unveiling how technology trends can be deployed to redesign products, services and processes. The authors provide business opportunities based on technological innovation across 10 industrial sectors in easy to read case studies. Each case study is a story that narrates the potential and influence of a technological innovation on an enterprise, by defining the challenges faced, the type of technology adopted, and the impact. Provides readers with compelling reasons for implementing technology trends in industrial value chains; Written in a simple, easy to read and exciting manner to be accessible to readers with different backgrounds and interests; Uses a single, structured paradigm in all the case studies. Table of Contents1-Agriculture 2-Automotive 3-Banking And Financial Services 4-Construction 5-Education 6-Food And Beverage 7-Healthcare 8-Media And Entertainment 9-Oil And Gas 10-Printing And Packaging 11-Real-Estate 12-Retail 13-Telecommunications 14-Textiles 15-Tourism
£40.49
Springer International Publishing AG On-Chip Networks, Second Edition
Book SynopsisThis book targets engineers and researchers familiar with basic computer architecture concepts who are interested in learning about on-chip networks. This work is designed to be a short synthesis of the most critical concepts in on-chip network design. It is a resource for both understanding on-chip network basics and for providing an overview of state of-the-art research in on-chip networks. We believe that an overview that teaches both fundamental concepts and highlights state-of-the-art designs will be of great value to both graduate students and industry engineers. While not an exhaustive text, we hope to illuminate fundamental concepts for the reader as well as identify trends and gaps in on-chip network research. With the rapid advances in this field, we felt it was timely to update and review the state of the art in this second edition. We introduce two new chapters at the end of the book. We have updated the latest research of the past years throughout the book and also expanded our coverage of fundamental concepts to include several research ideas that have now made their way into products and, in our opinion, should be textbook concepts that all on-chip network practitioners should know. For example, these fundamental concepts include message passing, multicast routing, and bubble flow control schemes.Table of ContentsPreface.- Acknowledgments.- Introduction.- Interface with System Architecture.- Topology.- Routing.- Flow Control.- Router Microarchitecture.- Modeling and Evaluation.- Case Studies.- Conclusions.- References.- Authors' Biographies.
£37.85
Springer International Publishing AG System Level ESD Protection
Book SynopsisThis book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection. It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations.Table of ContentsSystem 1 Level ESD design.- System Level Test Methods.- On-Chip System Level ESD Devices and Clamps.- Latch-up at System-Level Stress.- IC and Systemn ESD Co-Design.
£80.99
Springer International Publishing AG Electronics for Embedded Systems
Book SynopsisThis book provides semester-length coverage of electronics for embedded systems, covering most common analog and digital circuit-related issues encountered while designing embedded system hardware. It is written for students and young professionals who have basic circuit theory background and want to learn more about passive circuits, diode and bipolar transistor circuits, the state-of-the-art CMOS logic family and its interface with older logic families such as TTL, sensors and sensor physics, operational amplifier circuits to condition sensor signals, data converters and various circuits used in electro-mechanical device control in embedded systems. The book also provides numerous hardware design examples by integrating the topics learned in earlier chapters. The last chapter extensively reviews the combinational and sequential logic design principles to be able to design the digital part of embedded system hardware.Table of ContentsFundamentals of Passive Circuit Analysis.- Diode and Bipolar Transistor Circuits.- MOS Transistors and CMOS Circuits.- TTL Logic and CMOS-TTL Interface.- Physics of Sensors.- Operational Amplifiers and Circuits.- Data Converters.- Front-End Electronics for Embedded Systems.- Review of Combinational and Sequential Logic Circuits and Design.
£62.99
Springer International Publishing AG Designing with Xilinx® FPGAs: Using Vivado
Book SynopsisThis book helps readers to implement their designs on Xilinx® FPGAs. The authors demonstrate how to get the greatest impact from using the Vivado® Design Suite, which delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. This book is a hands-on guide for both users who are new to FPGA designs, as well as those currently using the legacy Xilinx tool set (ISE) but are now moving to Vivado. Throughout the presentation, the authors focus on key concepts, major mechanisms for design entry, and methods to realize the most efficient implementation of the target design, with the least number of iterations.Table of ContentsChapter 1: State of the Art Programmable Logic 1Chapter 2: Vivado Design Tools 17Chapter 3: IP Flows 23Chapter 4: Gigabit Transceivers 35Chapter 5: Memory Controllers 49Chapter 6: Processor Options 65Chapter 7: Vivado IP Integrator 75Chapter 8: SysGen for DSP 85Chapter 9: Synthesis 97Chapter 10: C Based Design 111Chapter 11: Simulation 127Chapter 12: Clocking 141Chapter 13: Stacked Silicon Interconnect (SSI) 155Chapter 14: Timing Closure 167Chapter 15: Power Analysis and Optimization 179Chapter 16: System Monitor 191Chapter 17: Hardware Debug 205Chapter 18: Emulation Using FPGAs 221Chapter 19: Partial Reconfiguration & Hierarchical Design 239
£82.49
Springer International Publishing AG Inkjet-Configurable Gate Array: Towards Application Specific Printed Electronic Circuits
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£80.99
Springer-Verlag Berlin and Heidelberg GmbH & Co. KG Advances in Solar Photovoltaic Power Plants
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£125.99
River Publishers Heterogeneous Cyber Physical Systems of Systems
Book SynopsisCyber-physical systems are the natural extension of the so-called “Internet of Things”. They are “systems of collaborating computational elements controlling physical entities”. Cyber Physical Systems of Systems (CPSoS) are considered “The Next Computing Revolution” after Mainframe computing (60’s-70’s), Desktop computing & Internet (80’s-90’s) and Ubiquitous computing (00’s); because all aspects of daily life are rapidly evolving towards humans interacting amongst themselves as well as their environment via computational devices (often mobile), and because in most cases systems will employ their computational capabilities to interact amongst themselves. CPSoS enable the physical world to merge with the cyber one. Using sensors, the embedded systems monitor and collect data from physical processes, such as the steering of a vehicle, energy consumption or human health functions. The systems are networked making the data globally available. CPSoS make it possible for software applications to directly interact with events in the physical world, for example to measure and react to changes in blood pressure or peaks in energy consumption. Embedded hardware and software systems crucially expand the functionality and competitiveness of vehicles, aircraft, medical equipment, production plants and household appliances. Connecting these systems to a virtual environment of globally networked services and information systems opens completely new areas of innovation and novel business platforms. Future CPSoS will have many sophisticated, interconnected parts that must instantaneously exchange, parse, and act on detailed data in a highly coordinated manner. Continued advances in science and engineering will be necessary to enable advances in design and development of these complex systems. Multi- scale, multi-layer, multi-domain, and multi-system integrated infrastructures will require new foundations in system science and engineering. Scientists and engineers with an understanding of otherwise physical systems will need to work in tandem with computer and information scientists to achieve effective, workable designs. In this tutorial, basic and advanced issues on the design of the future heterogeneous CPSoS are presented including relevant Blockchain technologies, reconfigurable systems, advanced sensor interfaces and human-centered design processes. Certain advanced tools for the design and implementation of the cyber parts of the CPSoS (i.e. FPGA design tools from Xilinx) are also covered.Table of Contents0. Introduction; 1. Meta-Arduino-ing Microcontroller-Based Cyber Physical System Design; 2. Adaptivity and self-awareness of CPSs and CPSoSs; 3. The use of Blockchain in supply chain management; 4. Edge Intelligence – How to design Efficient Intelligent Edge devices; 5. Putting the humans in the middle of the CPS design process; 6. Design of scalable sensor interface circuits for a smart world; 7. Powering Cyber-Physical-System nodes by Energy Harvesting; 8. Hands on Hardware/Software Co-Design
£90.24
Springer Verlag, Singapore Advances in Communication and Computational Technology: Select Proceedings of ICACCT 2019
Book SynopsisThis book presents high-quality peer-reviewed papers from the International Conference on Advanced Communication and Computational Technology (ICACCT) 2019 held at the National Institute of Technology, Kurukshetra, India. The contents are broadly divided into four parts: (i) Advanced Computing, (ii) Communication and Networking, (iii) VLSI and Embedded Systems, and (iv) Optimization Techniques.The major focus is on emerging computing technologies and their applications in the domain of communication and networking. The book will prove useful for engineers and researchers working on physical, data link and transport layers of communication protocols. Also, this will be useful for industry professionals interested in manufacturing of communication devices, modems, routers etc. with enhanced computational and data handling capacities.Table of ContentsPart 1: Advanced Computing.- Distributed Computing.- Cloud Computing.- Cluster and Grid Computing.- Green Computing.- Image and Video Processing-. Big Data Computing.- Machine Learning.- Parallel Computing.- Soft Computing.- Quantum Computing.- Mobile Computing.- Quantum Computing.- Mobile Computing.- Biomedical Computing, Bioinformatics.- Swarm Intelligence & Swarm Robotics.- Evolutionary Computing.- Cellular Automata.- Cellular Computing.- Membrane Computing.- Part 2: Communication & Networking.- Signal Processing.- Image Processing.- Computer Network.- Wireless Network.- Ad-hoc Network.- Internet of Things (IOT).- Network Security.- Cryptography.- Physical Layer Security.- Cognitive Radios.- Software Defined Radio.- Optical Communication.- Antenna.- Satellite and Space Communications.- Next Generation Computing and Communication.- Network Analytics.- Vehicular, Underground and Underwater Networks.- RFID and Sensor Network.- Mobile & Ubiquitous Communication Networks.- Mobile Cloud.- Internet Technologies.- Information-Centric Networking.- Remote Sensing and GIS.- Network Protocols.- Modelling & Simulation of Communication Networks and Systems.- Software-Defined Networking.- Fault Tolerance, Reliability, and Survivability.- Flow and Congestion Control.- Network Architectures.- Part 3: VLSI & Embedded Systems.- Computer Architecture.- VLSI Circuit Design and CAD Tools.- Material Science and Nano Technology.- Nano Electronics and VLSI Technology.- Embedded Systems.- Mathematical Modeling and Scientific Computing.- Hybrid Intelligent Models and Applications.- Medical Informatics.- Part 4: Optimization Technique.- Control Systems and Applications.- Renewable Energy.- Power Electronics.- Cloud and Systems Management.- Big Data Communication and Analytics.- Algorithm Heuristic.- Graph, Geometric Algorithms and Applications.- Computer Graphics, Simulation, and Modelling.- Pattern Recognition and Analysis.- Intelligent Image Analysis.- Neuroimaging Techniques.- Robotics and Machine Vision.- Systems and Software Engineering.- Real-time Systems.- Intelligent Control.- Intelligent E-Learning Systems.- Fuzzy Logic.- Artificial Neural Network.- Evolutionary Computation.- Learning Theory.- Probabilistic Methods.- Multimedia.- Text mining.- Social media systems.- Adaptive hypermedia.- Crowd sourcing.- Personalization.- Security, privacy and social impact.- Applications of Computational Intelligence techniques in Science, Engineering, medicine, finance and education etc.- Mechatronics and Robotics.
£161.99
John Wiley & Sons Inc RF and Microwave Transistor Oscillator Design
Book SynopsisCombining the theory and practice of RF and microwave engineering, RF and Microwave Transistor Oscillator Design provides comprehensive results of established and new theoretical analysis, and the practical design of oscillators on modern active devices.Table of ContentsAbout the Author ix Preface xi Acknowledgements xv 1 Nonlinear circuit design methods 1 1.1 Spectral-domain analysis 1 1.1.1 Trigonometric identities 2 1.1.2 Piecewise-linear approximation 4 1.1.3 Bessel functions 8 1.2 Time-domain analysis 9 1.3 Newton–Raphson algorithm 12 1.4 Quasilinear method 15 1.5 Van der Pol method 20 1.6 Computer-aided analysis and design 24 References 28 2 Oscillator operation and design principles 29 2.1 Steady-state operation mode 29 2.2 Start-up conditions 31 2.3 Oscillator configurations and historical aspects 36 2.4 Self-bias condition 43 2.5 Oscillator analysis using matrix techniques 50 2.5.1 Parallel feedback oscillator 50 2.5.2 Series feedback oscillator 53 2.6 Dual transistor oscillators 55 2.7 Transmission-line oscillator 60 2.8 Push–push oscillator 65 2.9 Triple-push oscillator 72 2.10 Oscillator with delay line 75 References 79 3 Stability of self-oscillations 83 3.1 Negative-resistance oscillator circuits 83 3.2 General single-frequency stability condition 86 3.3 Single-resonant circuit oscillators 87 3.3.1 Series resonant circuit oscillator with constant load 87 3.3.2 Parallel resonant circuit oscillator with nonlinear load 88 3.4 Double-resonant circuit oscillator 89 3.5 Stability of multi-resonant circuits 91 3.5.1 General multi-frequency stability criterion 91 3.5.2 Two-frequency oscillation mode and its stability 93 3.5.3 Single-frequency stability of oscillator with two coupled resonant circuits 94 3.5.4 Transistor oscillators with two coupled resonant circuits 96 3.6 Phase plane method 105 3.6.1 Free-running oscillations in lossless resonant LC circuits 106 3.6.2 Oscillations in lossy resonant LC circuits 108 3.6.3 Aperiodic process in lossy resonant LC circuits 110 3.6.4 Transformer-coupled MOSFET oscillator 112 3.7 Nyquist stability criterion 113 3.8 Start-up and stability 118 References 125 4 Optimum design and circuit technique 127 4.1 Empirical optimum design approach 128 4.2 Analytic optimum design approach 136 4.3 Parallel feedback oscillators 138 4.3.1 Optimum oscillation condition 138 4.3.2 Optimum MOSFET oscillator 139 4.4 Series feedback bipolar oscillators 142 4.4.1 Optimum oscillation condition 142 4.4.2 Optimum common base oscillator 143 4.4.3 Quasilinear approach 146 4.4.4 Computer-aided design 150 4.5 Series feedback MESFET oscillators 152 4.5.1 Optimum common gate oscillator 152 4.5.2 Quasilinear approach 154 4.5.3 Computer-aided design 157 4.6 High-efficiency design technique 162 4.6.1 Class C operation mode 162 4.6.2 Class E power oscillators 165 4.6.3 Class DE power oscillators 170 4.6.4 Class F mode and harmonic tuning 172 4.7 Practical oscillator schematics 177 References 182 5 Noise in oscillators 187 5.1 Noise figure 187 5.2 Flicker noise 196 5.3 Active device noise modelling 198 5.3.1 MOSFET devices 198 5.3.2 MESFET devices 200 5.3.3 Bipolar transistors 203 5.4 Oscillator noise spectrum: linear model 205 5.4.1 Parallel feedback oscillator 205 5.4.2 Negative resistance oscillator 214 5.4.3 Colpitts oscillator 216 5.5 Oscillator noise spectrum: nonlinear model 219 5.5.1 Kurokawa approach 219 5.5.2 Impulse response model 224 5.6 Loaded quality factor 235 5.7 Amplitude-to-phase conversion 239 5.8 Oscillator pulling figure 241 References 245 6 Varactor and oscillator frequency tuning 251 6.1 Varactor modelling 251 6.2 Varactor nonlinearity 255 6.3 Frequency modulation 258 6.4 Anti-series varactor pair 262 6.5 Tuning linearity 267 6.5.1 VCOs with lumped elements 267 6.5.2 VCOs with transmission lines 273 6.6 Reactance compensation technique 276 6.7 Practical VCO schematics 280 6.7.1 VCO implementation techniques 280 6.7.2 Differential VCOs 286 6.7.3 Push–push VCOs 292 References 296 7 CMOS voltage-controlled oscillators 299 7.1 MOS varactor 299 7.2 Phase noise 305 7.3 Flicker noise 310 7.4 Tank inductor 313 7.5 Circuit design concepts and technique 317 7.5.1 Device operation modes 317 7.5.2 Start-up and steady-state conditions 321 7.5.3 Differential cross-coupled oscillators 325 7.5.4 Wideband tuning techniques 326 7.5.5 Quadrature VCOs 331 7.6 Implementation technology issues 333 7.7 Practical schematics of CMOS VCOs 335 References 342 8 Wideband voltage-controlled oscillators 347 8.1 Main requirements 347 8.2 Single-resonant circuits with lumped elements 351 8.2.1 Series resonant circuit 351 8.2.2 Parallel resonant circuit 353 8.3 Double-resonant circuit with lumped elements 356 8.4 Transmission line circuit realization 360 8.4.1 Oscillation system with uniform transmission line 360 8.4.2 Oscillation system with multi-section transmission line 365 8.5 VCO circuit design aspects 369 8.5.1 Common gate MOSFET and MESFET VCOs 369 8.5.2 Common collector bipolar VCO 373 8.5.3 Common base bipolar VCO 376 8.6 Wideband nonlinear design 378 8.7 Dual mode varactor tuning 381 8.8 Practical RF and microwave wideband VCOs 387 8.8.1 Wireless and satellite TV applications 387 8.8.2 Microwave monolithic VCO design 391 8.8.3 Push–push oscillators and oscipliers 394 References 396 9 Noise reduction techniques 399 9.1 Resonant circuit design technique 399 9.1.1 Oscillation systems with lumped elements 400 9.1.2 Oscillation systems with transmission lines 402 9.2 Low-frequency loading and feedback optimization 410 9.3 Filtering technique 416 9.4 Noise-shifting technique 423 9.5 Impedance noise matching 426 9.6 Nonlinear feedback loop noise suppression 430 References 433 Index 437
£111.56
John Wiley & Sons Inc Analysis and Design of Autonomous Microwave
Book SynopsisPresents harmonic-balance techniques that substantially increase the designer control over the oscillation in autonomous circuits. Provides an in-depth explanation and analysis of the main types of autonomous circuits Covers recent techniques for nonlinear-design and the stabilization of circuits .Table of ContentsPreface. 1. Oscillator Dynamics. 1.1. Introduction. 1.2. Operational Principle of Free-Running Oscillators. 1.3. Impedance-Admittance Analysis of an Oscillator. 1.4. Frequency-Domain Formulation of an Oscillator Circuit. 1.5. Oscillator Dynamics. 1.6. Phase Noise. 2. Phase Noise. 2.1. Introduction. 2.2. Random Variable and random Processes. 2.3. Noise Sources in Electronic Circuits. 2.4. Derivation of the Oscillator Noise Spectrum Using Time-Domain Analysis. 2.5. Frequency-Domain Analysis of a Noisy Oscillator. 3. Bifurcation Analysis. 3.1. Introduction. 3.2. Representation of Solutions. 3.3. Bifurcations. 4. Injected Oscillators and Frequency Dividers. 4.1. Introduction. 4.2. Injection-Locked Oscillators. 4.3. Frequency Dividers. 4.4. Subharmonically and Ultrasubharmonically Injection-Locked Oscillators. 4.5. Self-Oscillating Mixers. 5. Nonlinear Circuit Simulation. 5.1. Introduction. 5.2. Time-Domain Integration. 5.3. Fast Time-Domain Techniques. 5.4. Harmonic Balance. 5.5. Harmonic Balance Analysis of Autonomous and Synchronized Circuit. 5.6. Envelope Transient. 5.7. Conversion Matrix Approach. 6. Stability Analysis Using Harmonic Balance. 6.1. Introduction. 6.2. Local Stability Analysis. 6.3. Stability Analysis of Free-Running Oscillators. 6.4. Solution Curves Versus a Circuit Parameter. 6.5.Global Stability Analysis. 6.6. Bifurcation Synthesis and Control. 7. Noise Analysis Using Harmonic Balance. 7.1. Introduction. 7.2. Noise in Semiconductor Devices. 7.3. Decoupled Analysis of Phase and Amplitude Perturbations in a Harmonic Balance System. 7.4. Coupled Phase and Amplitude Noise Calculation. 7.5. Carrier Modulation Approach. 7.6. Conversion Matrix Approach. 7.7. Noise in Synchronized Oscillators. 8. Harmonic Balance Techniques for Oscillator Design. 8.1. Introduction. 8.2. Oscillator Synthesis. 8.3. Design of Voltage-Controlled Oscillators. 8.4. Maximization of Oscillator Efficiency. 8.5. Control of Oscillator Transients. 8.6. Phase Noise Reduction. 9. Stabilization Techniques for Phase Noise Reduction. 9.1. Introduction. 9.2. Self-Injection Topology. 9.3. Use of High-Q Resonators. 9.4. Stabilization Loop. 9.5. Transistor-Based Oscillators. 10. Coupled-Oscillator Systems. 10.1. Introduction. 10.2. Oscillator Systems with Global Coupling. 10.3. Coupled-Oscillator Systems for Beam Steering. 11. Simulation Techniques for Frequency-Divider Design. 11.1. Introduction. 11.2. Types of frequency dividers. 11.3. Design of Transistor-Based Regenerative Frequency Dividers. 11.4. Design of Harmonic Injection Dividers. 11.5. Extension of the Techniques to Subharmonic Injection Oscillators. 12. Circuit Stabilization. 12.1. Introduction. 12.2. Unstable Class AB Amplifier Using Power Combiners. 12.3. Unstable Class E/F Amplifier. 12.4. Unstable Class E Amplifier. 12.5. Stabilization of Oscillator Circuits. 12.6. Stabilization of Multifunction MMIC Chips. Index.
£152.06
John Wiley & Sons Inc Unconventional Nanopatterning Techniques and
Book SynopsisPatterning or lithography is at the core of modern science and technology and cuts across all disciplines. With the emergence of nanotechnology, conventional methods based on electron beam lithography and extreme ultraviolet photolithography have become prohibitively expensive.Table of ContentsPREFACE xv I NANOPATTERNING TECHNIQUES 1 1 INTRODUCTION 3 2 MATERIALS 7 2.1 Introduction 7 2.2 Mold Materials and Mold Preparation 8 2.2.1 Soft Molds 8 2.2.2 Hard Molds 19 2.2.3 Rigiflex Molds 19 2.3 Surface Treatment and Modification 21 References 23 3 PATTERNING BASED ON NATURAL FORCE 27 3.1 Introduction 27 3.2 Capillary Force 28 3.2.1 Open-Ended Capillary 29 3.2.2 Closed Permeable Capillary 31 3.2.3 Completely Closed Capillary 40 3.2.4 Fast Patterning 43 3.2.5 Capillary Kinetics 45 3.3 London Force and Liquid Filament Stability 48 3.3.1 Patterning by Selective Dewetting 49 3.3.2 Liquid Filament Stability: Filling and Patterning 51 3.4 Mechanical Stress: Patterning of A Metal Surface 56 References 63 4 PATTERNING BASED ON WORK OF ADHESION 67 4.1 Introduction 67 4.2 Work of Adhesion 68 4.3 Kinetic Effects 71 4.4 Transfer Patterning 74 4.5 Subtractive Transfer Patterning 79 4.6 Transfer Printing 82 References 91 5 PATTERNING BASED ON LIGHT: OPTICAL SOFT LITHOGRAPHY 95 5.1 Introduction 95 5.2 System Elements 96 5.2.1 Overview 96 5.2.2 Elastomeric Photomasks 96 5.2.3 Photosensitive Materials 99 5.3 Two-Dimensional Optical Soft Lithography (OSL) 100 5.3.1 Two-Dimensional OSL with Phase Masks 100 5.3.2 Two-Dimensional OSL with Embossed Masks 104 5.3.3 Two-Dimensional OSL with Amplitude Masks 105 5.3.4 Two-Dimensional OSL with AmplitudePhase Masks 109 5.4 Three-Dimensional Optical Soft Lithography 110 5.4.1 Optics 111 5.4.2 Patterning Results 112 5.5 Applications 117 5.5.1 Low-Voltage Organic Electronics 117 5.5.2 Filters and Mixers for Microfluidics 118 5.5.3 High Energy Fusion Targets and Media for Chemical Release 118 5.5.4 Photonic Bandgap Materials 120 References 122 6 PATTERNING BASED ON EXTERNAL FORCE: NANOIMPRINT LITHOGRAPHY 129L. Jay Guo 6.1 Introduction 129 6.2 NIL MOLD 133 6.2.1 Mold Fabrication 133 6.2.2 Mold Surface Preparation 137 6.2.3 Flexible Fluoropolymer Mold 137 6.3 NIL Resist 138 6.3.1 Thermoplastic Resist 139 6.3.2 Copolymer Thermoplastic Resists 141 6.3.3 Thermal-Curable Resists 142 6.3.4 UV-Curable Resist 146 6.3.5 Other Imprintable Materials 148 6.4 The Nanoimprint Process 149 6.4.1 Cavity Fill Process 149 6.5 Variations of NIL Processes 152 6.5.1 Reverse Nanoimprint 152 6.5.2 Combined Nanoimprint and Photolithography 155 6.5.3 Roll-to-Roll Nanoimprint Lithography (R2RNIL) 156 6.6 Conclusion 159 References 160 7 PATTERNING BASED ON EDGE EFFECTS: EDGE LITHOGRAPHY 167Matthias Geissler, Joseph M. McLellan, Eric P. Lee and Younan Xia 7.1 Introduction 167 7.2 Topography-Directed Pattern Transfer 169 7.2.1 Photolithography with Phase-Shifting Masks 170 7.2.2 Use of Edge-Defined Defects in SAMs 172 7.2.3 Controlled Undercutting 175 7.2.4 Edge-Spreading Lithography 176 7.2.5 Edge Transfer Lithography 178 7.2.6 Step-Edge Decoration 180 7.3 Exposure of Nanoscale Edges 181 7.3.1 Fracturing of Thin Films 182 7.3.2 Sectioning of Encapsulated Thin Films 182 7.3.3 Thin Metallic Films along Sidewalls of Patterned Stamps 184 7.3.4 Topographic Reorientation 186 7.4 Conclusion and Outlook 187 References 188 8 PATTERNING WITH ELECTROLYTE: SOLID-STATE SUPERIONIC STAMPING 195Keng H. Hsu, Peter L. Schultz, Nicholas X. Fang, and Placid M. Ferreira 8.1 Introduction 195 8.2 Solid-State Superionic Stamping 197 8.3 Process Technology 199 8.4 Process Capabilities 203 8.5 Examples of Electrochemically Imprinted Nanostructures Using the S4 Process 208 Acknowledgments 211 References 211 9 PATTERNING WITH GELS: LATTICE-GAS MODELS 215Paul J. Wesson and Bartosz A. Grzybowski 9.1 Introduction 215 9.2 The RDF Method 218 9.3 Microlenses: Fabrication 218 9.4 Microlenses: Modeling Aspects 220 9.4.1 Modeling Using PDEs 220 9.4.2 Modeling Using Lattice-Gas Method 221 9.5 RDF at the Nanoscale 222 9.5.1 Nanoscopic Features from Counter-Propagating RD Fronts 222 9.5.2 Failure of Continuum Description 225 9.5.3 Lattice-Gas Models at the Nanoscale 227 9.6 Summary and Outlook 229 References 230 10 PATTERNING WITH BLOCK COPOLYMERS 233Jia-Yu Wang, Wei Chen, and Thomas P. Russell 10.1 Introduction 233 10.2 Orientation 235 10.2.1 Self-Assembling 235 10.2.2 Self-Directing 247 10.3 Long-Range 254 10.3.1 Solvent Annealing 254 10.3.2 Graphoepitaxy 256 10.3.3 Sequential, Orthogonal Fields 260 10.4 Nanoporous BCP Films 262 10.4.1 Ozonolysis 264 10.4.2 Thermal Degradation 264 10.4.3 UV Degradation 267 10.4.4 Selective Extraction 271 10.4.5 “Soft” Chemical Etch 272 10.4.6 Cleavable Junction 272 10.4.7 Solvent-Induced Film Reconstruction 274 References 276 11 PERSPECTIVE ON APPLICATIONS 291 II APPLICATIONS 293 12 SOFT LITHOGRAPHY FOR MICROFLUIDIC MICROELECTROMECHANICAL SYSTEMS (MEMS)AND OPTICAL DEVICES 295Svetlana M. Mitrovski, Shraddha Avasthy, Evan M. Erickson, Matthew E. Stewart, John A. Rogers, and Ralph G. Nuzzo 12.1 Introduction 295 12.2 Microfluidic Devices for Concentration Gradients 297 12.3 Electrochemistry and Microfluidics 300 12.4 PDMS and Electrochemistry 302 12.5 Optics and Microfluidics 306 12.6 Unconventional Soft Lithographic Fabrication of Optical Sensors 314 Acknowledgments 317 References 318 13 UNCONVENTIONAL PATTERNING METHODS FOR BIONEMS 325Pilnam Kim, Yanan Du, Ali Khademhosseini, Robert Langer, and Kahp Y. Suh 13.1 Introduction 325 13.2 Fabrication of Nanofluidic System for Biological Applications 326 13.2.1 Unconventional Methods for Fabrication of Nanochannel 326 13.2.2 Application of Nanofluidic System 332 13.3 Fabrication of Biomolecular Nanoarrays for Biological Applications 338 13.3.1 DNA Nanoarray 338 13.3.2 Protein Arrays 340 13.3.3 Lipid Array 345 13.4 Fabrication of Nanoscale Topographies for Tissue Engineering Applications 347 13.4.1 Nanotopography-Induced Changes in Cell Adhesion 347 13.4.2 Nanotopography-Induced Changes in Cell Morphology 348 References 349 14 MICRO TOTAL ANALYSIS SYSTEM 359Yuki Tanaka and Takehiko Kitamori 14.1 Introduction 359 14.1.1 Historical Backgrounds 359 14.2 Fundamentals on Microchip Chemistry 361 14.2.1 Characteristics of Liquid Microspace 361 14.2.2 Liquid Handling 362 14.2.3 Concepts of Micro Unit Operation and Continuous-Flow Chemical Processing 362 14.3 Key Technologies 365 14.3.1 Fabrication of Microchips 365 14.3.2 Patterning for Fluid Control 366 14.3.3 Detection 366 14.4 Applications 368 14.4.1 Synthesis 368 14.4.2 Cell Adhesion Control 369 14.4.3 Liquid Handling: Valve Using Wettability 370 References 372 15 COMBINATIONS OF TOP-DOWN AND BOTTOM-UP NANOFABRICATION TECHNIQUES AND THEIR APPLICATION TO CREATE FUNCTIONAL DEVICES 379Pascale Maury, David N. Reinhoudt, and Jurriaan Huskens 15.1 Introduction 379 15.2 Top-Down and Bottom-Up Techniques 380 15.2.1 Top-Down Techniques 380 15.2.2 Bottom-Up Techniques 383 15.2.3 Mixed Techniques 384 15.3 Combining Top-Down and Bottom-Up Techniques for High Resolution Patterning 385 15.3.1 Top-Down Nanofabrication and Polymerization 386 15.3.2 Top-Down Nanofabrication and Micelles 387 15.3.3 Top-Down Nanofabrication and Block Copolymer Assembly 387 15.3.4 Top-Down Nanofabrication and NP Assembly 389 15.3.5 Top-Down Nanofabrication and Layer-by-Layer Assembly 392 15.4 Applicaion of Combined Top-Down and Bottom-Up Nanofabrication for Creating Functional Devices 397 15.4.1 Photonic Crystal Devices 397 15.4.2 Protein Assays 400 References 406 16 ORGANIC ELECTRONIC DEVICES 419 16.1 Introduction 419 16.2 Organic Light-Emitting Diodes 420 16.3 Organic Thin Film Transistors 429 References 439 17 INORGANIC ELECTRONIC DEVICES 445 17.1 Introduction 445 17.2 Inorganic Semiconductor Materials for Flexible Electronics 446 17.2.1 “Bottom-Up” Approaches 447 17.2.2 “Top-Down” Approaches 449 17.3 Soft Lithography Techniques for Generating Inorganic Electronic Systems 452 17.3.1 Micromolding in Capillaries 453 17.3.2 Imprint Lithography 454 17.3.3 Dry Transfer Printing 454 17.4 Fabrication of Electronic Devices 459 17.4.1 Transistors on Rigid Substrates via MIMIC Processing 459 17.4.2 Flexible Inorganic Transistors 459 17.4.3 Flexible Integrated Circuits 463 17.4.4 Heterogeneous Electronics 466 17.4.5 Stretchable Electronics 469 References 475 18 MECHANICS OF STRETCHABLE SILICON FILMS ON ELASTOMERIC SUBSTRATES 483Hanqing Jiang, Jizhou Song, Yonggang Huang, and John A. Rogers 18.1 Introduction 483 18.2 Buckling Analysis of Stiff Thin Ribbons on Compliant Substrates 484 18.3 Finite-Deformation Buckling Analysis of Stiff Thin Ribbons on Compliant Substrates 488 18.4 Edge Effects 495 18.5 Effect of Ribbon Width and Spacing 498 18.6 Buckling Analysis of Stiff Thin Membranes on Compliant Substrates 502 18.6.1 One-Dimensional Buckling Mode 504 18.6.2 Checkerboard Buckling Mode 506 18.6.3 Herrington Buckling Mode 506 18.7 Precisely Controlled Buckling of Stiff Thin Ribbons on Compliant Substrates 507 18.8 Concluding Remarks 512 Acknowledgments 512 References 512 19 MULTISCALE FABRICATION OF PLASMONIC STRUCTURES 515Joel Henzie, Min H. Lee, and Teri W. Odom 19.1 Introduction 515 19.1.1 Brief Primer on Surface Plasmons 517 19.1.2 Conventional Methods to Plasmonic Structures 518 19.2 Soft Lithography and Metal Nanostructures 518 19.3 A Platform for Multiscale Patterning 520 19.3.1 Soft Interference Lithography: Patterns on a Nanoscale Pitch 520 19.3.2 Phase-Shifting Photolithography: Patterns on a Microscale Pitch 520 19.3.3 PEEL: Transferring Photoresist Patterns to Plasmonic Materials 521 19.4 Subwavelength Arrays of Nanoholes: Plasmonic Materials 522 19.4.1 Infinite Arrays of Nanoholes 523 19.4.2 Finite Arrays (Patches) of Nanoholes 525 19.5 Microscale Arrays of Nanoscale Holes 526 19.6 Plasmonic Particle Arrays 528 19.6.1 Metal and Dielectric Nanoparticles 528 19.6.2 Anisotropic Nanoparticles 531 19.6.3 Pyramidal Nanostructures 531 Acknowledgments 533 References 533 20 A RIGIFLEX MOLD AND ITS APPLICATIONS 539Se-Jin Choi, Tae-Wan Kim, and Seung-Jun Baek 20.1 Introduction 539 20.2 Modulus-Tunable Rigiflex Mold 540 20.3 Applications of Rigiflex Mold 544 20.3.1 From Nanoimprint to Microcontact Printing 544 20.3.2 Rapid Flash Patterning for Residue-Free Patterning 547 20.3.3 Continuous Rigiflex Imprinting 549 20.3.4 Soft Molding Application 553 20.3.5 Capillary Force Lithography Applications 556 20.3.6 Transfer Fabrication Technique 558 References 561 21 NANOIMPRINT TECHNOLOGY FOR FUTURE LIQUID CRYSTAL DISPLAY 565Jong M. Kim, Hwan Y. Choi, Moon-G. Lee, Seungho Nam, Jin H. Kim, Seongmo Whang, Soo M. Lee, Byoung H. Cheong, Hyuk Kim, Ji M. Lee, and In T. Han 21.1 Introduction 565 21.2 Holographic LGP 569 21.2.1 Design and Properties of Holographic LGP 570 21.2.2 NI Technology for the Holographic LGP 572 21.3 Polarized LGP 573 21.3.1 Design and Properties of Polarized LGP 574 21.3.2 Fabrication of the Polarized LGP 575 21.3.3 Optical Performance of the Polarized LGP 576 21.4 Reflective Polarizer: Wire Grid Polarizer 579 21.4.1 Design and Properies of WGP 580 21.4.2 Fabrication and Applications 581 21.5 Transflective Display 585 21.5.1 Design and Optical Properties of Reflecting Pattern 587 21.5.2 Fabrication of the Reflecting Pattern 588 References 592 INDEX 595
£138.56
John Wiley & Sons Inc Fundamentals of RF and Microwave Transistor
Book SynopsisIncludes extensive design information in the form of equations, tables, graphs and examples. Offers an in-depth study of amplifiers. Simple design equations are included to help understand design concepts. Practical and simple to understand examples with over 70 fully solved.Table of ContentsForeword. Preface. Chapter 1: Introduction. 1.1 Transistor Amplifier. 1.2 Early History of Transistor Amplifiers. 1.3 Benefits of Transistor Amplifiers. 1.4 Transistors. 1.5 Design of Amplifiers. 1.6 Amplifier Manufacturing Technologies. 1.7 Applications of Amplifiers. 1.8 Amplifier Cost. 1.9 Current Trends. 1.10 Book Organization. References. Chapter 2: Linear Network Analysis. 2.1 Impedance Matrix. 2.2 Admittance Matrix. 2.3 ABCD Parameters. 2.4 S-Parameters. 2.5 Relationships Between Various 2-Port Parameters. References. Problems. Chapter 3: Amplifier Characteristics and Definitions. 3.1 Bandwidth. 3.2 Power Gain. 3.3 Input and Output VSWR. 3.4 Output Power. 3.5 Power Added Efficiency. 3.6 Intermodulation Distortion. 3.7 Harmonic Power. 3.8 Peak-to-Average Ratio. 3.9 Combiner Efficiency. 3.10 Noise Characterization. 3.11 Dynamic Range. 3.12 Multi-Stage Amplifier Characteristics. 3.13 Gate and Drain Pushing Factors. 3.14 Amplifier Temperature Coefficient. 3.15 Mean Time To Failure. References. Problems. Chapter 4: Transistors. 4.1 Transistor Types. 4.2 Si Bipolar Transistor. 4.3 GaAs MESFET. 4.4 Hetrojunction Field Effect Transistor. 4.5 Hetrojunction BipolarTransistors. 4.6 MOSFET. References. Problems. Chapter 5: Transistor Models. 5.1 Transistor Model Types. 5.2 MESFET Models. 5.3 pHEMT Models. 5.4 HBT Model. 5.5 MOSFET Models. 5.6 BJT Models. 5.7 Transistor Model Scaling. 5.8 Source- and Load-Pull Data. 5.9 Temperature Dependent Models. References. Problems. Chapter 6: Matching Network Components. 6.1 Impedance Matching Elements. 6.2 Transmission Lines Matching Elements. 6.3 Lumped Elements. 6.4 Bond Wire Inductors. 6.5 Broadband Inductors. References. Problems. Chapter 7: Impedance Matching Techniques. 7.1 One-Port and Two-Port Networks. 7.2 Narrowband Matching Techniques. 7.3 Wideband Matching Techniques. References. Problems. Chapter 8: Amplifier Classes and Analyses. 8.1 Classes of Amplifiers. 8.2 Analysis of Class-A Amplifiers. 8.3 Analysis of Class-B Amplifiers. 8.4 Analysis of Class-C Amplifiers. 8.5 Analysis of Class-E Amplifiers. 8.6 Analysis of Class-F Amplifiers. 8.7 Comparison Between Various Amplifier Classes. References. Problems. Chapter 9: Amplifier Design Methods. 9.1 Amplifier Design. 9.2 Amplifier Design techniques. 9.3 Matching Networks. 9.4 Amplifier Design Examples. 9.5 Silicon Based Handset Amplifier Design. References. Problems. Chapter 10: High-Efficiency Amplifier Techniques. 10.1 High-Efficiency Design. 10.2 Harmonic Reaction Amplifier. 10.3 Harmonic Injection Technique. 10.4 Harmonic Control Amplifier. 10.5 High-PAE Design Considerations. References. Problems. Chapter 11: Broadband Amplifier Techniques. 11.1 Transistor Bandwidth Limitations. 11.2 Broadband Amplifier Techniques. 11.3 Broadband Power Amplifier Design Considerations. References. Problems. Chapter 12: Linearization Techniques. 12.1 Nonlinear Analysis. 12.2 Phase Distortion. 12.3 Linearization of Power Amplifiers. 12.4 Efficiency Enhancement Techniques for Linear Amplifiers. 12.5 Linear Amplifier Design Considerations. 12.6 Linear Amplifier Design Examples. References. Problems. Chapter 13: High-Voltage Power Amplifier Design. 13.1 Performance Overview of High-Voltage Transistors. 13.2 High-Voltage Transistors. 13.3 High-Power Amplifier Design Considerations. 13.4 Power Amplifier Design Examples. 13.5 Broadband HV Amplifiers. 13.6 Series FET Amplifiers. References. Problems. Chapter 14: Hybrid Amplifiers. 14.1 Hybrid Amplifier Technologies. 14.2 Printed Circuit Boards. 14.3 Hybrid Integrated Circuits. 14.4 Design of Internally Matched Power Amplifiers. 14.5 Low-Noise Amplifiers. 14.6 Power Amplifiers. References. Problems. Chapter 15: Monolithic Amplifiers. 15.1 Advantages of Monolithic Amplifiers. 15.2 Monolithic IC Technology. 15.3 MMIC Design. 15.4 Design Examples. 15.5 CMOS Fabrication. References. Problems. Chapter 16: Thermal Design. 16.1 Thermal Basics. 16.2 Transistor Thermal Design. 16.3 Amplifier Thermal Design. 16.4 Pulsed Operation. 16.5 Heat Sink Design. 16.6 Thermal Resistance Measurement. References. Problems. Chapter 17: Stability Analyses. 17.1 Even-Mode Oscillations. 17.2 Odd-Mode Oscillations. 17.3 Parametric Oscillations. 17.4 Spurous Parametric Oscillations. 17.5 Low-Frequency Oscillations. References. Problems. Chapter 18: Biasing Networks. 18.1 Biasing of Transistors. 18.2 Biasing Network Design Considerations. 18.3 Self-Bias Technique. 18.4 Biasing Multi-Stage Amplifiers. 18.5 Biasing Circuitry for Low-Frequency Stabilization. 18.6 Biasing Sequence. References. Problems. Chapter 19: Power Combining. 19.1 Device-Level Power Combining. 19.2 Circuit-Level Power Combining. 19.3 Power Dividers, Hybrids and Couplers. 19.4 N-Way Combiners. 19.5 Corporate Structures. 19.6 Power Handling of Isolation Resistors. 19.7 Spatial Power Combiners. 19.8 Comparison of Power Combining Schemes. References. Problems. Chapter 20: Integrated Function Amplifiers. 20.1 Integrated limiter/LNA. 20.2 Transmitter Chain. 20.3 Cascading of Amplifiers. References. Problems. Chapter 21: Amplifier Packages. 21.1 Amplifier Packaging Overview. 21.2 Materials for Packages. 21.3 Ceramic Package Design. 21.4 Plastic Package Design. 21.5 Package Assembly. 21.6 Thermal Considerations. 21.7 CAD Tools For Packages. 21.8 Power Amplifier Modules. References. Problems. Chapter 22: Transistor and Amplifier Measurements. 22.1 Transistor Measurements. 22.2 Amplifier Measurements. 22.3 Distortion Measurements. 22.4 Phase Noise Measurement. 22.5 Recovery Time Measurement. References. Problems. Appendix A: Physical Constants and Other Data. Appendix B: Units and Symbols. Appendix C: Frequency Band Designation. Appendix D: Decibel Units - (dB). Appendix E: Mathematical Relations. Appendix F: Smith Chart. Appendix G: Graphical Symbols. Appendix H: Acronyms and Abbreviations. Appendix I: List Of Symbols. Appendix J: Multiple Access and Modulation Techniques. Index.
£143.95
John Wiley & Sons Inc Design and Realizations of Miniaturized Fractal
Book SynopsisAn in-depth survey of the design and REALIZATIONS of miniaturized fractal microwave and RF filters Engineers are continually searching for design methods that can satisfy the ever-increasing demand for miniaturization, accuracy, reliability, and fast development time. Design and Realizations of Miniaturized Fractal RF and Microwave Filters provides RF and microwave engineers and researchers, advanced graduate students, and wireless and telecommunication engineers with the knowledge and skills to design and realize miniaturized fractal microwave and RF filters. This book is an essential resource for the realization of portable and cellular phones, WiFi, 3G and 4G, and satellite networks. The text focuses on the synthesis and fabrication of miniaturized fractal filters with symmetrical and asymmetrical frequency characteristics in the C, X and Ku bands, though applications to other frequency bands are considered. Readers will find helpful guidance on: MTable of ContentsFOREWORD. PREFACE. 1 MICROWAVE FILTER STRUCTURES. 1.1 Background. 1.2 Cavity Filters. 1.3 Planar Filters. 1.4 Planar Filter Technology. 1.5 Active Filters. 1.6 Superconductivity or HTS Filters. 1.7 Periodic Structure Filters. 1.8 SAW Filters. 1.9 Micromachined Filters. 1.10 Summary. References. 2 IN-LINE SYNTHESIS OF PSEUDO-ELLIPTIC FILTERS. 2.1 Introduction. 2.2 Approximation and Synthesis. 2.3 Chebyshev Filters. 2.4 Pseudo-elliptic Filters. 2.5 Prototype Synthesis Examples. 2.6 Theoretical Coupling Coefficients and External Quality Factors. References. 3 SUSPENDED SUBSTRATE STRUCTURE. 3.1 Introduction. 3.2 Suspended Substrate Technology. 3.3 Unloaded Quality Factor of a Suspended Substrate Resonator. 3.4 Coupling Coefficients of Suspended Substrate Resonators. 3.5 Enclosure Design Considerations. References. 4 MINIATURIZATION OF PLANAR RESONATORS USING FRACTAL ITERATIONS. 4.1 Introduction. 4.2 Miniaturization of Planar Resonators. 4.3 Fractal Iteration Applied to Planar Resonators. 4.4 Minkowski Resonators. 4.5 Hibert Resonators. References. 5 DESIGN AND REALIZATIONS OF MEANDERED LINE FILTERS. 5.1 Introduction. 5.2 Third-order Pseudo-elliptic Filters with Transmission Zero on the Right. 5.3 Third-order Pseudo-elliptic Filters with Transmission Zero on the Left. References. 6 DESIGN AND REALIZATIONS OF HILBERT FILTERS. 6.1 Introduction. 6.2 Design of Hilbert Filters. 6.3 Realizations and Measured Performance. References. 7 DESIGN AND REALIZATION OF DUAL-MODE MINKOWSKI FILTERS. 7.1 Introduction. 7.2 Study of Minkowski Dual-Mode Resonators. 7.3 Design of Fourth-Order Pseudo-elliptic Filters with Two Transmission Zeros. 7.4 Realization and Measured Performance. References. APPENDIX 1: Equivalence Between J and K Lowpass Prototypes. APPENDIX 2: Extraction of the Unloaded Quality Factor of Suspended Substrate Resonators. INDEX.
£90.86
John Wiley & Sons Inc Synchronization and Arbitration in Digital
Book SynopsisToday's networks of processors on and off chip, operating with independent clocks, need effective synchronization of the data passing between them for reliability. When two or more processors request access to a common resource, such as a memory, an arbiter has to decide which request to deal with first.Table of ContentsPreface. List of Contributors. Acknowledgements. 1. Synchronization, Arbitration and Choice. 1.1 Introduction. 1.2 The Problem of Choice. 1.3 Choice in Electronics. 1.4 Arbitration. 1.5 Continuous and Discrete Quantities. 1.6 Timing. 1.7 Book Structure. PART I. 2. Modelling Metastability. 2.1 The Synchronizer. 2.2 Latch Model. 2.3 Failure Rates. 2.3.1 Event Histograms and MTBF. 2.4 Latches and Flip-flops. 2.5 Clock Back Edge. 3. Circuits. 3.1 Latches and Metastability Filters. 3.2 Effects of Filtering. 3.3 The Jamb Latch. 3.3.1 Jamb Latch Flip-flop. 3.4 Low Coupling Latch. 3.5 The Q-flop. 3.6 The MUTEX. 3.7 Robust Synchronizer. 3.8 The Tri-flop. 4. Noise and its Effects. 4.1 Noise. 4.2 Effect of Noise on a Synchronizer. 4.3 Malicious Inputs. 4.3.1 Synchronous Systems. 4.3.2 Asynchronous Systems. 5. Metastability Measurements. 5.1 Circuit Simulation. 5.1.1 Time Step Control. 5.1.2 Long-term τ. 5.1.3 Using Bisection. 5.2 Synchronizer Flip-flop Testing. 5.3 Rising and Falling Edges. 5.4 Delay-based Measurement. 5.5 Deep Metastability. 5.6 Back Edge Measurement. 5.7 Measure and Select. 5.7.1 Failure Measurement. 5.7.2 Synchronizer Selection. 6. Conclusions Part I. PART II. 7. Synchronizers in Systems. 7.1 Latency and Throughput. 7.2 FIFO Synchronizer. 7.3 Avoiding Synchronization. 7.4 Predictive Synchronizers. 7.5 Other Low-latency Synchronizers. 7.5.1 Locally Delayed Latching (LDL). 7.5.2 Speculative Synchronization. 7.6 Asynchronous Communication Mechanisms (ACM). 7.6.1 Slot Mechanisms. 7.6.2 Three-slot Mechanism. 7.6.3 Four-slot Mechanism. 7.6.4 Hardware Design and Metastability. 7.7 Some Common Synchronizer Design Issues. 7.7.1 Unsynchronized Paths. 7.7.2 Moving Metastability Out of Sight. 7.7.3 Multiple Synchronizer Flops. 8. Networks and Interconnects. 8.1 Communication on Chip. 8.1.1 Comparison of Network Architectures. 8.2 Interconnect Links. 8.3 Serial Links. 8.3.1 Using One Line. 8.3.2 Using Two Lines. 8.4 Differential Signalling. 8.5 Parallel Links. 8.5.1 One Hot Codes. 8.5.2 Transition Signaling. 8.5.3 n of m Codes. 8.5.4 Phase Encoding. 8.5.5 Time Encoding. 8.6 Parallel Serial Links. 9. Pausible and Stoppable Clocks in GALS. 9.1 GALS Clock Generators. 9.2 Clock Tree Delays. 9.3 A GALS Wrapper. 10. Conclusions Part II. PART III. 11. Arbitration. 11.1 Introduction. 11.2 Arbiter Definition. 11.3 Arbiter Applications, Resource Allocation Policies and Common Architectures. 11.4 Signal Transition Graphs, Our Main Modelling Language. 12. Simple Two-way Arbiters. 12.1 Basic Concepts and Conventions. 12.1.1 Two-phase or Non-return-to-zero (NRZ) Protocols. 12.1.2 Four-phase or Return-to-zero (RTZ) Protocols. 12.2 Simple Arbitration Between Two Asynchronous Requests. 12.3 Sampling the Logic Level of an Asynchronous Request. 12.4 Summary of Two-way Arbiters. 13. Multi-way Arbiters. 13.1 Multi-way MUTEX Using a Mesh. 13.2 Cascaded Tree Arbiters. 13.3 Ring-based Arbiters. 14. Priority Arbiters. 14.1 Introduction. 14.2 Priority Discipline. 14.3 Daisy-chain Arbiter. 14.4 Ordered Arbiter. 14.5 Canonical Structure of Priority Arbiters. 14.6 Static Priority Arbiter. 14.7 Dynamic Priority Arbiter. 15. Conclusions Part III. References. Index.
£95.36
John Wiley & Sons Inc ESD
Book SynopsisElectrostatic discharge (ESD) failure mechanisms continue to impact semiconductor components and systems as technologies scale from micro- to nano-electronics. This book studies electrical overstress, ESD, and latchup from a failure analysis and case-study approach. It provides a clear insight into the physics of failure from a generalist perspective, followed by investigation of failure mechanisms in specific technologies, circuits, and systems. The book is unique in covering both the failure mechanism and the practical solutions to fix the problem from either a technology or circuit methodology. Look inside for extensive coverage on: failure analysis tools, EOS and ESD failure sources and failure models of semiconductor technology, and how to use failure analysis to design more robust semiconductor components and systems; electro-thermal models and technologies; the state-of-the-art technologies discussed include CMOS, BiCMOS, silicon on insulator (SOTable of ContentsAbout the Author. Preface. Acknowledgments. 1 Failure Analysis and ESD. 1.1 Introduction. 1.2 ESD Failure: How Do Micro-electronic Devices Fail?. 1.3 Sensitivity of Semiconductor Components. 1.4 How Do Semiconductor Chips Fail––Are the Failures Random or Systematic?. 1.5 Closing Comments and Summary. Problems. References. 2 Failure Analysis Tools, Models, and Physics of Failure. 2.1 FA Techniques for Evaluation of ESD Events. 2.2 FA Tools. 2.3 ESD Simulation: ESD Pulse Models. 2.4 Electro-Thermal Physical Models. 2.5 Statistical Models for ESD Prediction. 2.6 Closing Comments and Summary. Problems. References. 3 CMOS Failure Mechanisms. 3.1 Tables of CMOS ESD Failure Mechanisms. 3.2 LOCOS Isolation-Defined CMOS. 3.3 Shallow Trench Isolation (STI). 3.4 Polysilicon-Defined Devices. 3.5 Lateral Diode with Block Mask. 3.6 MOSFETs. 3.7 Resistors. 3.8 Interconnects: Wires, Vias, and Contacts. 3.9 ESD Failure in CMOS Nanostructures. 3.10 Closing Comments and Summary. Problems. References. 4 CMOS Circuits: Receivers and Off-Chip Drivers. 4.1 Tables of CMOS Receiver and OCD ESD Failure Mechanisms. 4.2 Receiver Circuits. 4.3 Receivers Circuits with ESD Networks. 4.4 Receiver Circuits with Half-Pass Transmission Gate. 4.5 Receiver with Full-Pass Transmission Gate. 4.6 Receiver, Half-Pass Transmission Gate, and Keeper Network. 4.7 Receiver Circuit with Pseudo-zero VT Half-Pass Transmission Gate. 4.8 Receiver with Zero VT Transmission Gate. 4.9 Receiver Circuits with Bleed Transistors. 4.10 Receiver Circuits with Test Functions. 4.11 Receiver with Schmitt Trigger Feedback Networks. 4.12 Off-Chip Drivers. 4.13 Single NFET Pull-down OCD. 4.14 Series Cascode MOSFETs. 4.15 I/O Design Considerations and ESD Parasitic Failure Mechanisms. 4.16 Closing Comments and Summary. Problems. References. 5 CMOS Integration. 5.1 Table of CMOS Integration ESD Failure Mechanisms. 5.2 Architecture and Design Synthesis-Related Failures. 5.3 Alternate Current Loop. 5.4 Chip Capacitance. 5.5 ESD Power Clamps. 5.6 Intra- and Inter-domain ESD Protection. 5.7 Split Ground Configurations. 5.8 Mixed Voltage Interface. 5.9 Mixed Signal Interface. 5.10 Inter-domain Signal Line ESD Failures. 5.11 Decoupling Capacitors. 5.12 System Clock and Phase-Locked Loop. 5.13 Fuse Networks. 5.14 Bond Pads. 5.15 MOSFET Gate Structure. 5.16 Fill Shapes. 5.17 No Connects. 5.18 Test Circuitry. 5.19 Multi-chip Systems. 5.20 CMOS Latchup Failures. 5.21 Closing Comments and Summary. Problems. References. 6 SOI ESD Failure Mechanisms. 6.1 Tables of SOI Device and Integration ESD Failure Mechanisms. 6.2 SOI N-channel MOSFETs. 6.3 SOI Diodes. 6.4 SOI Buried Resistors. 6.5 SOI Failure Mechanisms in 150 nm Technology. 6.6 SOI ESD Failure Mechanisms in 45 nm Technology. 6.7 SOI ESD Failure Mechanisms in 32 nm Technology. 6.8 SOI ESD Failure Mechanisms in 22 nm Technology and the Future. 6.9 SOI Design Synthesis and ESD Failure Mechanisms. 6.10 SOI Integration: ESD Failure Mechanisms. 6.11 Closing Comments and Summary. Problems. References. 7 RF CMOS and ESD. 7.1 Tables of RF CMOS ESD Failure Mechanisms. 7.2 RF MOSFET. 7.3 RF Shallow Trench Isolation Diode. 7.4 RF Polysilicon Gated Diode. 7.5 Silicon-Controlled Rectifier. 7.6 Schottky Barrier Diodes. 7.7 Capacitors. 7.8 Resistors. 7.9 Inductors. 7.10 Examples of RF ESD Circuit Failure Mechanisms. 7.11 Closing Comments and Summary. Problems. Reference. 8 Micro-electromechanical Systems. 8.1 Table of MEM Failure Mechanisms. 8.2 Electrostatically Actuated Devices. 8.3 Micro-mechanical Engines. 8.4 Torsional Ratcheting Actuator. 8.5 Electromagnetic Micro-power Generators. 8.6 MEM Inductors. 8.7 Electrostatically Actuated Variable Capacitor. 8.8 Micro-mechanical Switches. 8.9 RF MEM Switch. 8.10 Micro-mechanical Mirrors. 8.11 Electrostatically Actuated Torsional Micro-mirrors. 8.12 Closing Comments and Summary. Problems. References. 9 Gallium Arsenide. 9.1 Tables of GaAs-Based ESD Failure Mechanisms. 9.2 GaAs Technology. 9.3 GaAs Energy-to-failure and Power-to-failure. 9.4 GaAs ESD Failures in Active and Passive Elements. 9.5 GaAs HBT Devices. 9.6 GaAs HBT-Based Passive Elements. 9.7 GaAs PHEMT Devices. 9.8 GaAs Power Amplifiers. 9.9 InGaAs. 9.10 Gallium Nitride. 9.11 InP and ESD. 9.12 Closing Comments and Summary. Problems. References. 10 Smart Power, LDMOS, and BCD Technology. 10.1 Tables of LDMOS ESD Failure Mechanisms. 10.2 LOCOS-Defined LDMOS Devices. 10.3 STI-Defined LDMOS Devices. 10.4 STI-Defined Isolated LDMOS Transistors. 10.5 LDMOS Transistors: ESD Electrical Measurements. 10.6 LDMOS-Based ESD Networks. 10.7 LDMOS ESD Failure Mechanisms. 10.8 LDMOS Transistor Design Enhancement. 10.9 Latchup Events in LDMOS and BCD Technology. 10.10 Closing Comments and Summary. Problems. References. 11 Magnetic Recording. 11.1 Tables of Magnetic Recording Failure Mechanisms. 11.2 MR Heads. 11.3 Inductive Heads. 11.4 GMR Heads. 11.5 TMR Heads. 11.6 ESD Solutions. 11.7 Closing Comments and Summary. Problems. References. 12 Photo-masks and Reticles: Failure Mechanisms. 12.1 Table of Photo-masks ESD Failure Mechanisms. 12.2 Photo-mask Failure Mechanisms. 12.3 Photo-mask Inspection Tools. 12.4 Photo-mask ESD Characterization. 12.5 Electrical Breakdown Versus Gap Spacing. 12.6 Electrical Breakdown in Air: The Townsend Model. 12.7 Electric Breakdown in Air: Toepler’s Spark Law. 12.8 Air Breakdown: The Paschen Breakdown Model. 12.9 Paschen Curve Versus Reticle Breakdown Plot. 12.10 Electrical Model of Photo-mask Breakdown. 12.11 ESD Latent Damage. 12.12 ESD Damage for Single Versus Multiple Events. 12.13 ESD Damage to Anti-reflective Coating. 12.14 ESD Solutions in Photo-masks. 12.15 Closing Comments and Summary. Problems. References. Index.
£102.56
John Wiley & Sons Inc Computational Lithography
Book SynopsisThis is the first book to address the optimization of resolution enhancement techniques in optical lithography. It provides an in-depth discussion of RET tools that use model-based mathematical optimization approaches.Trade Review"Computational lithography draws from the rich theory of inverse problems, optics, optimization, and computational imaging; as such, the book is also directed to researchers and practitioners in these fields. " (Consumer Electronics Net, 15 March 2011)Table of ContentsPreface xi Acknowledgments xiii Acronyms xv 1 Introduction 1 1.1 Optical Lithography 1 1.1.1 Optical Lithography and Integrated Circuits 2 1.1.2 Brief History of Optical Lithography Systems 3 1.2 Rayleigh’s Resolution 5 1.3 Resist Processes and Characteristics 7 1.4 Techniques in Computational Lithography 10 1.4.1 Optical Proximity Correction 11 1.4.2 Phase-Shifting Masks 11 1.4.3 Off-Axis Illumination 14 1.4.4 Second-Generation RETs 15 1.5 Outline 16 2 Optical Lithography Systems 19 2.1 Partially Coherent Imaging Systems 19 2.1.1 Abbe’s Model 19 2.1.2 Hopkins Diffraction Model 22 2.1.3 Coherent and Incoherent Imaging Systems 24 2.2 Approximation Models 25 2.2.1 Fourier Series Expansion Model 25 2.2.2 Singular Value Decomposition Model 29 2.2.3 Average Coherent Approximation Model 32 2.2.4 Discussion and Comparison 34 2.3 Summary 36 3 Rule-Based Resolution Enhancement Techniques 37 3.1 RET Types 37 3.1.1 Rule-Based RETs 37 3.1.2 Model-Based RETs 38 3.1.3 Hybrid RETs 39 3.2 Rule-Based OPC 39 3.2.1 Catastrophic OPC 40 3.2.2 One-Dimensional OPC 40 3.2.3 Line-Shortening Reduction OPC 42 3.2.4 Two-Dimensional OPC 43 3.3 Rule-Based PSM 44 3.3.1 Dark-Field Application 44 3.3.2 Light-Field Application 45 3.4 Rule-Based OAI 46 3.5 Summary 47 4 Fundamentals of Optimization 48 4.1 Definition and Classification 48 4.1.1 Definitions in the Optimization Problem 48 4.1.2 Classification of Optimization Problems 49 4.2 Unconstrained Optimization 50 4.2.1 Solution of Unconstrained Optimization Problem 50 4.2.2 Unconstrained Optimization Algorithms 52 4.3 Summary 57 5 Computational Lithography with Coherent Illumination 58 5.1 Problem Formulation 59 5.2 OPC Optimization 62 5.2.1 OPC Design Algorithm 62 5.2.2 Simulations 64 5.3 Two-Phase PSM Optimization 65 5.3.1 Two-Phase PSM Design Algorithm 65 5.3.2 Simulations 68 5.4 Generalized PSM Optimization 72 5.4.1 Generalized PSM Design Algorithm 72 5.4.2 Simulations 75 5.5 Resist Modeling Effects 79 5.6 Summary 82 6 Regularization Framework 83 6.1 Discretization Penalty 84 6.1.1 Discretization Penalty for OPC Optimization 84 6.1.2 Discretization Penalty for Two-Phase PSM Optimization 86 6.1.3 Discretization Penalty for Generalized PSM Optimization 87 6.2 Complexity Penalty 93 6.2.1 Total Variation Penalty 93 6.2.2 Global Wavelet Penalty 94 6.2.3 Localized Wavelet Penalty 98 6.3 Summary 100 7 Computational Lithography with Partially Coherent Illumination 101 7.1 OPC Optimization 102 7.1.1 OPC Design Algorithm Using the Fourier Series Expansion Model 102 7.1.2 Simulations Using the Fourier Series Expansion Model 105 7.1.3 OPC Design Algorithm Using the Average Coherent Approximation Model 107 7.1.4 Simulations Using the Average Coherent Approximation Model 111 7.1.5 Discussion and Comparison 111 7.2 PSM Optimization 115 7.2.1 PSM Design Algorithm Using the Singular Value Decomposition Model 116 7.2.2 Discretization Regularization for PSM Design Algorithm 118 7.2.3 Simulations 118 7.3 Summary 122 8 Other RET Optimization Techniques 123 8.1 Double-Patterning Method 123 8.2 Post-Processing Based on 2D DCT 128 8.3 Photoresist Tone Reversing Method 131 8.4 Summary 135 9 Source and Mask Optimization 136 9.1 Lithography Preliminaries 137 9.2 Topological Constraint 140 9.3 Source–Mask Optimization Algorithm 141 9.4 Simulations 141 9.5 Summary 145 10 Coherent Thick-Mask Optimization 146 10.1 Kirchhoff Boundary Conditions 147 10.2 Boundary Layer Model 147 10.2.1 Boundary Layer Model in Coherent Imaging Systems 147 10.2.2 Boundary Layer Model in Partially Coherent Imaging Systems 151 10.3 Lithography Preliminaries 153 10.4 OPC Optimization 157 10.4.1 Topological Constraint 157 10.4.2 OPC Optimization Algorithm Based on BL Model Under Coherent Illumination 158 10.4.3 Simulations 159 10.5 PSM Optimization 162 10.5.1 Topological Constraint 162 10.5.2 PSM Optimization Algorithm Based on BL Model Under Coherent Illumination 165 10.5.3 Simulations 165 10.6 Summary 170 11 Conclusions and New Directions of Computational Lithography 171 11.1 Conclusion 171 11.2 New Directions of Computational Lithography 173 11.2.1 OPC Optimization for the Next-Generation Lithography Technologies 173 11.2.2 Initialization Approach for the Inverse Lithography Optimization 173 11.2.3 Double Patterning and Double Exposure Methods in Partially Coherent Imaging System 174 11.2.4 OPC and PSM Optimizations for Inverse Lithography Based on Rigorous Mask Models in Partially Coherent Imaging System 174 11.2.5 Simultaneous Source and Mask Optimization for Inverse Lithography Based on Rigorous Mask Models 174 11.2.6 Investigation of Factors Influencing the Complexity of the OPC and PSM Optimization Algorithms 174 Appendix A: Formula Derivation in Chapter 5 175 Appendix B: Manhattan Geometry 181 Appendix C: Formula Derivation in Chapter 6 182 Appendix D: Formula Derivation in Chapter 7 185 Appendix E: Formula Derivation in Chapter 8 189 Appendix F: Formula Derivation in Chapter 9 194 Appendix G: Formula Derivation in Chapter 10 195 Appendix H: Software Guide 199 References 217 Index 223
£95.36
John Wiley & Sons Inc Modelling Photovoltaic Systems Using PSPICE
Book SynopsisPhotovoltaics (PV), the direct conversion of light from the sun into electricity, is an increasingly important means of distributed power generation. Using SPICE, the tool of choice for circuits and electronics designers, this book highlights the increasing importance of modelling techniques in the quantitative analysis of PV systems.Table of ContentsForeword. Preface. Acknowledgements. Introduction to Photovoltaic Systems and PSpice. Spectral Response and Short-Circuit Current. Electrical Characteristics of the Solar Cell. Solar Cell Arrays, PV Modules and PV Generators. Interfacing PV Modules to Loads and Battery Modelling. Power Conditioning and Inverter Modelling. Standalone PV Systems. Grid-connected PV Systems. Small Photovoltaics. Annex 1 PSpice Files Used in Chapter 1. Annex 2 PSpice Files Used in Chapter 2. Annex 3 PSpice Files Used in Chapter 3. Annex 4 PSpice Files Used in Chapter 4. Annex 5 PSpice Files Used in Chapter 5. Annex 6 PSpice Files Used in Chapter 6. Annex 7 PSpice Files Used in Chapter 7. Annex 8 PSpice Files Used in Chapter 8. Annex 9 PSpice Files Used in Chapter 9. Annex 10 Summary of Solar Cell Basic Theory. Annex 11 Estimation of the Radiation in an Arbitrarily Oriented Surface. Index.
£153.85
John Wiley & Sons Inc Modelling Photovoltaic Systems Using PSpice
Book SynopsisPhotovoltaics (PV), the direct conversion of light from the sun into electricity, is an increasingly important means of distributed power generation. Using SPICE, the tool of choice for circuits and electronics designers, this book highlights the increasing importance of modelling techniques in the quantitative analysis of PV systems.Table of ContentsIntroduction to Photovoltaic Systems and Pspice Spectral Response and Short Circuit Current Electrical Characteristics of the Solar Cell Solar Cell Arrays PV Modules and PV Generators Interfacing PV Modules to Loads and Battery Modelling Power Conditioning and Inverter Modelling Stand - Alone PV Systems Grid Connected PV Systems Small Photovoltaics
£65.50
John Wiley & Sons Inc Advanced Circuits for Emerging Technologies
Book SynopsisCMOS technology is the dominant technology for fabricating integrated circuits (ICs or chips). It is reliable, manufacturable, low power, low cost, and most importantly, scalable. This authoritative CMOS circuit design book covers advanced circuits for emerging technologies, including digital VLSI, analog VLSI and VSLI memories.Table of ContentsPreface xiii Contributors xv Part I Digital Design and Power Management 1 Design in the Energy–Delay Space 3Massimo Alioto, Elio Consoli, and Gaetano Palumbo 1.1 Introduction 3 1.2 Energy and Delay Modeling 4 1.3 Energy–Delay Space Analysis and Hardware-Intensity 14 1.4 Energy-Efficient Design of Digital Circuits 20 1.5 Design of Energy-Efficient Pipelined Systems 29 1.6 Conclusion 36 References 37 2 Subthreshold Source-Coupled Logic 41Armin Tajalli and Yusuf Leblebici 2.1 Introduction 41 2.2 Ultralow Power CMOS Logic: Design and Tradeoffs 43 2.3 Subthreshold Source-Coupled Logic 47 2.4 Power-Frequency Scaling 51 2.5 Conclusions 53 References 55 3 Ultralow-Voltage Design of Nanometer CMOS Circuits for Smart Energy-Autonomous Systems 57David Bol 3.1 Introduction 57 3.2 Impact of Technology Scaling on Subthreshold MOSFET Characteristics 61 3.3 Scaling Trend of the Minimum-Energy Point 63 3.4 Practical Energy of Nanometer ULV Circuits under Robustness and Timing Constraints 69 3.5 Technology/Circuit Methodology and Roadmap for ULV Design in the Nanometer Era 75 3.6 Conclusion 78 References 79 4 Impairment-Aware Analog Circuit Design by Reconfiguring Feedback Systems 85Ping-Ying Wang 4.1 Introduction 86 4.2 Theorem of Impairment-Aware Analog Design in Feedback Systems 86 4.3 Practical Implementations 89 4.4 Measured Results 96 4.5 Conclusions 99 References 100 5 Rom-Based Logic Design: A Low-Power Design Perspective 103Bipul C. Paul 5.1 Introduction 103 5.2 RBL Design 105 5.3 RBL Adder 108 5.4 RBL Multiplier 111 5.5 Conclusions 116 References 117 6 Power Management: Enabling Technology 119Lou Hutter and Felicia James 6.1 Macroeconomic Drivers for Power Technologies 119 6.2 Market Trends 122 6.3 Application Examples 123 6.4 Technology Implications and Trends 124 6.5 Current Technologies and Capabilities 130 6.6 Specific Application Example 140 6.7 Emerging Technologies 142 6.8 Conclusion 143 References 143 7 Ultralow Power Management Circuit for Optimal Energy Harvesting in Wireless Body Area Network 147Yen Kheng Tan, Yuanjin Zheng, and Huey Chian Foong 7.1 Introduction 147 7.2 Wireless Body Area Network 148 7.3 Optimal Energy Harvesting System 159 7.4 Ultralow Power Management Integrated Circuit for Solar Energy Harvesting System 163 7.5 Conclusions 171 References 171 Part II Analog and RF design 8 Analog Circuit Design for SOI 177Andrew Marshall 8.1 SOI Devices 177 8.2 Partially Depleted SOI 178 8.3 FDSOI and FinFET 181 8.4 Device Considerations (FDSOI AND PDSOI) 181 8.5 Analog Circuit Building Blocks 184 8.6 Operational Amplifiers 189 8.7 Operational Transconductance Amplifier 193 8.8 Radio Frequency Low-Noise Amplifier 197 8.9 Mixers and Analog Multipliers 197 8.10 Analog to Digital and Digital to Analog Converters 201 8.11 Summary 204 References 204 9 Frequency Generation and Control with Self-Referenced CMOS Oscillators 207Michael S. McCorquodale, Nathaniel Gaskin, and Vidyabhusan Gupta 9.1 Introduction 207 9.2 Self-Referenced CMOS Oscillators 211 9.3 Packaging 225 9.4 Conclusion 234 References 235 10 Synthesis of Static and Dynamic Translinear Circuits 239Bradley A. Minch 10.1 Translinear Circuits: What Is In a Name? 239 10.2 The Scope of Translinear Circuits 242 10.3 Static and Dynamic Translinear Circuit Synthesis 242 10.4 Static Translinear Circuit Synthesis Examples 250 10.5 Dynamic Translinear Circuit Synthesis Examples 260 References 272 11 Microwatt Power CMOS Analog Circuit Designs: Ultralow Power LSIS for Power-Aware Applications 277Ken Ueno and Tetsuya Hirose 11.1 Introduction 277 11.2 Subthreshold Characteristics in a MOSFET 279 11.3 Low-Power Voltage Reference Circuits 284 11.4 Low-Power Current Reference Circuits 293 11.5 Example of Power-Aware LSI Applications: CMOS Smart Sensor for Monitoring the Quality of Perishables 299 11.6 Conclusion and Discussion 308 References 310 12 High-Speed Current-Mode Data Drivers for Amoled Displays 313Yong-Joon Jeon and Gyu-Hyeong Cho 12.1 Introduction 313 12.2 Current-Mode Drivers in Representation of the Second-Generation Current Conveyor 316 12.3 Improved Transient Current Feed-Forward Output Buffer 317 12.4 Push-Pull Transient Current Feedforward Output Buffer 324 12.5 Conclusion 332 References 333 13 RF Transceivers for Wireless Applications 335Alireza Zolfaghari, Hooman Darabi, and Henrik Jensen 13.1 Transmitter Architectures 335 13.2 Cartesian Transmitters 336 13.3 Constant-Envelope Transmitters Using Phase Modulated Loops 339 13.4 Polar Transmitters 340 13.5 Case Studies 346 References 350 Part III Device Layout and Reliability 14 Technology-Aware Communication Architecture Design for Parallel Hardware Platforms 355Davide Bertozzi, Alessandro Strano, Daniele Ludovici, and Francisco Gilabert 14.1 Introduction 355 14.2 NoC Building Blocks: The Switch 358 14.3 NoC Connectivity Pattern 362 14.4 NoCs and the GALS Paradigm 372 14.5 Putting Everything Together: Technology-Aware Network Connectivity 385 14.6 Looking Forward: Mesochronous Synchronization 389 14.7 Conclusions 390 References 390 15 Design and Optimization of Integrated Transmission Lines on Scaled CMOS Technologies 393Federico Vecchi, Matteo Repossi, Wissam Eyssa, Paolo Arcioni, and Francesco Svelto 15.1 Introduction 393 15.2 Coplanar Waveguides 394 15.3 Shielded Transmission Lines 397 15.4 Accurate and Fast Analysis of Periodic Lines 402 15.5 Design and Experimental Results 406 15.6 Conclusions 411 References 413 16 On-Chip Surfing Interconnect 415Suwen Yang and Mark Greenstreet 16.1 Introduction 415 16.2 Surfing 417 16.3 Surfing DLLs 419 16.4 Pipelined Clock Forwarding 423 16.5 Source Synchronous Surfing 427 16.6 Surfing Handshakes 431 16.7 Summary 435 References 436 17 On-Chip Spiral Inductors with Integrated Magnetic Materials 439Wei Xu, Saurabh Sinha, Hao Wu, Tawab Dastagir, Yu Cao, and Hongbin Yu 17.1 Introduction 439 17.2 Previous Work 441 17.3 Magnetic Materials 443 17.4 Simulation Study 447 17.5 Device Fabrication 451 17.6 Measurement Results 453 17.7 Potential Applications of On-Chip Spiral Inductors with Magnetic Materials 455 17.8 Conclusion 458 References 458 18 Reliability of Nanoelectronic VLSI 463Milos Stanisavljevic, Alexandre Schmid, and Yusuf Leblebici 18.1 Introduction 463 18.2 Increased Defect Density and Reliability 464 18.3 Reliability Evaluation 466 18.4 Historically Important CAD Tools 467 18.5 Recent Progress 469 18.6 Monte Carlo Reliability Evaluation Tool 473 18.7 Fault-Tolerant Computing 476 18.8 Conclusions 476 References 477 19 Temperature Monitoring Issues in Nanometer CMOS Integrated Circuits 483Pablo Ituero and Marisa López-Vallejo 19.1 Introduction 483 19.2 From Where Does Heat Come in Nanometer Circuits? 485 19.3 Harmful Effects Due to Temperature in VLSI Chips 488 19.4 Temperature Sensing for DTM 493 19.5 Thermal Modeling 498 19.6 Thermal Sensor Placement and Allocation 500 19.7 Temperature Monitoring Networks 503 19.8 Conclusions 505 References 505 Part IV Circuit Testing 20 Low-Power Testing for Low-Power LSI Circuits 511Xiaoqing Wen and Yervant Zorian 20.1 Introduction 511 20.2 Test Power Problem in Logic LSI Testing 513 20.3 Basic Strategies to Test Power Reduction 515 20.4 Shift Power Reduction 517 20.5 Capture Power Reduction 519 20.6 Toward Next-Generation Low-Power Testing Solutions 522 20.7 Summary 525 References 526 21 Checkers for Online Self-Testing of Analog Circuits 529Haralampos-G. Stratigopoulos and Yiorgos Makris 21.1 Introduction 529 21.2 Time-Invariant Linear Circuits 531 21.3 Fully Differential Circuits 542 21.4 Conclusions 553 References 553 22 Design and Test of Robust CMOS RF and mm-Wave Radios 557Sleiman Bou-Sleiman and Mohammed Ismail 22.1 Introduction 557 22.2 Why Robust RF and mm-Wave ICs? 558 22.3 Design Methodology for First-Time-Right Radio SoCs 564 22.4 Robust RF and mm-Wave Radio Transceivers 571 22.5 Summary 578 References 579 23 Contactless Testing and Diagnosis Techniques 581Selahattin Sayil 23.1 Introduction 581 23.2 Electron-Beam Method 582 23.3 Photoemissive Probing 583 23.4 Electro-Optic Probing 584 23.5 Charge Density Probing 587 23.6 Photoexcitation Probe Techniques 588 23.7 Electric Force Microscopy 589 23.8 Capacitive Coupling Method 590 23.9 Dynamic Internal Testing of CMOS using Hot-Carrier Luminescence 591 23.10 All-Silicon Optical Contactless Testing of Integrated Circuits 592 23.11 Conclusion 596 References 596 Index 599
£125.96
John Wiley & Sons Inc Infrared Detectors and Systems 24 Wiley Series in
Book SynopsisThis text examines the theory and application of infrared detectors. It describes the optical detection process and the electronics involved in mimicking the eye. It further describes how well optical systems detect radiation.Table of ContentsPartial table of contents: Geometrical Optics. Radiometry. Optical-Detection Processes. Probability and Statistics for Optical Detection. Figures of Merit for Optical Detectors. Photovoltaic Detectors. Thermal Detectors. Schottky-Barrier Photodiodes. Infrared Search Systems. Modulation Transfer Function. Thermal-Imager Systems. Appendices. Index.
£180.86
John Wiley & Sons Inc Digital Design from Zero to One
Book SynopsisTakes a fresh look at basic digital design. From definition, to example, to graphic illustration, to simulation result, the book progresses through the main themes of digital design. Technically up-to-date, this book covers all the latest topics: Field programmable gate arrays, PALs and ROMs. The latest memory chips for SRAM and DRAM are shown. Software for creating the excitation equations of FSM are covered, as well as LogicWorks and Beige Bag PC and more.Table of ContentsCOMBINATIONAL LOGIC. From Numbers to Switches. Truth Tables and Boolean Algebra. Map and Table Methods for Minimizing Boolean Expressions. Programmable Circuits for Combinational Design. SEQUENTIAL DESIGN. Evolution of Flip-Flops. Synchronous Counters. Synchronous Finite State Machines. MASTERING DESIGN. Memory. Digital Communication and Serial Transmission. Arithmetic Hardware. Register Transfer Logic. Index.
£122.50
John Wiley & Sons Inc Fundamentals of Microwave Transmission Lines
Book SynopsisTransmission lines are basic components of electric power systems and are therefore basic elements in distributed circuit analysis and in microwave circuit design. This is a complete guide to solving microwave transmission problems. This book strives for clarity and rapid learning of material essential for distributed circuits.Table of ContentsIntroduction to Distributed Circuits. The Mathematics of Traveling Waves. Coupled Lines. Time Domain Topics. Sinusoidal Steady State. The Smith Chart. Single Frequency Matching. Index.
£174.56
John Wiley & Sons Inc Signal Integrity Effects in Custom IC and ASIC
Book SynopsisSingh provides hands-on and research knowledge to a broad audience to help them get past very serious design problems. It covers signal integrity effects in high performance radio frequency IC designs, and substrate coupling.Trade Review"In the era of System-on-Chip, when large portions of the overall system are integrated on one large chip, designers are facing increasingly challenging issues. For the first time, this book is taking a closer look at the signal integrity problems faced by both high-performance and cost-performance applications, digital and mixed-signal integrated circuits. System designers are given guidance in power distribution analysis, interconnect optimization, and mixed, digital-analog circuit integration challenges. Researchers and CAD engineers can get an in-depth view of the current and future requirements for full-chip CAD tools, on-chip transmission line designs, integrated passive components, and many other critical signal integrity issues. This book is bringing together a broad range of representative papers that will further the understanding both in the industrial and academic communities." (Alina Deutsch, Research Staff Member, T.J. Watson Research Center, International Business Machines) "Electrical integrity (or environment noise) is becoming the principal obstacle in system-on-a-chip design. Digital circuits create a very noisy environment in which other digital and analog circuits must function. This environmental noise comes about because of coupling through the interconnect, power supply, and substrate. This book surveys the latest literature on electrical integrity analysis and design and is, therefore, an invaluable resource for anyone designing systems-on-a-chip." (Kenneth L. Shepard, Professor, Columbia University) "The explosion of wireless communications that offer greater mobility and broadband communications that provide super fast access to the Internet have placed new demands on IC designers. The key to developing successful Systems on Chip designs that offer Analog and Mixed Signal capabilities is the approach used to extract and analyze the affects of parasitics on signal integrity. This book offers a tutorial guide to IC designers who want to move to the next level of chip design by unlocking the secrets of signal integrity." (Jake Buurma Senior Vice President, Worldwide Research & Development, Cadence Design Systems, Inc.) "As technology scales to .1 micron and below, second order effects due to physical phenomena that were not much visible before start playing a more and more significant role. So much so that well-established methodologies and tools are not providing the necessary level of confidence to the designer that her/his integrated circuit will perform as planned. The need for more accurate extraction and analysis is obvious when we observe horror stories about very hard to detect intermittent faults created by interactions among signals on different wires. There are two complementary approaches to the problem that come to mind as always when we go over the limit of previous methods - increase the accuracy of the analysis tools, and/or solve the problems by imposing constraints on the degrees of freedom left to the designer. This collection of papers covers both in details. It is the most comprehensive syllabus of important results for researchers and designers on the topic. I highly recommend to read it and to pay attention to the messages given by the papers of the collection." (Alberto Sangiovanni-Vincentelli, Professor, University of California Berkeley)Table of ContentsForeword. From the Early Days of CMOS to Today. Signal Integrity: A Problem for Design and CAD Engineers. Preface. Acknowledgments. Signal Integrity Effects in Systme-on-Chip Designs - A Designer's Perspective. Part 1: Interconnect Crosstalk. Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits. FastCap: A Multipole Accelerated 3-D Capacitance Extraction Program. Efficient Coupled Noise Estimation for On-Chip Interconnects. Switching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise. Digital Sensitivity: Predicting Signal Interaction using Functional Analysis. Crosstalk Reduction for VLSI. Noise-aware Repeater Insertion and Wire Sizing For On-Chip Interconnect Hierarchical Moment-Matching. Post Global Routing Crosstalk Synthesis. Minimum Crosstalk Channel Routing. Reducing Cross-Coupling among Interconnect Wires in Deep-Submicron Datapath Design. A Postprocessing Algorithm for Crosstalk-driven Wire Perturbation. Noise in Digital Dynamic CMOS Circuits. Design of Dynamic Circuits with Enhanced Noise Tolerance. Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. High Frequency Simulation and Characterization of Advanced Copper Interconnects. Static Noise Analysis for Digital Integrated Circuits in Partially-Depleted Silicon-On-Insulator Technology. Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. Part 2: Inductance Effects. On-Chip Wiring Design Challenges for Gigahertz Operation. IC Analyses Including Extracted Inductance Models. FASTHENRY: A Multipole-Accelerated 3-D Inductance Extraction Program. Full-Chip, Three-Dimensional, Shapes-Based RLC Extraction. On-Chip Inductance Modeling and Analysis. How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K. Figures of Merit to Characterize the Importance of On-Chip Inductance. Layout-Techniques for Minimizing On-Chip Interconnect Self Inductance. A Twisted-Bundle Layout Structure for Minimizing Inductive Coupling Noise. Part 3: Power Grid and Distribution Noise. Full-Chip Verification of UDSM Designs. Power Supply Noise in Future IC's: A Crystal Ball Reading. A Floorplan-based Planning Methodology for Power and Clock Distribution in ASICs. Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design. Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices. Full-Chip Signal Interconnect Analysis for Electromigration Reliability. Power Dissipation Analysis and Optimization of Deep Submicron CMOS Digital Circuits. Simulation and Optimization of the Power Distribution Network in VLSI Circuits. Design Strategies and Decoupling Techniques for Reducing the Effects of Electrical Interference in Mixed-Mode IC's. Design and Analysis of Power Distribution Networks in Power PC Microprocessors. Modeling the Power and Ground Effects of BGA Packages. Effects of Power/Ground Via Distribution on the Power/Ground Performance of C4/BGA Packages. Power Distribution Fidelity of Wirebond Compared to Flip Chip Devices in Grid Array Packages. Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers. Part 4: Substrate Noise. Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits. Principles of Substrate Crosstalk Generation in CMOS Circuits. Experimental Comparison of Substrate Noise Coupling Using Different Wafer Types. Modeling and Analysis of Substrate Coupling in Integrated Circuits. Fast Methods for Extraction and Sparsification of Substrate Coupling. SUBWAVE: A Methodology for Modeling Digital Substrate Noise Injection in Mixed-Signal ICs. Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation. Analysis of Ground-Bounce Induced Substrate Noise Coupling in a Low Resistive Bulk Epitaxial Process: Design Strategies to Minimize Noise Effects on a Mixed-Signal Chip. A Methodology for Measurement and Characterization of Substrate Noise in High Frequency Circuits. Measurement of Digital Noise in Mixed-Signal Integrated Circuits. Effects of Substrate Resistances on LNA Performance and a Bondpad Structure for Reducing the Effects in a Silicon Bipolar Technology. A Study of Oscillator Jitter Due to Supply and Substrate Noise. CMOS Technology Characterization for Analog and RF Design. Noise Reduction Is Crucial to Mixed-Signal ASIC Design Success (Parts I & II). Author Index. Subject Index. About the Editor.
£151.16
John Wiley & Sons Inc Devices for Integrated Circuits
Book SynopsisA detailed, modern introduction to semiconductors made in silicon and III-V compounds. This book develops the device physics of pn junctions, bipolar transistors, Schottky barriers, MOS capacitors, and MOS field-effect transistors (MOSFETs).Table of ContentsIntegrated Circuit Family Tree Electrons in Solids Carrier Transport and Recombination p-n Junctions: I-V Behavior p-n Junctions: Reverse Breakdown and Junction Capacitance Schottky-Barrier Devices MOS Capacitors MOS Field-Effect Transistors Bipolar Transistors Appendix I: Introduction to PSPICE
£244.76
John Wiley & Sons Inc Electronic Components
Book SynopsisThe definitive one-stop guide to selecting and using all types of electronic components, including. Resistors Capacitors Chokes, Inductors, and Transformers Delay Lines, Connectors, and Interconnection Devices Switches, Relays, and Contactors Wire and Cable Discrete Semiconductors Integrated Circuits.Table of ContentsThe Parts Selection Process. Resistors. Capacitors. Chokes, Coils, Inductors, and Transformers. Delay Lines. Connectors and Interconnection Devices. Switches. Relays and Contactors. Wire and Cable. Discrete Semiconductors. Integrated Circuits. Sources of Information, Specifications, and Parts. Standards/Trade Organizations. Thermistors. Index.
£216.86
John Wiley & Sons Inc LeastMeanSquare Adaptive Filters
Book SynopsisFrom elininating outside interference to separate data stream traveling together, filters are used for a range of applications in communications. The Least Mean Square (LMS) filter has established itself as the workhorse for the design of linear adaptive systems. This book deals with this topic.Trade Review"...strongly recommended for researchers working in the field of signal processing and its applications." (IEEE Circuits & Devices, January/February 2006)Table of ContentsContributors. Introduction (Simon Haykin). 1. On the Efficiency of Adaptive Algorithms (Berrnard Widrow and Max Kamenetsky). 2. Travelling-Wave Model of Long LMS Filters (Hans Butterweck). 3. Energy Conservation and the Learning Ability of LMS Adaptive Filters (Ali Sayed & Vitor H. Nascimento). 4. On the Robustness of LMS Filters (Babak Hassibi). 5. Dimension Analysis for Least-Mean-Square Algorithms (Iven M.Y. Mareels, et al.). 6. Control of LMS-Type Adaptive Filters (Eberhard Haensler and Gerhard Uwe Schmidt). 7. Affine Projection Algorithms (Steve Gay). 8. Proportionate Adaptation: New Paradigms in Adaptive Filters (Zhe Chen, et al.). 9. Steady-State Dynamic Weight Behavior in (N)LMS Adaptive Filters (A.A. (Louis) Beex and James R. Zeidler). 10. Error Whitening Wiener Filters: Theory and Algorithms (Jose Principe, et al.). Index.
£145.76
John Wiley & Sons Inc ComputerAided Design of Analog Integrated
Book SynopsisThe tools and techniques you need to break the analog design bottleneck! Ten years ago, analog seemed to be a dead-end technology. Today, System-on-Chip (SoC) designs are increasingly mixed-signal designs. With the advent of application-specific integrated circuits (ASIC) technologies that can integrate both analog and digital functions on a single chip, analog has become more crucial than ever to the design process. Today, designers are moving beyond hand-crafted, one-transistor-at-a-time methods. They are using new circuit and physical synthesis tools to design practical analog circuits; new modeling and analysis tools to allow rapid exploration of system level alternatives; and new simulation tools to provide accurate answers for analog circuit behaviors and interactions that were considered impossible to handle only a few years ago. To give circuit designers and CAD professionals a better understanding of the history and the current state of the art in the field, this volumTable of ContentsPreface ix Acknowledgments xi Part I Introduction to Analog CAD Part II Analog Synthesis Part III Symbolic Analysis Part IV Analog Layout Part V Analog Modeling Analysis Part VI Spec Simulation Part VII Analog Centering and Yield Optimization Part VIII Analog Test About the Editors 754
£154.76
John Wiley & Sons Inc Integrated Technology
Book SynopsisPresenting survey in Integrated Passive Component Technology, this title describes the processes available for creating integrated passives, measuring their properties, and applying them.Trade Review"…a comprehensive look at the reasons and current challenges…[of integrating] passive devices into board or IC…just the right dose of the math to explain the physics and theory behind the technology." (IEEE Circuits & Devices Magazine, Jan/Feb 2005) "...an interesting and useful book; I wholeheartedly recommend it."(Circuit World, Vol.30, No. 2003)Table of ContentsContributors. Preface. 1 Introduction (Richard K. Ulrich). 1.1 Status and Trends in Discrete Passive Components. 1.2 Definitions and Configurations of Integrated Passives. 1.3 Comparison to Integrated Active Devices. 1.4 Substrates and Interconnect Systems for Integrated Passives. 1.5 Fabrication of Integrated Passives. 1.6 Reasons for Integrating Passive Devices. 1.7 Problems with Integrating Passive Devices. 1.8 Applications for Integrated Passives. 1.9 The Past and Future of Integrated Passives. 1.10 Organization of this Book. References. 2 Characteristics and Performance of Planar Resistors (Richard K. Ulrich). 2.1 Performance Parameters. 2.2 Resistance in Electronic Materials. 2.3 Sizing Integrated Resistors. 2.4 Trimming. References. 3 Integrated Resistor Materials and Processes (Richard K. Ulrich). 3.1 Single-Component Metals. 3.2 Metal Alloys and Metal–Nonmetal Compounds. 3.3 Semiconductors. 3.4 Cermets. 3.5 Polymer Thick Film. 3.6 Ink Jet Deposition. 3.7 Commercialized Processes. 3.8 Summary. References. 4 Dielectric Materials for Integrated Capacitors (Richard K. Ulrich). 4.1 Polarizability and Capacitance. 4.2 Capacitance Density. 4.3 Temperature Effects. 4.4 Frequency and Voltage Effects. 4.5 Aging Effects. 4.6 Composition and Morphology Effects. 4.7 Leakage and Breakdown. 4.8 Dissipation Factor. 4.9 Comparison to EIA Dielectric Classifications. 4.10 Matching Dielectric Materials to Applications. References. 5 Size and Configuration of Integrated Capacitors (Richard K. Ulrich). 5.1 Comparison of Integrated and Discrete Areas. 5.2 Layout Options. 5.3 Tolerance. 5.4 Mixed Dielectric Strategies. 5.5 CV Product. 5.6 Maximum Capacitance Density and Breakdown Voltage. References. 6 Processing Integrated Capacitors (Richard K. Ulrich). 6.1 Sputtering. 6.2 CVD, PECVD and MOCVD. 6.3 Anodization. 6.4 Sol-Gel and Hydrothermal Ferroelectrics. 6.5 Thin- and Thick-Film Polymers. 6.6 Thick-Film Dielectrics. 6.7 Interlayer Insulation. 6.8 Interdigitated Capacitors. 6.9 Capacitor Plate Materials. 6.10 Trimming Integrated Capacitors. 6.11 Commercialized Integrated Capacitor Technologies. 6.12 Summary. References. 7 Defects and Yield Issues (Richard K. Ulrich). 7.1 Causes of Fatal Defects in Integrated Capacitors. 7.2 Measurement of Defect Density. 7.3 Defect Density and System Yield. 7.3.1 Predicting Yield from Defect Density. 7.4 Yield Enhancement Techniques for Capacitors. 7.5 Conclusions. References. 8 Electrical Performance of Integrated Capacitors (Richard K. Ulrich and Leonard W. Schaper). 8.1 Modeling Ideal Passives. 8.2 Modeling Real Capacitors. 8.3 Electrical Performance of Discrete and Integrated Capacitors. 8.4 Dissipation Factor of Real Capacitors. 8.5 Measurement of Capacitor Properties. 8.6 Summary. References. 9 Decoupling (Leonard W. Schaper). 9.1 Power Distribution. 9.2 Decoupling with Discrete Capacitors. 9.3 Decoupling with Integrated Capacitors. 9.4 Dielectrics and Configurations for Integrated Decoupling. 9.5 Integrated Decoupling as an Entry Application. References. 10 Integrated Inductors (Geert J. Carchon and Walter De Raedt). 10.1 Introduction. 10.2 Inductor Behavior and Performance Parameters. 10.3 Inductor Performance Prediction. 10.4 Integrated Inductor Examples. 10.5 Use of Inductors in Circuits: Examples. 10.6 Conclusions. Acknowledgments. References. 11 Modeling of Integrated Inductors and Resistors for Microwave Applications (Zhenwen Wang, M. Jamal Deen, and A. H. Rahal). 11.1 Introduction. 11.2 Modeling of Spiral Inductors. 11.3 Modeling of Thin-Film Resistors. 11.4 Conclusions. References. Appendix: Characteristics of Microscript Lines. 12 Other Applications and Integration Technologies (Elizabeth Logan, Geert J. Carchon, Walter De Raedt, Richard K. Ulrich, and Leonard W. Schaper). 12.1 Demonstration Devices Fabricated with Integrated Passives. 12.2 Commercialized Thin-Film Build-Up Integrated Passives. 12.3 Other Integrated Passive Technologies. 12.4 Summary. Acknowledgments. References. 13 The Economics of Embedded Passives (Peter A. Sandborn). 13.1 Introduction. 13.2 Modeling Embedded Passive Economics. 13.3 Key Aspects of Modeling Embedded Passive Costs. 13.4 Example Case Studies. 13.5 Summary. Acknowledgments. References. 14 The Future of Integrated Passives (Richard K. Ulrich). 14.1 Status of Passive Integration. 14.2 Issues for Implementation on Organic Substrates. 14.3 Progress on Board-Level Implementation. 14.4 Three Ways In for Organic Boards. 14.5 Conclusion. Index. About the Editors.
£128.66
John Wiley & Sons Inc Fundamentals of IIIV Devices
Book SynopsisA systematic, accessible introduction to III-V semiconductor devices With this handy book, readers seeking to understand semiconductor devices based on III-V materials no longer have to wade through difficult review chapters focusing on a single, novel aspect of the technology. Well-known industry expert William Liu presents here a systematic, comprehensive treatment at an introductory level. Without assuming even a basic course in device physics, he covers the dc and high-frequency operations of all major III-V devices-heterojunction bipolar transistors (HBTs), metal-semiconductor field-effect transistors (MESFETs), and the heterojunction field-effect transistors (HFETs), which include the high electron mobility transistors (HEMTs). An excellent introduction for researchers and circuit designers working on wireless communications equipment, Fundamentals of III-V Devices offers a variety of features, including: * An introductory chapter on the basic properties, growth process, and Table of ContentsBasic Properties and Device Physics of III-V Materials. Two-Terminal Heterojunction Devices. HBT D.C. Characteristics. HBT High-Frequency Properties. FET D.C. Characteristics. FET High-Frequency Properties. Transistor Fabrication and Device Comparison. Appendices. Index.
£169.16
John Wiley & Sons Inc Introduction to CMOS OpAmps and Comparators
Book SynopsisRoubik Gregorian, a well-known industry expert, provides circuit designers with the technical knowledge needed to design high-performance op-amps and comparators suitable for most analog circuit applications.Table of ContentsMOS Devices as Circuit Elements. Basic Analog CMOS Subcircuits. CMOS Operational Amplifier. Comparators. Digital-to-Analog Converters. Analog-to-Digital Converters. Practical Considerations and Design Examples. Index.
£130.45
John Wiley & Sons Inc Sensors and Signal Conditioning 1
Book SynopsisPraise for the First Edition . . . A unique piece of work, a book for electronics engineering, in general, but well suited and excellently applicable also to biomedical engineering . . . I recommend it with no reservation, congratulating the authors for the job performed. -IEEE Engineering in Medicine & Biology Describes a broad range of sensors in practical use and some circuit designs; copious information about electronic components is supplied, a matter of great value to electronic engineers. A large number of applications are supplied for each type of sensor described . . . This volume is of considerable importance.-Robotica In this new edition of their successful book, renowned authorities Ramon Pallàs-Areny and John Webster bring you up to speed on the latest advances in sensor technology, addressing both the explosive growth in the use of microsensors and improvements made in classical macrosensors. They continue to offer the only combined treatment foTrade Review"...It is sufficiently detailed to be useful to just about anyone involved with sensor development and implementation..." (n-lux.net, 4 February 2003)Table of ContentsIntroduction to Sensor-Based Measurement Systems. Resistive Sensors. Signal Conditioning for Resistive Sensors. Reactance Variation and Electromagnetic Sensors. Signal Conditioning for Reactance Variation Sensors. Self-Generating Sensors. Signal Conditioning for Self-Generating Sensors. Digital and Intelligent Sensors. Other Sensing Methods. Appendix. Index.
£164.66
John Wiley & Sons Inc HighSpeed Digital System Design
Book SynopsisA cutting-edge guide to the theory and practice of high-speed digital system design An understanding of high-speed interconnect phenomena is essential for digital designers who must deal with the challenges posed by the ever-increasing operating speeds of today''s microprocessors. This book provides a much-needed, practical guide to the state of the art of modern digital system design, combining easily accessible explanations with immensely useful problem-solving strategies. Written by three leading Intel engineers, High-Speed Digital System Design clarifies difficult and often neglected topics involving the effects of high frequencies on digital buses and presents a variety of proven techniques and application examples. Extensive appendices, formulas, modeling techniques as well as hundreds of figures are also provided. Coverage includes: * A thorough introduction to the digital aspects of basic transmission line theory * Crosstalk and nonideal transmissTrade Review"...an excellent guidebook for interconnect design...this very valuable work is highly recommended for design engineers and recent graduates struggling to transition from theory to real-world design." (Choice, Vol. 38, No. 8, April 2001) "This is an excellent book for anyone who has basic circuit theory knowledge.... It is a recommended book for all academic engineering libraries and would, also, be useful for the practicing engineer." (E-Streams, Vol. 4, No. 8, August 2001)Table of ContentsPreface. 1. The Importance of Interconnect Design. 1.1 The Basics. 1.2 The Past and the Future. 2. Ideal Transmission Line Fundamentals. 2.1 Transmission Line Structures on a PCB or MCM. 2.2 Wave Propagation. 2.3 Transmission Line Parameters. 2.3.1 Characteristic Impedance. 2.3.2 Propagation Velocity, Time, and Distance. 2.3.3 Equivalent Circuit Models for SPICE Simulation. 2.4 Launching Initial Wave and Transmission Line Reflections. 2.4.1 Initial Wave. 2.4.2 Multiple Reflections. 2.4.3 Effect of Rise Time on Reflections. 2.4.4 Reflections From Reactive Loads. 2.4.5 Termination Schemes to Eliminate Reflections. 2.5 Additional Examples. 2.5.1 Problem. 2.5.2 Goals. 2.5.3 Calculating the Cross-Sectional Geometry of the PCB. 2.5.4 Calculating the Propagation Delay. 2.5.5 Determining the Wave Shape Seen at the Receiver. 2.5.6 Creating an Equivalent Circuit. 3. Crosstalk. 3.1 Mutual Inductance and Mutual Capacitance. 3.2 Inductance and Capacitance Matrix. 3.3 Field Simulators. 3.4 Crosstalk-Induced Noise. 3.5 Simulating Crosstalk Using Equivalent Circuit Models. 3.6 Crosstalk-Induced Flight Time and Signal Integrity Variations. 3.6.1 Effect of Switching Patterns on Transmission Line Performance. 3.6.2 Simulating Traces in a Multiconductor System Using a Single-Line Equivalent Model. 3.7 Crosstalk Trends. 3.8 Termination of Odd- and Even-Mode Transmission Line Pairs. 3.8.1 Pi Termination Network. 3.8.2 T Termination Network. 3.9 Minimization of Crosstalk. 3.10 Additional Examples. 3.10.1 Problem. 3.10.2 Goals. 3.10.3 Determining the Maximum Crosstalk-Induced Impedance and Velocity Swing. 3.10.4 Determining if Crosstalk Will Induce False Triggers. 4. Nonideal Interconnect Issues. 4.1 Transmission Line Losses. 4.1.1 Conductor DC Losses. 4.1.2 Dielectric DC Losses. 4.1.3 Skin Effect. 4.1.4 Frequency-Dependent Dielectric Losses. 4.2 Variations in the Dielectric Constant. 4.3 Serpentine Traces. 4.4 Intersymbol Interference. 4.5 Effects of 90 Bends. 4.6 Effect of Topology. 5. Connectors, Packages, and Vias. 5.1 Vias. 5.2 Connectors. 5.2.1 Series Inductance. 5.2.2 Shunt Capacitance. 5.2.3 Connector Crosstalk. 5.2.4 Effects of Inductively Coupled Connector Pin Fields. 5.2.5 EMI. 5.2.6 Connector Design Guidelines. 5.3 Chip Packages. 5.3.1 Common Types of Packages. 5.3.2 Creating a Package Model. 5.3.3 Effects of a Package. 5.3.4 Optimal Pin-Outs. 6. Nonideal Return Paths, Simultaneous Switching Noise, and Power Delivery. 6.1 Nonideal Current Return Paths. 6.1.1 Path of Least Inductance. 6.1.2 Signals Traversing a Ground Gap. 6.1.3 Signals That Change Reference Planes. 6.1.4 Signals Referenced to a Power or a Ground Plane. 6.1.5 Other Nonideal Return Path Scenarios. 6.1.6 Differential Signals. 6.2 Local Power Delivery Networks. 6.2.1 Determining the Local Decoupling Requirements for High-Speed I/O. 6.2.2 System-Level Power Delivery. 6.2.3 Choosing a Decoupling Capacitor. 6.2.4 Frequency Response of a Power Delivery System. 6.3 SSO/SSN. 6.3.1 Minimizing SSN. 7. Buffer Modeling. 7.1 Types of Models. 7.2 Basic CMOS Output Buffer. 7.2.1 Basic Operation. 7.2.2 Linear Modeling of the CMOS Buffer. 7.2.3 Behavioral Modeling of the Basic CMOS Buffer. 7.3 Output Buffers That Operate in the Saturation Region. 7.4 Conclusions. 8. Digital Timing Analysis. 8.1 Common-Clock Timing. 8.1.1 Common-Clock Timing Equations. 8.2 Source Synchronous Timing. 8.2.1 Source Synchronous Timing Equations. 8.2.2 Deriving Source Synchronous Timing Equations from an Eye Diagram. 8.2.3 Alternative Source Synchronous Schemes. 8.3 Alternative Bus Signaling Techniques. 8.3.1 Incident Clocking. 8.3.2 Embedded Clock. 9. Design Methodologies. 9.1 Timings. 9.1.1 Worst-Case Timing Spreadsheet. 9.1.2 Statistical Spreadsheets. 9.2 Timing Metrics, Signal Quality Metrics, and Test Loads. 9.2.1 Voltage Reference Uncertainty. 9.2.2 Simulation Reference Loads. 9.2.3 Flight Time. 9.2.4 Flight-Time Skew. 9.2.5 Signal Integrity. 9.3 Design Optimization. 9.3.1 Paper Analysis. 9.3.2 Routing Study. 9.4 Sensitivity Analysis. 9.4.1 Initial Trend and Significance Analysis. 9.4.2 Ordered Parameter Sweeps. 9.4.3 Phase 1 Solution Space. 9.4.4 Phase 2 Solution Space. 9.4.5 Phase 3 Solution Space. 9.5 Design Guidelines. 9.6 Extraction. 9.7 General Rules of Thumb to Follow When Designing a System. 10. Radiated Emissions Compliance and System Noise Minimization. 10.1 FCC Radiated Emission Specifications. 10.2 Physical Mechanisms of Radiation. 10.2.1 Differential-Mode Radiation. 10.2.2 Common-Mode Radiation. 10.2.3 Wave Impedance. 10.3 Decoupling and Choking. 10.3.1 High-Frequency Decoupling at the System Level. 10.3.2 Choking Cables and Localized Power and Ground Planes. 10.3.3 Low-Frequency Decoupling and Ground Isolation. 10.4 Additional PCB Design Criteria, Package Considerations, and Pin-Outs. 10.4.1 Placement of High-Speed Components and Traces. 10.4.2 Crosstalk. 10.4.3 Pin Assignments and Package Choice. 10.5 Enclosure (Chassis) Considerations. 10.5.1 Shielding Basics. 10.5.2 Apertures. 10.5.3 Resonances. 10.6 Spread Spectrum Clocking. 11. High-Speed Measurement Techniques. 11.1 Digital Oscilloscopes. 11.1.1 Bandwidth. 11.1.2 Sampling. 11.1.3 Other Effects. 11.1.4 Statistics. 11.2 Time-Domain Reflectometry. 11.2.1 TDR Theory. 11.2.2 Measurement Factors. 11.3 TDR Accuracy. 11.3.1 Launch Parasitics. 11.3.2 Probe Types. 11.3.3 Reflections. 11.3.4 Interface Transmission Loss. 11.3.5 Cable Loss. 11.3.6 Amplitude Offset Error. 11.4 Impedance Measurement. 11.4.1 Accurate Characterization of Impedance. 11.4.2 Measurement Region in TDR Impedance Profile. 11.5 Odd- and Even-Mode Impedance. 11.6 Crosstalk Noise. 11.7 Propagation Velocity. 11.7.1 Length Difference Method. 11.7.2 Y-Intercept Method. 11.7.3 TDT Method. 11.8 Vector Network Analyzer. 11.8.1 Introduction to S Parameters. 11.8.2 Equipment. 11.8.3 One-Port Measurements (ZO,L,C). 11.8.4 Two-Port Measurements (Td, Attenuation, Crosstalk). 11.8.5 Calibration. 11.8.6 Calibration for One-Port Measurements. 11.8.7 Calibration for Two-Port Measurements. 11.8.8 Calibration Verification. Appendix A: Alternative Characteristic Impedance Formulas. A.1 Microstrip. A.2 Symmetric Stripline. A.3 Offset Stripline. Appendix B: GTL Current-Mode Analysis. B.1 Basic GTL Operation. B.2 GTL Transitions When a Middle Agent Is Driving. B.3 GTL Transitions When an End Agent With a Termination Is Driving. B.4 Transitions When There is a Pull-Up at the Middle Agent. Appendix C: Frequency-Domain Components in a Digital Signal. Appendix D: Useful S-Parameter Conversions. D.1 ABCD, Z, and Y Parameters. D.2 Normalizing the S Matrix to a Different Characteristic Impedance. D.3 Derivation of the Formulas Used to Extract the Mutual Inductance and Capacitance from a Short Structure Using S21 Measurements. D.4 Derivation of the Formula to Extract Skin Effect Resistance from a Transmission Line. Appendix E: Definition of the Decibel. Appendix F: FCC Emission Limits. Bibliography. Index.
£125.06
John Wiley & Sons Inc Electric Circuit Analysis 3e Student Problem Set
Book Synopsis* Introduces the operational amplifier early, and uses it as a basic element throughout the book. * Provides numerous exercises and examples throughout. * Written in a clear, precise style that has been highly praised throughout many editions. .
£67.92
