Electronics: circuits and components Books

Book SynopsisThis expanded third edition of the most popular book on electromagnetic compatibility reflects all of the latest advances and developments in the field. It demonstrates how and why noise in electronic digital systems can be avoided or minimized.Trade Review"This is an outstanding book. At 872 pages thick, it is a valuable follow-up to Ott's earlier books, Noise Reduction Techniques in Electronic Systems (first edition, 1975; second edition, 1987) . . . EMC will remain with us in the foreseeable future, and we need books like this one." (The Radio Science Bulletin, 1 June 2011) Table of ContentsPreface xxiii Part 1 EMC Theory 1 1 Electromagnetic Compatibility 3 1.1 Introduction 3 1.2 Noise and Interference 3 1.3 Designing for Electromagnetic Compatibility 4 1.4 Engineering Documentation and EMC 6 1.5 United States’ EMC Regulations 6 1.6 Canadian EMC Requirements 19 1.7 European Union’s EMC Requirements 20 1.8 International Harmonization 26 1.9 Military Standards 27 1.10 Avionics 28 1.11 The Regulatory Process 30 1.12 Typical Noise Path 30 1.14 Miscellaneous Noise Sources 33 1.15 Use of Network Theory 36 Summary 38 Problems 39 References 41 Further Reading 42 2 Cabling 44 2.1 Capacitive Coupling 45 2.2 Effect of Shield on Capacitive Coupling 48 2.3 Inductive Coupling 52 2.4 Mutual Inductance Calculations 54 2.5 Effect of Shield on Magnetic Coupling 56 2.6 Shielding to Prevent Magnetic Radiation 64 2.7 Shielding a Receptor Against Magnetic Fields 67 2.8 Common Impedance Shield Coupling 69 2.9 Experimental Data 70 2.10 Example of Selective Shielding 74 2.11 Shield Transfer Impedance 75 2.12 Coaxial Cable Versus Twisted Pair 75 2.13 Braided Shields 79 2.14 Spiral Shields 81 2.15 Shield Terminations 84 2.16 Ribbon Cables 94 2.17 Electrically Long Cables 96 Summary 96 Problems 98 References 103 Further Reading 104 3 Grounding 106 3.1 AC Power Distribution and Safety Grounds 107 3.2 Signal Grounds 120 3.3 Equipment/System Grounding 132 3.4 Ground Loops 142 3.5 Low-Frequency Analysis of Common-Mode Choke 147 3.6 High-Frequency Analysis of Common-Mode Choke 152 3.7 Single Ground Reference for a Circuit 154 Summary 155 Problems 156 References 157 Further Reading 157 4 Balancing and Filtering 158 4.1 Balancing 158 4.2 Filtering 174 4.3 Power Supply Decoupling 178 4.4 Driving Capacitive Loads 186 4.5 System Bandwidth 188 4.6 Modulation and Coding 190 Summary 190 Problems 191 References 192 Further Reading 193 5 Passive Components 194 5.1 Capacitors 194 5.2 Inductors 203 5.3 Transformers 204 5.4 Resistors 206 5.5 Conductors 208 5.6 Transmission Lines 215 5.7 Ferrites 225 Summary 233 Problems 234 References 237 Further Reading 237 6 Shielding 238 6.1 Near Fields and Far Fields 238 6.2 Characteristic and Wave Impedances 241 6.3 Shielding Effectiveness 243 6.4 Absorption Loss 245 6.5 Reflection Loss 249 6.6 Composite Absorption and Reflection Loss 257 6.7 Summary of Shielding Equations 260 6.8 Shielding with Magnetic Materials 260 6.9 Experimental Data 265 6.10 Apertures 267 6.11 Waveguide Below Cutoff 280 6.12 Conductive Gaskets 282 6.13 The ‘‘IDEAL’’ Shield 287 6.14 Conductive Windows 288 6.16 Internal Shields 293 6.17 Cavity Resonance 295 6.18 Grounding of Shields 296 Summary 296 Problems 297 References 299 Further Reading 300 7 Contact Protection 302 7.1 Glow Discharges 302 7.2 Metal-Vapor or Arc Discharges 303 7.3 AC Versus DC Circuits 305 7.4 Contact Material 306 7.5 Contact Rating 306 7.6 Loads with High Inrush Currents 307 7.7 Inductive Loads 308 7.8 Contact Protection Fundamentals 310 7.9 Transient Suppression for Inductive Loads 314 7.10 Contact Protection Networks for Inductive Loads 318 7.11 Inductive Loads Controlled by a Transistor Switch 322 7.12 Resistive Load Contact Protection 323 7.13 Contact Protection Selection Guide 323 7.14 Examples 324 Summary 325 Problems 326 References 327 Further Reading 327 8 Intrinsic Noise Sources 328 8.1 Thermal Noise 328 8.2 Characteristics of Thermal Noise 332 8.3 Equivalent Noise Bandwidth 334 8.4 Shot Noise 337 8.5 Contact Noise 338 8.6 Popcorn Noise 339 8.7 Addition of Noise Voltages 340 8.8 Measuring Random Noise 341 Summary 342 Problems 343 References 345 Further Reading 345 9 Active Device Noise 346 9.1 Noise Factor 346 9.2 Measurement of Noise Factor 349 9.3 Calculating S/N Ratio and Input Noise Voltage from Noise Factor 351 9.4 Noise Voltage and Current Model 353 9.5 Measurment of Vn and In 355 9.6 Calculating Noise Factor and S/N Ratio from Vn–In 356 9.7 Optimum Source Resistance 357 9.8 Noise Factor of Cascaded Stages 360 9.9 Noise Temperature 362 9.10 Bipolar Transistor Noise 364 9.11 Field-Effect Transistor Noise 368 9.12 Noise in Operational Amplifiers 370 Summary 375 Problems 376 References 377 Further Reading 378 10 Digital Circuit Grounding 379 10.1 Frequency Versus Time Domain 380 10.2 Analog Versus Digital Circuits 380 10.3 Digital Logic Noise 380 10.4 Internal Noise Sources 381 10.5 Digital Circuit Ground Noise 384 10.6 Ground Plane Current Distribution and Impedance 391 10.7 Digital Logic Current Flow 412 Summary 419 Problems 420 References 421 Further Reading 422 Part 2 EMC Applications 423 11 Digital Circuit Power Distribution 425 11.1 Power Supply Decoupling 425 11.2 Transient Power Supply Currents 426 11.3 Decoupling Capacitors 431 11.4 Effective Decoupling Strategies 436 11.5 The Effect of Decoupling on Radiated Emissions 454 11.6 Decoupling Capacitor Type and Value 456 11.7 Decoupling Capacitor Placement and Mounting 457 11.8 Bulk Decoupling Capacitors 459 11.9 Power Entry Filters 460 Summary 461 Problems 461 References 463 Further Reading 463 12 Digital Circuit Radiation 464 12.1 Differential-Mode Radiation 465 12.2 Controlling Differential-Mode Radiation 471 12.3 Common-Mode Radiation 477 12.4 Controlling Common-Mode Radiation 480 Summary 488 Problems 489 References 490 Further Reading 491 13 Conducted Emissions 492 13.1 Power Line Impedance 492 13.2 Switched-Mode Power Supplies 495 13.3 Power-Line Filters 511 13.4 Primary-to-Secondary Common-Mode Coupling 523 13.5 Frequency Dithering 524 13.6 Power Supply Instability 524 13.7 Magnetic Field Emissions 525 13.8 Variable Speed Motor Drives 528 13.9 Harmonic Suppression 536 Summary 541 Problems 542 References 544 Further Reading 544 14 RF and Transient Immunity 545 14.1 Performance Criteria 545 14.2 RF Immunity 546 14.3 Transient Immunity 557 14.4 Power Line Disturbances 572 Summary 575 Problems 576 References 578 Further Reading 579 15 Electrostatic Discharge 580 15.1 Static Generation 580 15.2 Human Body Model 587 15.3 Static Discharge 589 15.4 ESD Protection in Equipment Design 592 15.5 Preventing ESD Entry 594 15.6 Hardening Sensitive Circuits 608 15.7 ESD Grounding 608 15.8 Nongrounded Products 609 15.9 Field-Induced Upset 610 15.10 Transient Hardened Software Design 612 15.11 Time Windows 617 Summary 617 Problems 619 References 620 Further Reading 621 16 PCB Layout and Stackup 622 16.1 General PCB Layout Considerations 622 16.2 PCB-to-Chassis Ground Connection 625 16.3 Return Path Discontinuities 626 16.4 PCB Layer Stackup 635 Summary 655 Problems 657 References 658 Further Reading 658 17 Mixed-Signal PCB Layout 660 17.1 Split Ground Planes 660 17.2 Microstrip Ground Plane Current Distribution 662 17.3 Analog and Digital Ground Pins 665 17.4 When Should Split Ground Planes Be Used? 668 17.5 Mixed Signal ICs 669 17.6 High-Resolution A/D and D/A Converters 671 17.7 A/D and D/A Converter Support Circuitry 676 17.8 Vertical Isolation 679 17.9 Mixed-Signal Power Distribution 681 17.10 The IPC Problem 684 Summary 685 Problems 686 References 687 Further Reading 687 18 Precompliance EMC Measurements 688 18.1 Test Environment 689 18.2 Antennas Versus Probes 689 18.3 Common-Mode Currents on Cables 690 18.4 Near Field Measurements 694 18.5 Noise Voltage Measurements 697 18.6 Conducted Emission Testing 700 18.7 Spectrum Analyzers 707 18.8 EMC Crash Cart 711 18.9 One-Meter Radiated Emission Measurements 713 18.10 Precompliance Immunity Testing 717 18.11 Precompliance Power Quality Tests 723 18.12 Margin 726 Summary 728 Problems 729 References 730 Further Reading 731 Appendix 733 A. The Decibel 733 B. The Ten Best Ways to Maximize the Emission from Your Product 740 C. Multiple Reflections of Magnetic Fields in Thin Shields 743 D. Dipoles for Dummies 746 E. Partial Inductance 765 F. Answers to Problems 790 Index 825

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Book SynopsisIncludes extensive design information in the form of equations, tables, graphs and examples. Offers an in-depth study of amplifiers. Simple design equations are included to help understand design concepts. Practical and simple to understand examples with over 70 fully solved.Table of ContentsForeword. Preface. Chapter 1: Introduction. 1.1 Transistor Amplifier. 1.2 Early History of Transistor Amplifiers. 1.3 Benefits of Transistor Amplifiers. 1.4 Transistors. 1.5 Design of Amplifiers. 1.6 Amplifier Manufacturing Technologies. 1.7 Applications of Amplifiers. 1.8 Amplifier Cost. 1.9 Current Trends. 1.10 Book Organization. References. Chapter 2: Linear Network Analysis. 2.1 Impedance Matrix. 2.2 Admittance Matrix. 2.3 ABCD Parameters. 2.4 S-Parameters. 2.5 Relationships Between Various 2-Port Parameters. References. Problems. Chapter 3: Amplifier Characteristics and Definitions. 3.1 Bandwidth. 3.2 Power Gain. 3.3 Input and Output VSWR. 3.4 Output Power. 3.5 Power Added Efficiency. 3.6 Intermodulation Distortion. 3.7 Harmonic Power. 3.8 Peak-to-Average Ratio. 3.9 Combiner Efficiency. 3.10 Noise Characterization. 3.11 Dynamic Range. 3.12 Multi-Stage Amplifier Characteristics. 3.13 Gate and Drain Pushing Factors. 3.14 Amplifier Temperature Coefficient. 3.15 Mean Time To Failure. References. Problems. Chapter 4: Transistors. 4.1 Transistor Types. 4.2 Si Bipolar Transistor. 4.3 GaAs MESFET. 4.4 Hetrojunction Field Effect Transistor. 4.5 Hetrojunction BipolarTransistors. 4.6 MOSFET. References. Problems. Chapter 5: Transistor Models. 5.1 Transistor Model Types. 5.2 MESFET Models. 5.3 pHEMT Models. 5.4 HBT Model. 5.5 MOSFET Models. 5.6 BJT Models. 5.7 Transistor Model Scaling. 5.8 Source- and Load-Pull Data. 5.9 Temperature Dependent Models. References. Problems. Chapter 6: Matching Network Components. 6.1 Impedance Matching Elements. 6.2 Transmission Lines Matching Elements. 6.3 Lumped Elements. 6.4 Bond Wire Inductors. 6.5 Broadband Inductors. References. Problems. Chapter 7: Impedance Matching Techniques. 7.1 One-Port and Two-Port Networks. 7.2 Narrowband Matching Techniques. 7.3 Wideband Matching Techniques. References. Problems. Chapter 8: Amplifier Classes and Analyses. 8.1 Classes of Amplifiers. 8.2 Analysis of Class-A Amplifiers. 8.3 Analysis of Class-B Amplifiers. 8.4 Analysis of Class-C Amplifiers. 8.5 Analysis of Class-E Amplifiers. 8.6 Analysis of Class-F Amplifiers. 8.7 Comparison Between Various Amplifier Classes. References. Problems. Chapter 9: Amplifier Design Methods. 9.1 Amplifier Design. 9.2 Amplifier Design techniques. 9.3 Matching Networks. 9.4 Amplifier Design Examples. 9.5 Silicon Based Handset Amplifier Design. References. Problems. Chapter 10: High-Efficiency Amplifier Techniques. 10.1 High-Efficiency Design. 10.2 Harmonic Reaction Amplifier. 10.3 Harmonic Injection Technique. 10.4 Harmonic Control Amplifier. 10.5 High-PAE Design Considerations. References. Problems. Chapter 11: Broadband Amplifier Techniques. 11.1 Transistor Bandwidth Limitations. 11.2 Broadband Amplifier Techniques. 11.3 Broadband Power Amplifier Design Considerations. References. Problems. Chapter 12: Linearization Techniques. 12.1 Nonlinear Analysis. 12.2 Phase Distortion. 12.3 Linearization of Power Amplifiers. 12.4 Efficiency Enhancement Techniques for Linear Amplifiers. 12.5 Linear Amplifier Design Considerations. 12.6 Linear Amplifier Design Examples. References. Problems. Chapter 13: High-Voltage Power Amplifier Design. 13.1 Performance Overview of High-Voltage Transistors. 13.2 High-Voltage Transistors. 13.3 High-Power Amplifier Design Considerations. 13.4 Power Amplifier Design Examples. 13.5 Broadband HV Amplifiers. 13.6 Series FET Amplifiers. References. Problems. Chapter 14: Hybrid Amplifiers. 14.1 Hybrid Amplifier Technologies. 14.2 Printed Circuit Boards. 14.3 Hybrid Integrated Circuits. 14.4 Design of Internally Matched Power Amplifiers. 14.5 Low-Noise Amplifiers. 14.6 Power Amplifiers. References. Problems. Chapter 15: Monolithic Amplifiers. 15.1 Advantages of Monolithic Amplifiers. 15.2 Monolithic IC Technology. 15.3 MMIC Design. 15.4 Design Examples. 15.5 CMOS Fabrication. References. Problems. Chapter 16: Thermal Design. 16.1 Thermal Basics. 16.2 Transistor Thermal Design. 16.3 Amplifier Thermal Design. 16.4 Pulsed Operation. 16.5 Heat Sink Design. 16.6 Thermal Resistance Measurement. References. Problems. Chapter 17: Stability Analyses. 17.1 Even-Mode Oscillations. 17.2 Odd-Mode Oscillations. 17.3 Parametric Oscillations. 17.4 Spurous Parametric Oscillations. 17.5 Low-Frequency Oscillations. References. Problems. Chapter 18: Biasing Networks. 18.1 Biasing of Transistors. 18.2 Biasing Network Design Considerations. 18.3 Self-Bias Technique. 18.4 Biasing Multi-Stage Amplifiers. 18.5 Biasing Circuitry for Low-Frequency Stabilization. 18.6 Biasing Sequence. References. Problems. Chapter 19: Power Combining. 19.1 Device-Level Power Combining. 19.2 Circuit-Level Power Combining. 19.3 Power Dividers, Hybrids and Couplers. 19.4 N-Way Combiners. 19.5 Corporate Structures. 19.6 Power Handling of Isolation Resistors. 19.7 Spatial Power Combiners. 19.8 Comparison of Power Combining Schemes. References. Problems. Chapter 20: Integrated Function Amplifiers. 20.1 Integrated limiter/LNA. 20.2 Transmitter Chain. 20.3 Cascading of Amplifiers. References. Problems. Chapter 21: Amplifier Packages. 21.1 Amplifier Packaging Overview. 21.2 Materials for Packages. 21.3 Ceramic Package Design. 21.4 Plastic Package Design. 21.5 Package Assembly. 21.6 Thermal Considerations. 21.7 CAD Tools For Packages. 21.8 Power Amplifier Modules. References. Problems. Chapter 22: Transistor and Amplifier Measurements. 22.1 Transistor Measurements. 22.2 Amplifier Measurements. 22.3 Distortion Measurements. 22.4 Phase Noise Measurement. 22.5 Recovery Time Measurement. References. Problems. Appendix A: Physical Constants and Other Data. Appendix B: Units and Symbols. Appendix C: Frequency Band Designation. Appendix D: Decibel Units - (dB). Appendix E: Mathematical Relations. Appendix F: Smith Chart. Appendix G: Graphical Symbols. Appendix H: Acronyms and Abbreviations. Appendix I: List Of Symbols. Appendix J: Multiple Access and Modulation Techniques. Index.

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Book SynopsisAn in-depth survey of the design and REALIZATIONS of miniaturized fractal microwave and RF filters Engineers are continually searching for design methods that can satisfy the ever-increasing demand for miniaturization, accuracy, reliability, and fast development time. Design and Realizations of Miniaturized Fractal RF and Microwave Filters provides RF and microwave engineers and researchers, advanced graduate students, and wireless and telecommunication engineers with the knowledge and skills to design and realize miniaturized fractal microwave and RF filters. This book is an essential resource for the realization of portable and cellular phones, WiFi, 3G and 4G, and satellite networks. The text focuses on the synthesis and fabrication of miniaturized fractal filters with symmetrical and asymmetrical frequency characteristics in the C, X and Ku bands, though applications to other frequency bands are considered. Readers will find helpful guidance on: MTable of ContentsFOREWORD. PREFACE. 1 MICROWAVE FILTER STRUCTURES. 1.1 Background. 1.2 Cavity Filters. 1.3 Planar Filters. 1.4 Planar Filter Technology. 1.5 Active Filters. 1.6 Superconductivity or HTS Filters. 1.7 Periodic Structure Filters. 1.8 SAW Filters. 1.9 Micromachined Filters. 1.10 Summary. References. 2 IN-LINE SYNTHESIS OF PSEUDO-ELLIPTIC FILTERS. 2.1 Introduction. 2.2 Approximation and Synthesis. 2.3 Chebyshev Filters. 2.4 Pseudo-elliptic Filters. 2.5 Prototype Synthesis Examples. 2.6 Theoretical Coupling Coefficients and External Quality Factors. References. 3 SUSPENDED SUBSTRATE STRUCTURE. 3.1 Introduction. 3.2 Suspended Substrate Technology. 3.3 Unloaded Quality Factor of a Suspended Substrate Resonator. 3.4 Coupling Coefficients of Suspended Substrate Resonators. 3.5 Enclosure Design Considerations. References. 4 MINIATURIZATION OF PLANAR RESONATORS USING FRACTAL ITERATIONS. 4.1 Introduction. 4.2 Miniaturization of Planar Resonators. 4.3 Fractal Iteration Applied to Planar Resonators. 4.4 Minkowski Resonators. 4.5 Hibert Resonators. References. 5 DESIGN AND REALIZATIONS OF MEANDERED LINE FILTERS. 5.1 Introduction. 5.2 Third-order Pseudo-elliptic Filters with Transmission Zero on the Right. 5.3 Third-order Pseudo-elliptic Filters with Transmission Zero on the Left. References. 6 DESIGN AND REALIZATIONS OF HILBERT FILTERS. 6.1 Introduction. 6.2 Design of Hilbert Filters. 6.3 Realizations and Measured Performance. References. 7 DESIGN AND REALIZATION OF DUAL-MODE MINKOWSKI FILTERS. 7.1 Introduction. 7.2 Study of Minkowski Dual-Mode Resonators. 7.3 Design of Fourth-Order Pseudo-elliptic Filters with Two Transmission Zeros. 7.4 Realization and Measured Performance. References. APPENDIX 1: Equivalence Between J and K Lowpass Prototypes. APPENDIX 2: Extraction of the Unloaded Quality Factor of Suspended Substrate Resonators. INDEX.

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Book SynopsisToday's networks of processors on and off chip, operating with independent clocks, need effective synchronization of the data passing between them for reliability. When two or more processors request access to a common resource, such as a memory, an arbiter has to decide which request to deal with first.Table of ContentsPreface. List of Contributors. Acknowledgements. 1. Synchronization, Arbitration and Choice. 1.1 Introduction. 1.2 The Problem of Choice. 1.3 Choice in Electronics. 1.4 Arbitration. 1.5 Continuous and Discrete Quantities. 1.6 Timing. 1.7 Book Structure. PART I. 2. Modelling Metastability. 2.1 The Synchronizer. 2.2 Latch Model. 2.3 Failure Rates. 2.3.1 Event Histograms and MTBF. 2.4 Latches and Flip-flops. 2.5 Clock Back Edge. 3. Circuits. 3.1 Latches and Metastability Filters. 3.2 Effects of Filtering. 3.3 The Jamb Latch. 3.3.1 Jamb Latch Flip-flop. 3.4 Low Coupling Latch. 3.5 The Q-flop. 3.6 The MUTEX. 3.7 Robust Synchronizer. 3.8 The Tri-flop. 4. Noise and its Effects. 4.1 Noise. 4.2 Effect of Noise on a Synchronizer. 4.3 Malicious Inputs. 4.3.1 Synchronous Systems. 4.3.2 Asynchronous Systems. 5. Metastability Measurements. 5.1 Circuit Simulation. 5.1.1 Time Step Control. 5.1.2 Long-term τ. 5.1.3 Using Bisection. 5.2 Synchronizer Flip-flop Testing. 5.3 Rising and Falling Edges. 5.4 Delay-based Measurement. 5.5 Deep Metastability. 5.6 Back Edge Measurement. 5.7 Measure and Select. 5.7.1 Failure Measurement. 5.7.2 Synchronizer Selection. 6. Conclusions Part I. PART II. 7. Synchronizers in Systems. 7.1 Latency and Throughput. 7.2 FIFO Synchronizer. 7.3 Avoiding Synchronization. 7.4 Predictive Synchronizers. 7.5 Other Low-latency Synchronizers. 7.5.1 Locally Delayed Latching (LDL). 7.5.2 Speculative Synchronization. 7.6 Asynchronous Communication Mechanisms (ACM). 7.6.1 Slot Mechanisms. 7.6.2 Three-slot Mechanism. 7.6.3 Four-slot Mechanism. 7.6.4 Hardware Design and Metastability. 7.7 Some Common Synchronizer Design Issues. 7.7.1 Unsynchronized Paths. 7.7.2 Moving Metastability Out of Sight. 7.7.3 Multiple Synchronizer Flops. 8. Networks and Interconnects. 8.1 Communication on Chip. 8.1.1 Comparison of Network Architectures. 8.2 Interconnect Links. 8.3 Serial Links. 8.3.1 Using One Line. 8.3.2 Using Two Lines. 8.4 Differential Signalling. 8.5 Parallel Links. 8.5.1 One Hot Codes. 8.5.2 Transition Signaling. 8.5.3 n of m Codes. 8.5.4 Phase Encoding. 8.5.5 Time Encoding. 8.6 Parallel Serial Links. 9. Pausible and Stoppable Clocks in GALS. 9.1 GALS Clock Generators. 9.2 Clock Tree Delays. 9.3 A GALS Wrapper. 10. Conclusions Part II. PART III. 11. Arbitration. 11.1 Introduction. 11.2 Arbiter Definition. 11.3 Arbiter Applications, Resource Allocation Policies and Common Architectures. 11.4 Signal Transition Graphs, Our Main Modelling Language. 12. Simple Two-way Arbiters. 12.1 Basic Concepts and Conventions. 12.1.1 Two-phase or Non-return-to-zero (NRZ) Protocols. 12.1.2 Four-phase or Return-to-zero (RTZ) Protocols. 12.2 Simple Arbitration Between Two Asynchronous Requests. 12.3 Sampling the Logic Level of an Asynchronous Request. 12.4 Summary of Two-way Arbiters. 13. Multi-way Arbiters. 13.1 Multi-way MUTEX Using a Mesh. 13.2 Cascaded Tree Arbiters. 13.3 Ring-based Arbiters. 14. Priority Arbiters. 14.1 Introduction. 14.2 Priority Discipline. 14.3 Daisy-chain Arbiter. 14.4 Ordered Arbiter. 14.5 Canonical Structure of Priority Arbiters. 14.6 Static Priority Arbiter. 14.7 Dynamic Priority Arbiter. 15. Conclusions Part III. References. Index.

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Book SynopsisElectrostatic discharge (ESD) failure mechanisms continue to impact semiconductor components and systems as technologies scale from micro- to nano-electronics. This book studies electrical overstress, ESD, and latchup from a failure analysis and case-study approach. It provides a clear insight into the physics of failure from a generalist perspective, followed by investigation of failure mechanisms in specific technologies, circuits, and systems. The book is unique in covering both the failure mechanism and the practical solutions to fix the problem from either a technology or circuit methodology. Look inside for extensive coverage on: failure analysis tools, EOS and ESD failure sources and failure models of semiconductor technology, and how to use failure analysis to design more robust semiconductor components and systems; electro-thermal models and technologies; the state-of-the-art technologies discussed include CMOS, BiCMOS, silicon on insulator (SOTable of ContentsAbout the Author. Preface. Acknowledgments. 1 Failure Analysis and ESD. 1.1 Introduction. 1.2 ESD Failure: How Do Micro-electronic Devices Fail?. 1.3 Sensitivity of Semiconductor Components. 1.4 How Do Semiconductor Chips Fail––Are the Failures Random or Systematic?. 1.5 Closing Comments and Summary. Problems. References. 2 Failure Analysis Tools, Models, and Physics of Failure. 2.1 FA Techniques for Evaluation of ESD Events. 2.2 FA Tools. 2.3 ESD Simulation: ESD Pulse Models. 2.4 Electro-Thermal Physical Models. 2.5 Statistical Models for ESD Prediction. 2.6 Closing Comments and Summary. Problems. References. 3 CMOS Failure Mechanisms. 3.1 Tables of CMOS ESD Failure Mechanisms. 3.2 LOCOS Isolation-Defined CMOS. 3.3 Shallow Trench Isolation (STI). 3.4 Polysilicon-Defined Devices. 3.5 Lateral Diode with Block Mask. 3.6 MOSFETs. 3.7 Resistors. 3.8 Interconnects: Wires, Vias, and Contacts. 3.9 ESD Failure in CMOS Nanostructures. 3.10 Closing Comments and Summary. Problems. References. 4 CMOS Circuits: Receivers and Off-Chip Drivers. 4.1 Tables of CMOS Receiver and OCD ESD Failure Mechanisms. 4.2 Receiver Circuits. 4.3 Receivers Circuits with ESD Networks. 4.4 Receiver Circuits with Half-Pass Transmission Gate. 4.5 Receiver with Full-Pass Transmission Gate. 4.6 Receiver, Half-Pass Transmission Gate, and Keeper Network. 4.7 Receiver Circuit with Pseudo-zero VT Half-Pass Transmission Gate. 4.8 Receiver with Zero VT Transmission Gate. 4.9 Receiver Circuits with Bleed Transistors. 4.10 Receiver Circuits with Test Functions. 4.11 Receiver with Schmitt Trigger Feedback Networks. 4.12 Off-Chip Drivers. 4.13 Single NFET Pull-down OCD. 4.14 Series Cascode MOSFETs. 4.15 I/O Design Considerations and ESD Parasitic Failure Mechanisms. 4.16 Closing Comments and Summary. Problems. References. 5 CMOS Integration. 5.1 Table of CMOS Integration ESD Failure Mechanisms. 5.2 Architecture and Design Synthesis-Related Failures. 5.3 Alternate Current Loop. 5.4 Chip Capacitance. 5.5 ESD Power Clamps. 5.6 Intra- and Inter-domain ESD Protection. 5.7 Split Ground Configurations. 5.8 Mixed Voltage Interface. 5.9 Mixed Signal Interface. 5.10 Inter-domain Signal Line ESD Failures. 5.11 Decoupling Capacitors. 5.12 System Clock and Phase-Locked Loop. 5.13 Fuse Networks. 5.14 Bond Pads. 5.15 MOSFET Gate Structure. 5.16 Fill Shapes. 5.17 No Connects. 5.18 Test Circuitry. 5.19 Multi-chip Systems. 5.20 CMOS Latchup Failures. 5.21 Closing Comments and Summary. Problems. References. 6 SOI ESD Failure Mechanisms. 6.1 Tables of SOI Device and Integration ESD Failure Mechanisms. 6.2 SOI N-channel MOSFETs. 6.3 SOI Diodes. 6.4 SOI Buried Resistors. 6.5 SOI Failure Mechanisms in 150 nm Technology. 6.6 SOI ESD Failure Mechanisms in 45 nm Technology. 6.7 SOI ESD Failure Mechanisms in 32 nm Technology. 6.8 SOI ESD Failure Mechanisms in 22 nm Technology and the Future. 6.9 SOI Design Synthesis and ESD Failure Mechanisms. 6.10 SOI Integration: ESD Failure Mechanisms. 6.11 Closing Comments and Summary. Problems. References. 7 RF CMOS and ESD. 7.1 Tables of RF CMOS ESD Failure Mechanisms. 7.2 RF MOSFET. 7.3 RF Shallow Trench Isolation Diode. 7.4 RF Polysilicon Gated Diode. 7.5 Silicon-Controlled Rectifier. 7.6 Schottky Barrier Diodes. 7.7 Capacitors. 7.8 Resistors. 7.9 Inductors. 7.10 Examples of RF ESD Circuit Failure Mechanisms. 7.11 Closing Comments and Summary. Problems. Reference. 8 Micro-electromechanical Systems. 8.1 Table of MEM Failure Mechanisms. 8.2 Electrostatically Actuated Devices. 8.3 Micro-mechanical Engines. 8.4 Torsional Ratcheting Actuator. 8.5 Electromagnetic Micro-power Generators. 8.6 MEM Inductors. 8.7 Electrostatically Actuated Variable Capacitor. 8.8 Micro-mechanical Switches. 8.9 RF MEM Switch. 8.10 Micro-mechanical Mirrors. 8.11 Electrostatically Actuated Torsional Micro-mirrors. 8.12 Closing Comments and Summary. Problems. References. 9 Gallium Arsenide. 9.1 Tables of GaAs-Based ESD Failure Mechanisms. 9.2 GaAs Technology. 9.3 GaAs Energy-to-failure and Power-to-failure. 9.4 GaAs ESD Failures in Active and Passive Elements. 9.5 GaAs HBT Devices. 9.6 GaAs HBT-Based Passive Elements. 9.7 GaAs PHEMT Devices. 9.8 GaAs Power Amplifiers. 9.9 InGaAs. 9.10 Gallium Nitride. 9.11 InP and ESD. 9.12 Closing Comments and Summary. Problems. References. 10 Smart Power, LDMOS, and BCD Technology. 10.1 Tables of LDMOS ESD Failure Mechanisms. 10.2 LOCOS-Defined LDMOS Devices. 10.3 STI-Defined LDMOS Devices. 10.4 STI-Defined Isolated LDMOS Transistors. 10.5 LDMOS Transistors: ESD Electrical Measurements. 10.6 LDMOS-Based ESD Networks. 10.7 LDMOS ESD Failure Mechanisms. 10.8 LDMOS Transistor Design Enhancement. 10.9 Latchup Events in LDMOS and BCD Technology. 10.10 Closing Comments and Summary. Problems. References. 11 Magnetic Recording. 11.1 Tables of Magnetic Recording Failure Mechanisms. 11.2 MR Heads. 11.3 Inductive Heads. 11.4 GMR Heads. 11.5 TMR Heads. 11.6 ESD Solutions. 11.7 Closing Comments and Summary. Problems. References. 12 Photo-masks and Reticles: Failure Mechanisms. 12.1 Table of Photo-masks ESD Failure Mechanisms. 12.2 Photo-mask Failure Mechanisms. 12.3 Photo-mask Inspection Tools. 12.4 Photo-mask ESD Characterization. 12.5 Electrical Breakdown Versus Gap Spacing. 12.6 Electrical Breakdown in Air: The Townsend Model. 12.7 Electric Breakdown in Air: Toepler’s Spark Law. 12.8 Air Breakdown: The Paschen Breakdown Model. 12.9 Paschen Curve Versus Reticle Breakdown Plot. 12.10 Electrical Model of Photo-mask Breakdown. 12.11 ESD Latent Damage. 12.12 ESD Damage for Single Versus Multiple Events. 12.13 ESD Damage to Anti-reflective Coating. 12.14 ESD Solutions in Photo-masks. 12.15 Closing Comments and Summary. Problems. References. Index.

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Book SynopsisPhotovoltaics (PV), the direct conversion of light from the sun into electricity, is an increasingly important means of distributed power generation. Using SPICE, the tool of choice for circuits and electronics designers, this book highlights the increasing importance of modelling techniques in the quantitative analysis of PV systems.Table of ContentsForeword. Preface. Acknowledgements. Introduction to Photovoltaic Systems and PSpice. Spectral Response and Short-Circuit Current. Electrical Characteristics of the Solar Cell. Solar Cell Arrays, PV Modules and PV Generators. Interfacing PV Modules to Loads and Battery Modelling. Power Conditioning and Inverter Modelling. Standalone PV Systems. Grid-connected PV Systems. Small Photovoltaics. Annex 1 PSpice Files Used in Chapter 1. Annex 2 PSpice Files Used in Chapter 2. Annex 3 PSpice Files Used in Chapter 3. Annex 4 PSpice Files Used in Chapter 4. Annex 5 PSpice Files Used in Chapter 5. Annex 6 PSpice Files Used in Chapter 6. Annex 7 PSpice Files Used in Chapter 7. Annex 8 PSpice Files Used in Chapter 8. Annex 9 PSpice Files Used in Chapter 9. Annex 10 Summary of Solar Cell Basic Theory. Annex 11 Estimation of the Radiation in an Arbitrarily Oriented Surface. Index.

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Book SynopsisPhotovoltaics (PV), the direct conversion of light from the sun into electricity, is an increasingly important means of distributed power generation. Using SPICE, the tool of choice for circuits and electronics designers, this book highlights the increasing importance of modelling techniques in the quantitative analysis of PV systems.Table of ContentsIntroduction to Photovoltaic Systems and Pspice Spectral Response and Short Circuit Current Electrical Characteristics of the Solar Cell Solar Cell Arrays PV Modules and PV Generators Interfacing PV Modules to Loads and Battery Modelling Power Conditioning and Inverter Modelling Stand - Alone PV Systems Grid Connected PV Systems Small Photovoltaics

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Book SynopsisDesign techniques for nonlinear microwave circuits are much less developed than for linear microwave circuits. This work addresses the design and measurement aspects.Trade Review"…any reader of 'Nonlinear Microwave Circuit Design' will gain insight into the many issues that are blissfully disregarded when using only linear techniques." (IEEE Microwave Magazine, December 2004)Table of ContentsPreface. Chapter 1. Nonlinear Analysis Methods. 1.1 Introduction. 1.2 Time-Domain Solution. 1.3 Solution Through Series Expansion 1.4 The Conversion Matrix. 1.5 Bibliography. Chapter 2. Nonlinear Measurements. 2.1 Introduction. 2.2 Load/Source-Pull. 2.3 The Vector Nonlinear Network Analyser. 2.4 Pulsed Measurements. 2.5 Bibliography. Chapter 3. Nonlinear Models. 3.1 Introduction. 3.2 Physical Models. 3.3 Equivalent-Circuit Models. 3.4 Black-Box Models. 3.5 Simplified Models. 3.6 Bibliography. Chapter 4. Power Amplifiers. 4.1 Introduction. 4.2 Classes of Operation. 4.3 Simplified Class-A Fundamental-Frequency Design For High Efficiency. 4.4 Multi-Harmonic Design For High Power And Efficiency. 4.5 Bibliography. Chapter 5. Oscillators. 5.1 Introduction. 5.2 Linear Stability and Oscillation Conditions. 5.3 From Linear To Nonlinear: Quasi-Large-Signal Oscillation And Stability Conditions. 5.4 Design Methods. 5.5 Nonlinear Analysis Methods For Oscillators. 5.6 Noise. 5.7 Bibliography. Chapter 6. Frequency Multipliers and Dividers. 6.1 Introduction. 6.2 Passive Multipliers. 6.3 Active Multipliers. 6.4 Frequency Dividers-The Rigenerative (Passive) Approach. 6.5 Bibliography. Chapter 7. Mixers. 7.1 Introduction. 7.2 Mixer Configurations. 7.3 Mixer Design. 7.4 Nonlinear Analysis. 7.5 Noise. 7.6 Bibliography. Chapter 8. Stability and Injection-locked Circuits. 8.1 Introduction. 8.2 Local Stability Of Nonlinear Circuits In Large-Signal Regime. 8.3 Nonlinear Analysis, Stability And Bifurcations. 8.4 Injection Locking. 8.5 Bibliography. Appendix. A.1. Transformation in the Fourier Domain of the Linear Differential Equation. A.2. Time-Frequency Transformations. A.3 Generalized Fourier Transformation for the Volterra Series Expansion. A.4 Discrete Fourier Transform and Inverse Discrete Fourier Transform for Periodic Signals. A.5 The Harmonic Balance System of Equations for the Example Circuit with N=3. A.6 The Jacobian Matrix A.7 Multi-dimensional Discrete Fourier Transform and Inverse Discrete Fourier Transform for quasi-periodic signals. A.8 Oversampled Discrete Fourier Transform and Inverse Discrete Fourier Transform for Quasi-Periodic Signals. A.9 Derivation of Simplified Transport Equations. A.10 Determination of the Stability of a Linear Network. A.11 Determination of the Locking Range of an Injection-Locked Oscillator. Index.

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Book SynopsisThis text examines the theory and application of infrared detectors. It describes the optical detection process and the electronics involved in mimicking the eye. It further describes how well optical systems detect radiation.Table of ContentsPartial table of contents: Geometrical Optics. Radiometry. Optical-Detection Processes. Probability and Statistics for Optical Detection. Figures of Merit for Optical Detectors. Photovoltaic Detectors. Thermal Detectors. Schottky-Barrier Photodiodes. Infrared Search Systems. Modulation Transfer Function. Thermal-Imager Systems. Appendices. Index.

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Book SynopsisTakes a fresh look at basic digital design. From definition, to example, to graphic illustration, to simulation result, the book progresses through the main themes of digital design. Technically up-to-date, this book covers all the latest topics: Field programmable gate arrays, PALs and ROMs. The latest memory chips for SRAM and DRAM are shown. Software for creating the excitation equations of FSM are covered, as well as LogicWorks and Beige Bag PC and more.Table of ContentsCOMBINATIONAL LOGIC. From Numbers to Switches. Truth Tables and Boolean Algebra. Map and Table Methods for Minimizing Boolean Expressions. Programmable Circuits for Combinational Design. SEQUENTIAL DESIGN. Evolution of Flip-Flops. Synchronous Counters. Synchronous Finite State Machines. MASTERING DESIGN. Memory. Digital Communication and Serial Transmission. Arithmetic Hardware. Register Transfer Logic. Index.

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Book SynopsisSingh provides hands-on and research knowledge to a broad audience to help them get past very serious design problems. It covers signal integrity effects in high performance radio frequency IC designs, and substrate coupling.Trade Review"In the era of System-on-Chip, when large portions of the overall system are integrated on one large chip, designers are facing increasingly challenging issues. For the first time, this book is taking a closer look at the signal integrity problems faced by both high-performance and cost-performance applications, digital and mixed-signal integrated circuits. System designers are given guidance in power distribution analysis, interconnect optimization, and mixed, digital-analog circuit integration challenges. Researchers and CAD engineers can get an in-depth view of the current and future requirements for full-chip CAD tools, on-chip transmission line designs, integrated passive components, and many other critical signal integrity issues. This book is bringing together a broad range of representative papers that will further the understanding both in the industrial and academic communities." (Alina Deutsch, Research Staff Member, T.J. Watson Research Center, International Business Machines) "Electrical integrity (or environment noise) is becoming the principal obstacle in system-on-a-chip design. Digital circuits create a very noisy environment in which other digital and analog circuits must function. This environmental noise comes about because of coupling through the interconnect, power supply, and substrate. This book surveys the latest literature on electrical integrity analysis and design and is, therefore, an invaluable resource for anyone designing systems-on-a-chip." (Kenneth L. Shepard, Professor, Columbia University) "The explosion of wireless communications that offer greater mobility and broadband communications that provide super fast access to the Internet have placed new demands on IC designers. The key to developing successful Systems on Chip designs that offer Analog and Mixed Signal capabilities is the approach used to extract and analyze the affects of parasitics on signal integrity. This book offers a tutorial guide to IC designers who want to move to the next level of chip design by unlocking the secrets of signal integrity." (Jake Buurma Senior Vice President, Worldwide Research & Development, Cadence Design Systems, Inc.) "As technology scales to .1 micron and below, second order effects due to physical phenomena that were not much visible before start playing a more and more significant role. So much so that well-established methodologies and tools are not providing the necessary level of confidence to the designer that her/his integrated circuit will perform as planned. The need for more accurate extraction and analysis is obvious when we observe horror stories about very hard to detect intermittent faults created by interactions among signals on different wires. There are two complementary approaches to the problem that come to mind as always when we go over the limit of previous methods - increase the accuracy of the analysis tools, and/or solve the problems by imposing constraints on the degrees of freedom left to the designer. This collection of papers covers both in details. It is the most comprehensive syllabus of important results for researchers and designers on the topic. I highly recommend to read it and to pay attention to the messages given by the papers of the collection." (Alberto Sangiovanni-Vincentelli, Professor, University of California Berkeley)Table of ContentsForeword. From the Early Days of CMOS to Today. Signal Integrity: A Problem for Design and CAD Engineers. Preface. Acknowledgments. Signal Integrity Effects in Systme-on-Chip Designs - A Designer's Perspective. Part 1: Interconnect Crosstalk. Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits. FastCap: A Multipole Accelerated 3-D Capacitance Extraction Program. Efficient Coupled Noise Estimation for On-Chip Interconnects. Switching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise. Digital Sensitivity: Predicting Signal Interaction using Functional Analysis. Crosstalk Reduction for VLSI. Noise-aware Repeater Insertion and Wire Sizing For On-Chip Interconnect Hierarchical Moment-Matching. Post Global Routing Crosstalk Synthesis. Minimum Crosstalk Channel Routing. Reducing Cross-Coupling among Interconnect Wires in Deep-Submicron Datapath Design. A Postprocessing Algorithm for Crosstalk-driven Wire Perturbation. Noise in Digital Dynamic CMOS Circuits. Design of Dynamic Circuits with Enhanced Noise Tolerance. Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. High Frequency Simulation and Characterization of Advanced Copper Interconnects. Static Noise Analysis for Digital Integrated Circuits in Partially-Depleted Silicon-On-Insulator Technology. Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. Part 2: Inductance Effects. On-Chip Wiring Design Challenges for Gigahertz Operation. IC Analyses Including Extracted Inductance Models. FASTHENRY: A Multipole-Accelerated 3-D Inductance Extraction Program. Full-Chip, Three-Dimensional, Shapes-Based RLC Extraction. On-Chip Inductance Modeling and Analysis. How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K. Figures of Merit to Characterize the Importance of On-Chip Inductance. Layout-Techniques for Minimizing On-Chip Interconnect Self Inductance. A Twisted-Bundle Layout Structure for Minimizing Inductive Coupling Noise. Part 3: Power Grid and Distribution Noise. Full-Chip Verification of UDSM Designs. Power Supply Noise in Future IC's: A Crystal Ball Reading. A Floorplan-based Planning Methodology for Power and Clock Distribution in ASICs. Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design. Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices. Full-Chip Signal Interconnect Analysis for Electromigration Reliability. Power Dissipation Analysis and Optimization of Deep Submicron CMOS Digital Circuits. Simulation and Optimization of the Power Distribution Network in VLSI Circuits. Design Strategies and Decoupling Techniques for Reducing the Effects of Electrical Interference in Mixed-Mode IC's. Design and Analysis of Power Distribution Networks in Power PC Microprocessors. Modeling the Power and Ground Effects of BGA Packages. Effects of Power/Ground Via Distribution on the Power/Ground Performance of C4/BGA Packages. Power Distribution Fidelity of Wirebond Compared to Flip Chip Devices in Grid Array Packages. Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers. Part 4: Substrate Noise. Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits. Principles of Substrate Crosstalk Generation in CMOS Circuits. Experimental Comparison of Substrate Noise Coupling Using Different Wafer Types. Modeling and Analysis of Substrate Coupling in Integrated Circuits. Fast Methods for Extraction and Sparsification of Substrate Coupling. SUBWAVE: A Methodology for Modeling Digital Substrate Noise Injection in Mixed-Signal ICs. Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation. Analysis of Ground-Bounce Induced Substrate Noise Coupling in a Low Resistive Bulk Epitaxial Process: Design Strategies to Minimize Noise Effects on a Mixed-Signal Chip. A Methodology for Measurement and Characterization of Substrate Noise in High Frequency Circuits. Measurement of Digital Noise in Mixed-Signal Integrated Circuits. Effects of Substrate Resistances on LNA Performance and a Bondpad Structure for Reducing the Effects in a Silicon Bipolar Technology. A Study of Oscillator Jitter Due to Supply and Substrate Noise. CMOS Technology Characterization for Analog and RF Design. Noise Reduction Is Crucial to Mixed-Signal ASIC Design Success (Parts I & II). Author Index. Subject Index. About the Editor.

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Book SynopsisA detailed, modern introduction to semiconductors made in silicon and III-V compounds. This book develops the device physics of pn junctions, bipolar transistors, Schottky barriers, MOS capacitors, and MOS field-effect transistors (MOSFETs).Table of ContentsIntegrated Circuit Family Tree Electrons in Solids Carrier Transport and Recombination p-n Junctions: I-V Behavior p-n Junctions: Reverse Breakdown and Junction Capacitance Schottky-Barrier Devices MOS Capacitors MOS Field-Effect Transistors Bipolar Transistors Appendix I: Introduction to PSPICE

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Book SynopsisThe definitive one-stop guide to selecting and using all types of electronic components, including. Resistors Capacitors Chokes, Inductors, and Transformers Delay Lines, Connectors, and Interconnection Devices Switches, Relays, and Contactors Wire and Cable Discrete Semiconductors Integrated Circuits.Table of ContentsThe Parts Selection Process. Resistors. Capacitors. Chokes, Coils, Inductors, and Transformers. Delay Lines. Connectors and Interconnection Devices. Switches. Relays and Contactors. Wire and Cable. Discrete Semiconductors. Integrated Circuits. Sources of Information, Specifications, and Parts. Standards/Trade Organizations. Thermistors. Index.

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Book SynopsisThe tools and techniques you need to break the analog design bottleneck! Ten years ago, analog seemed to be a dead-end technology. Today, System-on-Chip (SoC) designs are increasingly mixed-signal designs. With the advent of application-specific integrated circuits (ASIC) technologies that can integrate both analog and digital functions on a single chip, analog has become more crucial than ever to the design process. Today, designers are moving beyond hand-crafted, one-transistor-at-a-time methods. They are using new circuit and physical synthesis tools to design practical analog circuits; new modeling and analysis tools to allow rapid exploration of system level alternatives; and new simulation tools to provide accurate answers for analog circuit behaviors and interactions that were considered impossible to handle only a few years ago. To give circuit designers and CAD professionals a better understanding of the history and the current state of the art in the field, this volumTable of ContentsPreface ix Acknowledgments xi Part I Introduction to Analog CAD Part II Analog Synthesis Part III Symbolic Analysis Part IV Analog Layout Part V Analog Modeling Analysis Part VI Spec Simulation Part VII Analog Centering and Yield Optimization Part VIII Analog Test About the Editors 754

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Book SynopsisPresenting survey in Integrated Passive Component Technology, this title describes the processes available for creating integrated passives, measuring their properties, and applying them.Trade Review"…a comprehensive look at the reasons and current challenges…[of integrating] passive devices into board or IC…just the right dose of the math to explain the physics and theory behind the technology." (IEEE Circuits & Devices Magazine, Jan/Feb 2005) "...an interesting and useful book; I wholeheartedly recommend it."(Circuit World, Vol.30, No. 2003)Table of ContentsContributors. Preface. 1 Introduction (Richard K. Ulrich). 1.1 Status and Trends in Discrete Passive Components. 1.2 Definitions and Configurations of Integrated Passives. 1.3 Comparison to Integrated Active Devices. 1.4 Substrates and Interconnect Systems for Integrated Passives. 1.5 Fabrication of Integrated Passives. 1.6 Reasons for Integrating Passive Devices. 1.7 Problems with Integrating Passive Devices. 1.8 Applications for Integrated Passives. 1.9 The Past and Future of Integrated Passives. 1.10 Organization of this Book. References. 2 Characteristics and Performance of Planar Resistors (Richard K. Ulrich). 2.1 Performance Parameters. 2.2 Resistance in Electronic Materials. 2.3 Sizing Integrated Resistors. 2.4 Trimming. References. 3 Integrated Resistor Materials and Processes (Richard K. Ulrich). 3.1 Single-Component Metals. 3.2 Metal Alloys and Metal–Nonmetal Compounds. 3.3 Semiconductors. 3.4 Cermets. 3.5 Polymer Thick Film. 3.6 Ink Jet Deposition. 3.7 Commercialized Processes. 3.8 Summary. References. 4 Dielectric Materials for Integrated Capacitors (Richard K. Ulrich). 4.1 Polarizability and Capacitance. 4.2 Capacitance Density. 4.3 Temperature Effects. 4.4 Frequency and Voltage Effects. 4.5 Aging Effects. 4.6 Composition and Morphology Effects. 4.7 Leakage and Breakdown. 4.8 Dissipation Factor. 4.9 Comparison to EIA Dielectric Classifications. 4.10 Matching Dielectric Materials to Applications. References. 5 Size and Configuration of Integrated Capacitors (Richard K. Ulrich). 5.1 Comparison of Integrated and Discrete Areas. 5.2 Layout Options. 5.3 Tolerance. 5.4 Mixed Dielectric Strategies. 5.5 CV Product. 5.6 Maximum Capacitance Density and Breakdown Voltage. References. 6 Processing Integrated Capacitors (Richard K. Ulrich). 6.1 Sputtering. 6.2 CVD, PECVD and MOCVD. 6.3 Anodization. 6.4 Sol-Gel and Hydrothermal Ferroelectrics. 6.5 Thin- and Thick-Film Polymers. 6.6 Thick-Film Dielectrics. 6.7 Interlayer Insulation. 6.8 Interdigitated Capacitors. 6.9 Capacitor Plate Materials. 6.10 Trimming Integrated Capacitors. 6.11 Commercialized Integrated Capacitor Technologies. 6.12 Summary. References. 7 Defects and Yield Issues (Richard K. Ulrich). 7.1 Causes of Fatal Defects in Integrated Capacitors. 7.2 Measurement of Defect Density. 7.3 Defect Density and System Yield. 7.3.1 Predicting Yield from Defect Density. 7.4 Yield Enhancement Techniques for Capacitors. 7.5 Conclusions. References. 8 Electrical Performance of Integrated Capacitors (Richard K. Ulrich and Leonard W. Schaper). 8.1 Modeling Ideal Passives. 8.2 Modeling Real Capacitors. 8.3 Electrical Performance of Discrete and Integrated Capacitors. 8.4 Dissipation Factor of Real Capacitors. 8.5 Measurement of Capacitor Properties. 8.6 Summary. References. 9 Decoupling (Leonard W. Schaper). 9.1 Power Distribution. 9.2 Decoupling with Discrete Capacitors. 9.3 Decoupling with Integrated Capacitors. 9.4 Dielectrics and Configurations for Integrated Decoupling. 9.5 Integrated Decoupling as an Entry Application. References. 10 Integrated Inductors (Geert J. Carchon and Walter De Raedt). 10.1 Introduction. 10.2 Inductor Behavior and Performance Parameters. 10.3 Inductor Performance Prediction. 10.4 Integrated Inductor Examples. 10.5 Use of Inductors in Circuits: Examples. 10.6 Conclusions. Acknowledgments. References. 11 Modeling of Integrated Inductors and Resistors for Microwave Applications (Zhenwen Wang, M. Jamal Deen, and A. H. Rahal). 11.1 Introduction. 11.2 Modeling of Spiral Inductors. 11.3 Modeling of Thin-Film Resistors. 11.4 Conclusions. References. Appendix: Characteristics of Microscript Lines. 12 Other Applications and Integration Technologies (Elizabeth Logan, Geert J. Carchon, Walter De Raedt, Richard K. Ulrich, and Leonard W. Schaper). 12.1 Demonstration Devices Fabricated with Integrated Passives. 12.2 Commercialized Thin-Film Build-Up Integrated Passives. 12.3 Other Integrated Passive Technologies. 12.4 Summary. Acknowledgments. References. 13 The Economics of Embedded Passives (Peter A. Sandborn). 13.1 Introduction. 13.2 Modeling Embedded Passive Economics. 13.3 Key Aspects of Modeling Embedded Passive Costs. 13.4 Example Case Studies. 13.5 Summary. Acknowledgments. References. 14 The Future of Integrated Passives (Richard K. Ulrich). 14.1 Status of Passive Integration. 14.2 Issues for Implementation on Organic Substrates. 14.3 Progress on Board-Level Implementation. 14.4 Three Ways In for Organic Boards. 14.5 Conclusion. Index. About the Editors.

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Book SynopsisThis book is an introduction on the principles of digital logic circuits. While providing coverage to the usual topics in combinational and sequential circuit principles, it also includes a chapter on the use of the hardware description language ABEL in the design of circuits using PLDs and a chapter on computer organization.Table of ContentsNumber Representation, Codes, and Code Conversion. Switching Algebra and Logic Gates. Representation and Implementation of Logic Functions. Combinational Logic Design. Sequential Circuit Components. Synchronous Sequential Machines. Asynchronous Sequential Machines. Design Using Hardware Description Languages. Computer Organization. Appendix: MOSFETS and Bipolar Junction Transistors. Bibliography. Index.

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Book SynopsisRoubik Gregorian, a well-known industry expert, provides circuit designers with the technical knowledge needed to design high-performance op-amps and comparators suitable for most analog circuit applications.Table of ContentsMOS Devices as Circuit Elements. Basic Analog CMOS Subcircuits. CMOS Operational Amplifier. Comparators. Digital-to-Analog Converters. Analog-to-Digital Converters. Practical Considerations and Design Examples. Index.

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Book SynopsisPraise for the First Edition . . . A unique piece of work, a book for electronics engineering, in general, but well suited and excellently applicable also to biomedical engineering . . . I recommend it with no reservation, congratulating the authors for the job performed. -IEEE Engineering in Medicine & Biology Describes a broad range of sensors in practical use and some circuit designs; copious information about electronic components is supplied, a matter of great value to electronic engineers. A large number of applications are supplied for each type of sensor described . . . This volume is of considerable importance.-Robotica In this new edition of their successful book, renowned authorities Ramon Pallàs-Areny and John Webster bring you up to speed on the latest advances in sensor technology, addressing both the explosive growth in the use of microsensors and improvements made in classical macrosensors. They continue to offer the only combined treatment foTrade Review"...It is sufficiently detailed to be useful to just about anyone involved with sensor development and implementation..." (n-lux.net, 4 February 2003)Table of ContentsIntroduction to Sensor-Based Measurement Systems. Resistive Sensors. Signal Conditioning for Resistive Sensors. Reactance Variation and Electromagnetic Sensors. Signal Conditioning for Reactance Variation Sensors. Self-Generating Sensors. Signal Conditioning for Self-Generating Sensors. Digital and Intelligent Sensors. Other Sensing Methods. Appendix. Index.

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Book SynopsisA cutting-edge guide to the theory and practice of high-speed digital system design An understanding of high-speed interconnect phenomena is essential for digital designers who must deal with the challenges posed by the ever-increasing operating speeds of today''s microprocessors. This book provides a much-needed, practical guide to the state of the art of modern digital system design, combining easily accessible explanations with immensely useful problem-solving strategies. Written by three leading Intel engineers, High-Speed Digital System Design clarifies difficult and often neglected topics involving the effects of high frequencies on digital buses and presents a variety of proven techniques and application examples. Extensive appendices, formulas, modeling techniques as well as hundreds of figures are also provided. Coverage includes: * A thorough introduction to the digital aspects of basic transmission line theory * Crosstalk and nonideal transmissTrade Review"...an excellent guidebook for interconnect design...this very valuable work is highly recommended for design engineers and recent graduates struggling to transition from theory to real-world design." (Choice, Vol. 38, No. 8, April 2001) "This is an excellent book for anyone who has basic circuit theory knowledge.... It is a recommended book for all academic engineering libraries and would, also, be useful for the practicing engineer." (E-Streams, Vol. 4, No. 8, August 2001)Table of ContentsPreface. 1. The Importance of Interconnect Design. 1.1 The Basics. 1.2 The Past and the Future. 2. Ideal Transmission Line Fundamentals. 2.1 Transmission Line Structures on a PCB or MCM. 2.2 Wave Propagation. 2.3 Transmission Line Parameters. 2.3.1 Characteristic Impedance. 2.3.2 Propagation Velocity, Time, and Distance. 2.3.3 Equivalent Circuit Models for SPICE Simulation. 2.4 Launching Initial Wave and Transmission Line Reflections. 2.4.1 Initial Wave. 2.4.2 Multiple Reflections. 2.4.3 Effect of Rise Time on Reflections. 2.4.4 Reflections From Reactive Loads. 2.4.5 Termination Schemes to Eliminate Reflections. 2.5 Additional Examples. 2.5.1 Problem. 2.5.2 Goals. 2.5.3 Calculating the Cross-Sectional Geometry of the PCB. 2.5.4 Calculating the Propagation Delay. 2.5.5 Determining the Wave Shape Seen at the Receiver. 2.5.6 Creating an Equivalent Circuit. 3. Crosstalk. 3.1 Mutual Inductance and Mutual Capacitance. 3.2 Inductance and Capacitance Matrix. 3.3 Field Simulators. 3.4 Crosstalk-Induced Noise. 3.5 Simulating Crosstalk Using Equivalent Circuit Models. 3.6 Crosstalk-Induced Flight Time and Signal Integrity Variations. 3.6.1 Effect of Switching Patterns on Transmission Line Performance. 3.6.2 Simulating Traces in a Multiconductor System Using a Single-Line Equivalent Model. 3.7 Crosstalk Trends. 3.8 Termination of Odd- and Even-Mode Transmission Line Pairs. 3.8.1 Pi Termination Network. 3.8.2 T Termination Network. 3.9 Minimization of Crosstalk. 3.10 Additional Examples. 3.10.1 Problem. 3.10.2 Goals. 3.10.3 Determining the Maximum Crosstalk-Induced Impedance and Velocity Swing. 3.10.4 Determining if Crosstalk Will Induce False Triggers. 4. Nonideal Interconnect Issues. 4.1 Transmission Line Losses. 4.1.1 Conductor DC Losses. 4.1.2 Dielectric DC Losses. 4.1.3 Skin Effect. 4.1.4 Frequency-Dependent Dielectric Losses. 4.2 Variations in the Dielectric Constant. 4.3 Serpentine Traces. 4.4 Intersymbol Interference. 4.5 Effects of 90 Bends. 4.6 Effect of Topology. 5. Connectors, Packages, and Vias. 5.1 Vias. 5.2 Connectors. 5.2.1 Series Inductance. 5.2.2 Shunt Capacitance. 5.2.3 Connector Crosstalk. 5.2.4 Effects of Inductively Coupled Connector Pin Fields. 5.2.5 EMI. 5.2.6 Connector Design Guidelines. 5.3 Chip Packages. 5.3.1 Common Types of Packages. 5.3.2 Creating a Package Model. 5.3.3 Effects of a Package. 5.3.4 Optimal Pin-Outs. 6. Nonideal Return Paths, Simultaneous Switching Noise, and Power Delivery. 6.1 Nonideal Current Return Paths. 6.1.1 Path of Least Inductance. 6.1.2 Signals Traversing a Ground Gap. 6.1.3 Signals That Change Reference Planes. 6.1.4 Signals Referenced to a Power or a Ground Plane. 6.1.5 Other Nonideal Return Path Scenarios. 6.1.6 Differential Signals. 6.2 Local Power Delivery Networks. 6.2.1 Determining the Local Decoupling Requirements for High-Speed I/O. 6.2.2 System-Level Power Delivery. 6.2.3 Choosing a Decoupling Capacitor. 6.2.4 Frequency Response of a Power Delivery System. 6.3 SSO/SSN. 6.3.1 Minimizing SSN. 7. Buffer Modeling. 7.1 Types of Models. 7.2 Basic CMOS Output Buffer. 7.2.1 Basic Operation. 7.2.2 Linear Modeling of the CMOS Buffer. 7.2.3 Behavioral Modeling of the Basic CMOS Buffer. 7.3 Output Buffers That Operate in the Saturation Region. 7.4 Conclusions. 8. Digital Timing Analysis. 8.1 Common-Clock Timing. 8.1.1 Common-Clock Timing Equations. 8.2 Source Synchronous Timing. 8.2.1 Source Synchronous Timing Equations. 8.2.2 Deriving Source Synchronous Timing Equations from an Eye Diagram. 8.2.3 Alternative Source Synchronous Schemes. 8.3 Alternative Bus Signaling Techniques. 8.3.1 Incident Clocking. 8.3.2 Embedded Clock. 9. Design Methodologies. 9.1 Timings. 9.1.1 Worst-Case Timing Spreadsheet. 9.1.2 Statistical Spreadsheets. 9.2 Timing Metrics, Signal Quality Metrics, and Test Loads. 9.2.1 Voltage Reference Uncertainty. 9.2.2 Simulation Reference Loads. 9.2.3 Flight Time. 9.2.4 Flight-Time Skew. 9.2.5 Signal Integrity. 9.3 Design Optimization. 9.3.1 Paper Analysis. 9.3.2 Routing Study. 9.4 Sensitivity Analysis. 9.4.1 Initial Trend and Significance Analysis. 9.4.2 Ordered Parameter Sweeps. 9.4.3 Phase 1 Solution Space. 9.4.4 Phase 2 Solution Space. 9.4.5 Phase 3 Solution Space. 9.5 Design Guidelines. 9.6 Extraction. 9.7 General Rules of Thumb to Follow When Designing a System. 10. Radiated Emissions Compliance and System Noise Minimization. 10.1 FCC Radiated Emission Specifications. 10.2 Physical Mechanisms of Radiation. 10.2.1 Differential-Mode Radiation. 10.2.2 Common-Mode Radiation. 10.2.3 Wave Impedance. 10.3 Decoupling and Choking. 10.3.1 High-Frequency Decoupling at the System Level. 10.3.2 Choking Cables and Localized Power and Ground Planes. 10.3.3 Low-Frequency Decoupling and Ground Isolation. 10.4 Additional PCB Design Criteria, Package Considerations, and Pin-Outs. 10.4.1 Placement of High-Speed Components and Traces. 10.4.2 Crosstalk. 10.4.3 Pin Assignments and Package Choice. 10.5 Enclosure (Chassis) Considerations. 10.5.1 Shielding Basics. 10.5.2 Apertures. 10.5.3 Resonances. 10.6 Spread Spectrum Clocking. 11. High-Speed Measurement Techniques. 11.1 Digital Oscilloscopes. 11.1.1 Bandwidth. 11.1.2 Sampling. 11.1.3 Other Effects. 11.1.4 Statistics. 11.2 Time-Domain Reflectometry. 11.2.1 TDR Theory. 11.2.2 Measurement Factors. 11.3 TDR Accuracy. 11.3.1 Launch Parasitics. 11.3.2 Probe Types. 11.3.3 Reflections. 11.3.4 Interface Transmission Loss. 11.3.5 Cable Loss. 11.3.6 Amplitude Offset Error. 11.4 Impedance Measurement. 11.4.1 Accurate Characterization of Impedance. 11.4.2 Measurement Region in TDR Impedance Profile. 11.5 Odd- and Even-Mode Impedance. 11.6 Crosstalk Noise. 11.7 Propagation Velocity. 11.7.1 Length Difference Method. 11.7.2 Y-Intercept Method. 11.7.3 TDT Method. 11.8 Vector Network Analyzer. 11.8.1 Introduction to S Parameters. 11.8.2 Equipment. 11.8.3 One-Port Measurements (ZO,L,C). 11.8.4 Two-Port Measurements (Td, Attenuation, Crosstalk). 11.8.5 Calibration. 11.8.6 Calibration for One-Port Measurements. 11.8.7 Calibration for Two-Port Measurements. 11.8.8 Calibration Verification. Appendix A: Alternative Characteristic Impedance Formulas. A.1 Microstrip. A.2 Symmetric Stripline. A.3 Offset Stripline. Appendix B: GTL Current-Mode Analysis. B.1 Basic GTL Operation. B.2 GTL Transitions When a Middle Agent Is Driving. B.3 GTL Transitions When an End Agent With a Termination Is Driving. B.4 Transitions When There is a Pull-Up at the Middle Agent. Appendix C: Frequency-Domain Components in a Digital Signal. Appendix D: Useful S-Parameter Conversions. D.1 ABCD, Z, and Y Parameters. D.2 Normalizing the S Matrix to a Different Characteristic Impedance. D.3 Derivation of the Formulas Used to Extract the Mutual Inductance and Capacitance from a Short Structure Using S21 Measurements. D.4 Derivation of the Formula to Extract Skin Effect Resistance from a Transmission Line. Appendix E: Definition of the Decibel. Appendix F: FCC Emission Limits. Bibliography. Index.

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Book Synopsis* Introduces the operational amplifier early, and uses it as a basic element throughout the book. * Provides numerous exercises and examples throughout. * Written in a clear, precise style that has been highly praised throughout many editions. .

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Book SynopsisKalman filtering is a well-established topic in the field of control and signal processing and represents by far the most refined method for the design of neural networks. This book takes a nontraditional nonlinear approach and reflects the fact that most practical applications are nonlinear.Trade Review"Although the traditional approach to the subject is usually linear, this book recognizes and deals with the fact that real problems are most often nonlinear." (SciTech Book News, Vol. 25, No. 4, December 2001)Table of ContentsPreface. Contributors. Kalman Filters (S. Haykin). Parameter-Based Kalman Filter Training: Theory and Implementaion (G. Puskorius and L. Feldkamp). Learning Shape and Motion from Image Sequences (G. Patel, et al.). Chaotic Dynamics (G. Patel and S. Haykin). Dual Extended Kalman Filter Methods (E. Wan and A. Nelson). Learning Nonlinear Dynamical System Using the Expectation-Maximization Algorithm (S. Roweis and Z. Ghahramani). The Unscencted Kalman Filter (E. Wan and R. van der Merwe). Index.

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Book SynopsisRadio-Frequency Integrated-Circuit Engineering addresses the theory, analysis and design of passive and active RFIC''s using Si-based CMOS and Bi-CMOS technologies, and other non-silicon based technologies. The materials covered are self-contained and presented in such detail that allows readers with only undergraduate electrical engineering knowledge in EM, RF, and circuits to understand and design RFICs. Organized into sixteen chapters, blending analog and microwave engineering, Radio-Frequency Integrated-Circuit Engineering emphasizes the microwave engineering approach for RFICs. * Provides essential knowledge in EM and microwave engineering, passive and active RFICs, RFIC analysis and design techniques, and RF systems vital for RFIC students and engineers * Blends analog and microwave engineering approaches for RFIC design at high frequencies * Includes problems at the end of each chapterTable of ContentsPreface xvii 1 Introduction 1 Problems 5 2 Fundamentals of Electromagnetics 6 2.1 EM Field Parameters 6 2.2 Maxwell’s Equations 7 2.3 Auxiliary Relations 8 2.3.1 Constitutive Relations 8 2.3.2 Current Relations 9 2.4 Sinusoidal Time-Varying Steady State 9 2.5 Boundary Conditions 10 2.5.1 General Boundary Conditions 11 2.5.2 Specific Boundary Conditions 11 2.6 Wave Equations 12 2.7 Power 13 2.8 Loss and Propagation Constant in Medium 14 2.9 Skin Depth 16 2.10 Surface Impedance 17 Problems 19 3 Lumped Elements 20 3.1 Fundamentals of Lumped Elements 20 3.1.1 Basic Equations 23 3.2 Quality Factor of Lumped Elements 28 3.3 Modeling of Lumped Elements 30 3.4 Inductors 32 3.4.1 Inductor Configurations 32 3.4.2 Loss in Inductors 36 3.4.3 Equivalent-Circuit Models of Inductors 39 3.4.4 Resonance in Inductors 45 3.4.5 Quality Factor of Inductors 46 3.4.6 High Q Inductor Design Considerations 51 3.5 Lumped-Element Capacitors 60 3.5.1 Capacitor Configurations 60 3.5.2 Equivalent-Circuit Models of Capacitors 63 3.5.3 Resonance 68 3.5.4 Quality Factor 69 3.5.5 High Q Capacitor Design Considerations 71 3.6 Lumped-Element Resistors 72 3.6.1 Resistor Configurations 72 3.6.2 Basic Resistor Equations 72 3.6.3 Equivalent-Circuit Models of Resistors 75 References 75 Problems 76 4 Transmission Lines 85 4.1 Essentials of Transmission Lines 85 4.2 Transmission-Line Equations 86 4.2.1 General Transmission-Line Equations 86 4.2.2 Sinusoidal Steady-State Transmission-Line Equations 91 4.3 Transmission-Line Parameters 93 4.3.1 General Transmission Lines 93 4.3.2 Lossless Transmission Lines 96 4.3.3 Low Loss Transmission Lines 96 4.4 Per-Unit-Length Parameters R,L,C, and G 97 4.4.1 General Formulation 97 4.4.2 Formulation for Simple Transmission Lines 104 4.5 Dielectric and Conductor Losses in Transmission Lines 107 4.5.1 Dielectric Attenuation Constant 108 4.5.2 Conductor Attenuation Constant 109 4.6 Dispersion and Distortion in Transmission Lines 111 4.6.1 Dispersion 111 4.6.2 Distortion 111 4.6.3 Distortion-Less Transmission Lines 113 4.7 Group Velocity 115 4.8 Impedance, Reflection Coefficients, and Standing-Wave Ratios 117 4.8.1 Impedance 117 4.8.2 Reflection Coefficients 119 4.8.3 Standing-Wave Ratio 120 4.8.4 Perfect Match and Total Reflection 122 4.8.5 Lossless Transmission Lines 123 4.9 Synthetic Transmission Lines 126 4.10 Tem and Quasi-Tem Transmission-Line Parameters 128 4.10.1 Static or Quasi-Static Analysis 129 4.10.2 Dynamic Analysis 130 4.11 Printed-Circuit Transmission Lines 132 4.11.1 Microstrip Line 133 4.11.2 CoplanarWaveguide 135 4.11.3 Coplanar Strips 138 4.11.4 Strip Line 139 4.11.5 Slot Line 141 4.11.6 Field Distributions 142 4.12 Transmission Lines in RFICs 144 4.12.1 Microstrip Line 145 4.12.2 CoplanarWaveguide 146 4.12.3 Coplanar Strips 149 4.12.4 Strip Line 149 4.12.5 Slot Line 150 4.12.6 Transitions and Junctions Between Transmission Lines 150 4.13 Multi-Conductor Transmission Lines 152 4.13.1 Transmission-Line Equations 152 4.13.2 Propagation Modes 156 4.13.3 Characteristic Impedance and Admittance Matrix 157 4.13.4 Mode Characteristic Impedances and Admittances 159 4.13.5 Impedance and Admittance Matrix 161 4.13.6 Lossless Multiconductor Transmission Lines 163 References 173 Problems 174 Appendix 4: Transmission-Line Equations Derived From Maxwell’s Equations 182 5 Resonators 186 5.1 Fundamentals of Resonators 186 5.1.1 Parallel Resonators 187 5.1.2 Series Resonators 188 5.2 Quality Factor 189 5.2.1 Parallel Resonators 190 5.2.2 Series Resonators 193 5.2.3 Unloaded Quality Factor 195 5.2.4 Loaded Quality Factor 195 5.2.5 Evaluation of and Relation between Unloaded and Loaded Quality Factors 198 5.3 Distributed Resonators 205 5.3.1 Quality-Factor Characteristics 206 5.3.2 Transmission-Line Resonators 207 5.3.3 Waveguide Cavity Resonators 216 5.4 Resonator’s Slope Parameters 231 5.5 Transformation of Resonators 231 5.5.1 Impedance and Admittance Inverters 231 5.5.2 Examples of Resonator Transformation 236 References 237 Problems 238 6 Impedance Matching 244 6.1 Basic Impedance Matching 244 6.1.1 Smith Chart 244 6.2 Design of Impedance-Matching Networks 248 6.2.1 Impedance-Matching Network Topologies 249 6.2.2 Impedance Transformation through Series and Shunt Inductor and Capacitor 249 6.2.3 Examples of Impedance-Matching Network Design 252 6.2.4 Transmission-Line Impedance-Matching Networks 255 6.3 Kuroda Identities 262 References 266 Problems 266 7 Scattering Parameters 271 7.1 Multiport Networks 271 7.2 Impedance Matrix 273 7.3 Admittance Matrix 274 7.4 Impedance and Admittance Matrix in RF Circuit Analysis 274 7.4.1 T-Network Representation of Two-Port RF Circuits 275 7.4.2 π-Network Representation of Two-Port RF Circuits 278 7.5 Scattering Matrix 279 7.5.1 Fundamentals of Scattering Matrix 279 7.5.2 Examples for Scattering Parameters 287 7.5.3 Effect of Reference-Plane Change on Scattering Matrix 288 7.5.4 Return Loss, Insertion Loss, and Gain 290 7.6 Chain Matrix 293 7.7 Scattering Transmission Matrix 294 7.8 Conversion between Two-Port Parameters 295 7.8.1 Conversion from [Z] to [ABCD] 295 References 298 Problems 298 8 RF Passive Components 304 8.1 Characteristics of Multiport RF Passive Components 304 8.1.1 Characteristics of Three-Port Components 304 8.1.2 Characteristics of Four-Port Components 309 8.2 Directional Couplers 311 8.2.1 Fundamentals of Directional Couplers 311 8.2.2 Parallel-Coupled Directional Couplers 313 8.3 Hybrids 326 8.3.1 Hybrid T 326 8.3.2 Ring Hybrid 328 8.3.3 Branch-Line Coupler 335 8.4 Power Dividers 339 8.4.1 Even-Mode Analysis 340 8.4.2 Odd-Mode Analysis 342 8.4.3 Superimposition of Even and Odd Modes 343 8.5 Filters 345 8.5.1 Low Pass Filter 345 8.5.2 High Pass Filter Design 357 8.5.3 Band-Pass Filter Design 359 8.5.4 Band-Stop Filter Design 361 8.5.5 Filter Design Using Impedance and Admittance Inverters 364 References 371 Problems 372 9 Fundamentals of CMOS Transistors For RFIC Design 379 9.1 MOSFET Basics 379 9.1.1 MOSFET Structure 379 9.1.2 MOSFET Operation 382 9.2 MOSFET Models 386 9.2.1 Physics-Based Models 387 9.2.2 Empirical Models 387 9.2.3 SPICE Models 402 9.2.4 Passive MOSFET Models 404 9.3 Important MOSFET Frquencies 407 9.3.1 fT 408 9.3.2 fmax 408 9.4 Other Important MOSFET Parameters 409 9.5 Varactor Diodes 409 9.5.1 Varactor Structure and Operation 409 9.5.2 Varactor Model and Characteristics 410 References 412 Problems 412 10 Stability 418 10.1 Fundamentals of Stability 418 10.2 Determination of Stable and Unstable Regions 421 10.3 Stability Consideration for N-Port Circuits 427 References 427 Problems 428 11 Amplifiers 430 11.1 Fundamentals of Amplifier Design 430 11.1.1 Power Gain 430 11.1.2 Gain Design 433 11.2 Low Noise Amplifiers 443 11.2.1 Noise Figure Fundamentals 443 11.2.2 MOSFET Noise Parameters 446 11.2.3 Noise Figure of Multistage Amplifiers 447 11.2.4 Noise-Figure Design 448 11.2.5 Design for Gain and Noise Figure 450 11.3 Design Examples 451 11.3.1 Unilateral Amplifier Design 451 11.3.2 Bilateral Amplifier Design 454 11.4 Power Amplifiers 455 11.4.1 Power-Amplifier Parameters 455 11.4.2 Power-Amplifier Types 458 11.5 Balanced Amplifiers 470 11.5.1 Differential Amplifiers 470 11.5.2 Ninety-Degree Balanced Amplifiers 485 11.5.3 Push–Pull Amplifiers 487 11.6 Broadband Amplifiers 489 11.6.1 Compensated Matching Networks 489 11.6.2 Distributed Amplifiers 490 11.6.3 Feedback Amplifiers 523 11.6.4 Cascoded Common-Source Amplifiers 540 11.7 Current Mirrors 548 11.7.1 Basic Current Mirror 550 11.7.2 Cascode Current Mirror 550 References 552 Problems 553 A11.1 Fundamentals of Signal Flow Graph 563 A11.2 Signal Flow Graph of Two-Port Networks 563 A11.2.1 Transistor’s Signal Flow Graph 563 A11.2.2 Input Matching Network’s Signal Flow Graph 564 A11.2.3 Output Matching Network’s Signal Flow Graph 565 A11.2.4 Signal Flow Graph of the Composite Two-Port Network 566 A11.3 Derivation of Network’s Parameters Using Signal Flow Graphs 566 A11.3.1 Examples of Derivation 567 A11.3.2 Derivation of Reflection Coefficients and Power Gain 568 References 571 12 Oscillators 572 12.1 Principle of Oscillation 572 12.1.1 Oscillation Conditions 573 12.1.2 Oscillation Determination 574 12.2 Fundamentals of Oscillator Design 575 12.2.1 Basic Oscillators 576 12.2.2 Feedback Oscillators 579 12.3 Phase Noise 587 12.3.1 Fundamentals of Phase Noise 588 12.3.2 Phase Noise Modeling 593 12.3.3 Low Phase-Noise Design Consideration 599 12.3.4 Effects of Phase Noise on Systems 599 12.3.5 Analysis Example of Effects of Phase Noise 601 12.4 Oscillator Circuits 602 12.4.1 Cross-Coupled Oscillators 602 12.4.2 Distributed Oscillators 612 12.4.3 Push-Push Oscillators 617 References 626 Problems 627 13 Mixers 633 13.1 Fundamentals of Mixers 633 13.1.1 Mixing Principle 633 13.1.2 Mixer Parameters 636 13.2 Mixer Types 641 13.2.1 Single-Ended Mixer 642 13.2.2 Single-Balanced Mixer 642 13.2.3 Double-Balanced Mixer 646 13.2.4 Doubly Double-Balanced Mixer 649 13.3 Other Mixers 650 13.3.1 Passive Mixer 650 13.3.2 Image-Reject Mixer 651 13.3.3 Quadrature Mixer 652 13.3.4 Distributed Mixer 652 13.4 Mixer Analysis and Design 656 13.4.1 Switching Mixer Fundamental 656 13.4.2 Single-Ended Mixer 658 13.4.3 Single-Balanced Mixer 661 13.4.4 Double-Balanced Mixer 663 13.4.5 Source Degeneration in Mixer Design 665 13.5 Sampling Mixer 667 13.5.1 Fundamentals of Sampling 668 13.5.2 Sampling Theory 669 13.5.3 Sampling Process 670 13.5.4 Sample and Hold 673 13.5.5 Sampling Switch 678 13.5.6 Integrated Sampling Mixer 678 References 689 Problems 690 14 Switches 694 14.1 Fundamentals of Switches 694 14.1.1 Switch Operation 694 14.1.2 Important Parameters 695 14.2 Analysis of Switching MOSFET 697 14.2.1 Analysis of Shunt Transistor 697 14.2.2 Analysis of Series Transistor 698 14.2.3 Analysis of Combined Series and Shunt Transistors 699 14.2.4 Selection of MOSFET 699 14.2.5 Design Consideration for Improved Insertion Loss and Isolation 701 14.3 SPST Switches 702 14.3.1 SPST Switch Employing Two Parallel MOSFETs 702 14.3.2 SPST Switch Employing Two Series MOSFETs 703 14.3.3 SPST Switch Employing Two Series and Two Shunt MOSFETs 703 14.3.4 SPST Switch Using Impedance or Admittance Inverters 703 14.4 SPDT Switches 712 14.4.1 SPDT Switch Topologies 712 14.4.2 SPDT Switch Analysis 713 14.5 Ultra-Wideband Switches 714 14.5.1 Ultra-Wideband SPST Switch 715 14.5.2 Ultra-Wideband T/R Switch 721 14.6 Ultra-High-Isolation Switches 727 14.6.1 Ultra-High-Isolation Switch Architecture and Analysis 727 14.6.2 Ultra-High-Isolation SPST Switch Design 733 14.7 Filter Switches 737 References 739 Problems 739 15 RFIC Simulation, Layout, and Test 747 15.1 RFIC Simulation 748 15.1.1 DC Simulation 749 15.1.2 Small-Signal AC Simulation 749 15.1.3 Transient Simulation 749 15.1.4 Periodic Steady State Simulation 749 15.1.5 Harmonic-Balance Simulation 750 15.1.6 Periodic Distortion Analysis 751 15.1.7 Envelope Simulation 751 15.1.8 Periodic Small Signal Analysis 751 15.1.9 EM Simulation 751 15.1.10 Statistical and Mismatch Simulation 754 15.2 RFIC Layout 754 15.2.1 General Layout Issues 754 15.2.2 Passive and Active Component Layout 755 15.3 RFIC Measurement 758 15.3.1 On-Wafer Measurement 759 15.3.2 Off-Chip Measurement 782 References 784 Problems 784 16 Systems 788 16.1 Fundamentals of Systems 788 16.1.1 Friis Transmission Equation 788 16.1.2 System Equation 790 16.1.3 Signal-to-Noise Ratio of System 791 16.1.4 Receiver Sensitivity 793 16.1.5 System Performance Factor 794 16.1.6 Power 796 16.1.7 Angle and Range Resolution 797 16.1.8 Range Accuracy 800 16.2 System Type 801 16.2.1 Pulse System 801 16.2.2 FMCW System 803 16.2.3 Receiver Architectures 808 References 826 Problems 826 Appendix: RFIC Design Example: Mixer 830 A1.1 Circuit Design Specifications and General Design Information 830 A1.2 Mixer Design 830 A1.2.1 Single-Ended to Differential Input Active Balun 832 A1.2.2 Double-Balanced Gilbert Cell 832 A1.2.3 Differential to Single-Ended Output Active Balun 834 A1.2.4 Band-Pass Filter 834 A1.3 Mixer Optimization and Layout 835 A1.4 Simulation Results 836 A1.4.1 Stability 836 A1.4.2 Return Loss 836 A1.4.3 Conversion Gain 836 A1.4.4 Noise Figure 837 A1.4.5 Other Mixer Performance 837 A1.5 Measured Results 838 References 840 Index 841

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Book SynopsisThis new edition of the popular guide to telecommunications circuit design offers the same comprehensive coverage found in the first edition, but now features additional sections on mobile and wireless phones and pagers, compact antennas, switches, power amplifiers, and TDMA and CDMA modulation schemes.Trade Review"...useful as a reference for beginning students...and for self-study..." (IEEE Circuits & Devices Magazine, May 2003)Table of ContentsPreface. Chapter One. The Hstory of Telecommunications. Chapter Two. Amplitude Modulated Radio Transmitter. Chapter Three. The Amplitude-Modulated Radio Receiver. Chapter Four. Frequency Modulated Radio Transmitter. Chapter Five. The Frequency Modulated Radio Receiver. Chapter Six. The Television Transmitter. Chapter Seven. The Television Receiver. Chapter Eight. The Telephone Network. Chapter Nine. Signal Processing in the Telephone System. Chapter Ten. The Facsimile Machine. Chapter Eleven. Personal Wireless Communication System. Chapter Twelve. Telecommunication Transmission Media. Appendix A. The Transformer. Appendix B. Designation of Frequencies. Appendix C. The Electromagnetic Spectrum. Appendix D. The Modified Huffman Data Compression Code. Appendix E. Electronic Memory. Appendix F. Binary Coded Decimal to Seven-Segment Decoder. Index.

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Book Synopsis* Builds on the success of the first Razavi book, covering the most recent developments in phase-locked loop technology* Will include an introductory "tutorial" chapter composed by the editor which will outline and explain in brief the recent advances in PLL design. .Table of ContentsPreface. About the Author. Part I: Original Contributions. Devices and Circuits for Phase-Locked Systems. Delay-Locked Loops - An Overview. Delta-Sigma Fractional-N Phase-Locked Loops. Design Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems. Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers. Part II: Devices. Physics-Based Closed-Form Inductance Expression for Compact Modeling of Integrated Spiral Inductors. The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC's. Analysis, Design, and Optimization of Spiral Inductors and Transformers for Si RF IC's. Stacked Inductors and Transformers in CMOS Technology. Estimation Methods for Quality Factors of Inductors Fabricated in Silicon Integrated Circuit Process Technologies. A Q-Factor Enhancement Technique for MMIC Inductors. On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's. The Effects of a Ground Shield on the Characteristics and Performance of Spiral Inductors. Temperature Dependence of Q and Inductance in Spiral Inductors Fabricated in a Silicon-Germanium/BiCMOS Technology. Substrate Noise Coupling Through Planar Spiral Inductor. Design of High-Q Varactors for Low-Power Wireless Applications Using a Standard CMOS Process. On the Use of MOS Varactors in RF VCO's. Part III: Phase Noise and Jitter. Low-Noise Voltage-Controlled Oscillators Using Enhanced LC-Tanks. A Study of Phase Noise in CMOS Oscillators. A General Theory of Phase Noise in Electrical Oscillators. Physical Processes of Phase Noise in Differential LC Oscillators. Phase Noise in LC Oscillators. The Effect of Varactor Nonlinearity on the Phase Noise of Completely Integrated VCOs. Jitter in Ring Oscillators. Jitter and Phase Noise in Ring Oscillators. A Study of Oscillator Jitter Due to Supply and Substrate Noise. Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise. On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops. Part IV: Building Blocks. A Low-Noise, Low-Power VCO with Automatic Amplitude Control for Wireless Applications. A Fully Integrated VCO at 2 GHz. Tail Current Noise Suppression in RF CMOS VCOs. Low-Power Low-Phase-Noise Differentially Tuned Quadrature VCO Design in Standard CMOS. Analysis and Design of an Optimally Coupled 5-GHz Quadrature LC Oscillator. A 1.57-GHz Fully Integrated Very Low-Phase-Noise Quadrature VCO. A Low-Phase-Noise 5GHz Quadrature CMOS VCO Using Common-Mode Inductive Coupling. An Integrated 10/5GHz Injection-Locked Quadrature LC VCO in a 0.18[mu]m Digital CMOS Process. Rotary Traveling-Wave Oscillator Arrays: A New Clock Technology. 35-GHz Static and 48-GHz Dynamic Frequency Divider IC's Using 0.2-[mu]m AlGaAs/GaAs-HEMT's. Superharmonic Injection-Locked Frequency Dividers. A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-[mu]m CMOS Technology. A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-[mu]m CMOS. A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops. High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler. A 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC). A Simple Precharged CMOS Phase Frequency Detector. Part V: Clock Generation by PLLs and DLLs. A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation. A Low Jitter 0.3-165 MHz CMOS PLL Frequency Synthesizer for 3 V/5 V Operation. Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques. A Low-Jitter PLL Clock Generator for Microprocessors with Lock Range of 340-612 MHz. A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL. Active GHz Clock Network Using Distributed PLLs. A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control. A Low-Jitter 125-1250-MHz Process-Independent and Ripple-Poleless 0.18-[mu]m CMOS PLL Based on a Sample-Reset Loop Filter. A Dual-Loop Delay-Locked Loop Using Multiple Voltage-Controlled Delay Lines. An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance. A Semidigital Dual Delay-Locked Loop. A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle. A Portable Digital DLL for High-Speed CMOS Interface Circuits. CMOS DLL-Base 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator. A 1.5V 86 mW/ch 8-Channel 622-3125-Mb/s/ch CMOS SerDes Macrocell with Selectable Mux/Demux Ratio. A Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM. A Low-Jitter Wide-Range Skew-Calibrated Dual-Loop DLL Using Antifuse Circuitry for High-Speed DRAM. Part VI: RF Synthesis. An Adaptive PLL Tuning System Architecture Combining High Spectral Purity and Fast Settling Time. A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Receivers. A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver. A 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4-[mu]m CMOS Technology. Fast Switching Frequency Synthesizer with a Discriminator-Aided Phase Detector. Low-Power Dividerless Frequency Synthesis Using Aperture Phase Detection. A Stabilization Technique for Phase-Locked Frequency Synthesizers. A Modeling Approach for [Sigma]-[Delta] Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis. A Fully Integrated CMOS Frequency Synthesizer with Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS- and Cellular-CDMA Wireless Systems. A 1.1-GHz CMOS Fraction-N Frequency Synthesizer With a 3-b Third-Order [Sigma]-[Delta] Modulator. A 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching. A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation. A CMOS Monolothic [Sigma][Delta]-Controlled Fractional-N Frequency Synthesizer for DSC-1800. Part VII: Clock and Data Recovery. A 2.5-Gb/s Clock and Data Recovery IC with Tunable Jitter Characteristics for Use in LAN's and WAN's. Clock/Data Recovery PLL Using Half-Frequency Clock. A 0.5-[mu]m CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling. A 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability. SiGe Clock and Data Recovery IC with Linear-Type PLL for 10-Gb/s SONET Application. A Fully Integrated SiGe Receiver IC for 10-Gb/s Data Rate. A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector. A 10-Gb/s CMOS Clock and Data Recovery Circuit with Frequency Detection. A 10-Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18[mu]m CMOS. A 40-Gb/s Integrated Clock and Data Recovery Circuit in a 50-GHz f[subscript T] Silicon Bipolar Technology. A Fully Integrated 40-Gb/s Clock and Data Recovery IC With 1:4 DEMUX in SiGe Technology. Clock and Data Recovery IC for 40-Gb/s Fiber-Optic Receiver. Index.

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Book Synopsis* Examines the various methods available for circuit protection, including coverage of the newly developed ESD circuit protection schemes for VLSI circuits. * Provides guidance on the implementation of circuit protection measures. * Includes new sections on ESD design rules, layout approaches, package effects, and circuit concepts. * Reviews the new Charged Device Model (CDM) test method and evaluates design requirements necessary for circuit protection.Table of ContentsPreface 1. Introduction Background The ESD Problem Protecting against ESD Outline of the Book 2. ESD Phenomenon Introduction Electrostatic Voltage Discharge ESD Stress Models 3. Test Methods Introduction Human Body Model (HBM) Machine Model (MM) Charged Device Model (CDM) Socket Device Model (SDM) Metrology, Calibration, Verification Transmission Line Pulsing (TLP) Failure Criteria Summary 4 Physics and Operation of ESD Protection Circuits Introduction Resistors Diodes Transistor Operation Transistor Operation Under ESD Conditions Electrothermal Effects SCR Operation Conclusion 5 ESD Protection Design Concepts and Strategy The Qualities of Good ESD Protection ESD Protection Design Methods Selecting an ESD Strategy Summary 6 Design and Layout Requirements Introduction Thick Field Device NMOS Transistors (FPDs) Gate-Coupled NMOS (GCNMOS) Gate Driven nMOS (GDNMOS) SCR Protection Device ESD Protection Design Synthesis Total Input Protection ESD Protection Using Diode-Based Devices Power Supply Clamps BiPolar and BiCMOS Protection Circuits Summary 7 Advanced Protection Design Introduction PNP Driven NMOS (PDNMOS) Substrate Triggered NMOS (STNMOS) NMOS Triggered NMOS (NTNMOS) ESD for Mixed Voltage I/O CDM Protection SOI Technology High Voltage Transistors BiCMOS Protection RF Designs General I/O Protection Schemes Design/layout Errors Summary 8 Failure Modes, Reliability Issues, and Case Studies Introduction Failure Mode Analysis Reliability and Performance Considerations Advanced CMOS Input Protection Optimizing the Input Protection Scheme Designs for Special Applications Process Effects on Input Protection Design Total IC Chip Protection Power Bus Protection Internal Chip ESD Damage Stress Dependent ESD Behavior Failure Mode Case Studies Summary 9 Influence of Processing on ESD Introduction High Current Behavior Cross-section of a MOS Transistor Drain-Source Implant Effects P-Well Effects N-Well Effects Epitaxial Layers and Substrates Gate Oxides Silicides Contacts Interconnect and Metallization Gate Length Dependencies Silicon-On-Insulator (SOI) Bipolar Transistors Diodes Resistors Reliability Trade-Offs Summary 10 Device Modeling of High Current Effects Introduction The Physics of ESD Damage Thermal ("Second") Breakdown Analytical Models Using the Heat Equation Electrothermal Device Simulations Conclusions Circuit Simulation Basics, Approaches, and Simulations Introduction Modeling the MOSFET Modeling Bipolar Junction Transistors Modeling Diffusion Resistors Modeling Protection Diodes Simulation of Protection Circuits Electrothermal Circuit Simulations Conclusion 12 Conclusions Long-term Relevance of ESD in ICs State-of-the-art for ESD Protection Current Limitations Future Issues

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Book SynopsisFocuses on the basic operating principles and the techniques used to incorporate the devices into circuit applications. Part one reviews fundamental principles in transmission lines and circuits as well as semiconductor physics. Two-terminal solid-state devices, circuits and applications are covered in the second section. Part three discusses three-terminal solid-state devices, circuits and applications. Introduces noise figures and system parameters for receiver design. Includes numerous examples and problems.Table of ContentsTransmission Lines and Waveguides. S Parameters and Circuit Representations. Review of Semiconductor Physics. Varactor Devices and Circuits. Detector and Mixed Devices and Circuits. Receiver Noise Figure and Dynamic Range. p-i-n Diodes and Control Devices. Oscillator and Amplifier Circuits Using Two-Terminal Devices. Transferred Electron Devices and Circuits. IMPATT Devices and Circuits. Field-Effect Transistors. Bipolar Transistors, HEMTs, and HBTs. Transistor Amplifiers. Transistor Oscillators. Transistor Mixers, Switches, Phase Shifters, and Multipliers. Appendices.

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Book SynopsisThis advanced text studies the special interactions that occur between circuits and devices, which lead to an understanding of the design and performance characteristics of solid-state microwave amplifiers and oscillators.Table of ContentsMICROWAVE CIRCUITS. Review of Transmission Lines, Waveguides, and Smith ChartAnalysis. Linear Microwave Network Parameters. Waveguide and Transmission Line Parameters. Transmission Lines as Resonators and Circuit Elements. Microwave Networks and Components. MICROWAVE SOLID-STATE DEVICES. Solid-State Theory: Special Topics. Schottky Barrier Diodes. Microwave Transistors. IMPATT Diodes. Gunn Diodes. DEVICE-CIRCUIT INTERACTION. Transistor Amplifier Properties. Two-Terminal Negative-Resistance Amplifiers. Oscillators. Noise. Appendix. Index.

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Book SynopsisTimely, authoritative, application-oriented. an in-depthexploration of current and future uses of FPGAs in digital systemsThe development of field-programmable gate arrays (FPGAs) may wellbe the most important breakthrough for the microelectronicsindustry since the invention of the microprocessor. Using FPGAs, asystem designer working on a PC can now develop a working prototypein a few hours and change it at will in just a few minutes, ratherthan waiting weeks or months for a printed-circuit assembly or acustom integrated circuit to be built. This newfound ability tochange a system by simply altering its configuration memory is alsoleading to exciting new forms of computing, such as arrayapplications that exploit parallelism. Now in a book that functionsequally well as a working professional reference and apedagogically consistent computer engineering text, John V.Oldfield and Richard C. Dorf: * Provide a detailed overview of FPGAs in digital systemsdesign * Explain the underlyTable of ContentsSystem Implementation Strategies. Review of Logic Design and Electrical Aspects. Introduction to FPGA Architecture. Design Process Flows and Software Tools. Case Studies. Computational Applications. Business Development. Recent Developments. Afterword. Glossary. Index.

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Book SynopsisApplications oriented, it contains all the pertinent and comprehensive information necessary to meet the growing demands placed upon solid-state power conversion equipment. These demands include improved reliability, increased efficiency, higher packing density, improved performance plus meeting safety and EMC regulations. Features a thorough assessment of basic electrical and magnetic aspects of power conversion as well as thermal, protection, radiation and reliability considerations. Stresses semiconductor and magnetic components and gives an analysis of diverse topologies.Table of ContentsTransient Analysis, Circuit Analysis, and Waveforms. Semiconductors, Resistors, and Capacitors. Transformers, Inductors, and Conductors. Rectifiers and Filters. Phase Control Circuits. Transistor Inverters. Thyristor Inverters. Switching Regulators. dc-dc Converters. Resonant Mode Converters. Modulator and Control Analysis. Pulse-Forming Networks and Modulators. Protection and Safety. Electromagnetic Compatibility and Grounding. Semiconductor and Equipment Cooling. Reliability and Quality. Regulated Power Supplies. Uninterruptible Power Systems. Power Factor Correction. Glossary. Index.

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Book SynopsisDevices enormously smaller than before will remodel engineering,chemistry, medicine, and computer technology. How can we understandmachines that are so small? Nanosystems covers it all: powerand strength, friction and wear, thermal noise and quantumuncertainty. This is the book for starting the next century ofengineering. - Marvin Minsky MIT Science magazine calls Eric Drexler Mr. Nanotechnology.For years, Drexler has stirred controversy by declaring thatmolecular nanotechnology will bring a sweeping technologicalrevolution - delivering tremendous advances in miniaturization,materials, computers, and manufacturing of all kinds. Now, he''swritten a detailed, top-to-bottom analysis of molecular machinery -how to design it, how to analyze it, and how to build it.Nanosystems is the first scientifically detailed description ofdevelopments that will revolutionize most of the industrialprocesses and products currently in use. This groundbreaking work draws on physics and cheTable of ContentsPHYSICAL PRINCIPLES. Classical Magnitudes and Scaling Laws. Potential Energy Surfaces. Molecular Dynamics. Positional Uncertainty. Transitions, Errors, and Damage. Energy Dissipation. Mechanosynthesis. COMPONENTS AND SYSTEMS. Nanoscale Structural Components. Mobile Interfaces and Moving Parts. Intermediate Subsystems. Nanomechanical Computational Systems. Molecular Sorting, Processing, and Assembly. Molecular Manufacturing Systems. IMPLEMENTATION STRATEGIES. Macromolecular Engineering. Paths to Molecular Manufacturing. Appendices. Afterword. Symbols, Units, and Constants. Glossary. References. Index.

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Book SynopsisCircuit designers, packaging engineers, printed board fabricators, and procurement personnel will find this book''s microelectronic package design-for-reliability guidelines and approaches essential for achieving their life-cycle, cost-effectiveness, and on-time delivery goals. Its uniquely organized, time-phased approach to design, development, qualification, manufacture, and in-service management shows you step-by-step how to: * Define realistic system requirements in terms of mission profile, operating life, performance expectations, size, weight, and cost * Define the system usage environment so that all operating, shipping, and storage conditions, including electrical, thermal, radiation, and mechanical loads, are assessed using realistic data * Identify potential failure modes, sites, mechanisms, and architecture-stress interactions--PLUS appropriate measures you can take to reduce, eliminate, or accommodate expected failures * CharacterizTable of ContentsDesign for Reliability Concepts. Starting the Design Process. Substrates. Wire and Wirebonds. Tape Automated Bonding. Flip-Chip Bonding. Attachment. Case. Leads. Lead Seals. Lid Seal and Lid. Index.

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Book SynopsisThe first book to combine all of the various topics relevant to low--cost automation. Practical approach covers methods immediately applicable to industrial problems, showing how to select the most appropriate control method for a given application, then design the necessary circuit.Table of ContentsMotion Actuators. Sensors. Introduction to Switching Theory. Industrial Switching Elements. Electric Ladder Diagrams. Sequential Systems with Random Inputs. Pneumatic Control Circuits. Miscellaneous Switching Elements and Systems. Semiflexible Automation: Hardware Programmers. Flexible Automation: Programmable Controllers. Flexible Automation: Microcomputers. Introduction to Assembly Automation. Robotics and Numerical Control. Appendices. Index.

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Book SynopsisA new and innovative paradigm for RF frequency synthesis and wireless transmitter design Learn the techniques for designing and implementing an all-digital RF frequency synthesizer. In contrast to traditional RF techniques, this innovative book sets forth digitally intensive design techniques that lead the way to the development of low-cost, low-power, and highly integrated circuits for RF functions in deep submicron CMOS processes. Furthermore, the authors demonstrate how the architecture enables readers to integrate an RF front-end with the digital back-end onto a single silicon die using standard ASIC design flow. Taking a bottom-up approach that progressively builds skills and knowledge, the book begins with an introduction to basic concepts of frequency synthesis and then guides the reader through an all-digital RF frequency synthesizer design: Chapter 2 presents a digitally controlled oscillator (DCO), which is the foundation of a novel architectureTable of ContentsPREFACE xiii 1 INTRODUCTION 1 1.1 Frequency Synthesis 1 1.1.1 Noise in Oscillators 2 1.1.2 Frequency Synthesis Techniques 5 1.2 Frequency Synthesizer as an Integral Part of an RF Transceiver 9 1.2.1 Transmitter 10 1.2.2 Receiver 11 1.2.3 Toward Direct Transmitter Modulation 12 1.3 Frequency Synthesizers for Mobile Communications 16 1.3.1 Integer-N PLL Architecture 17 1.3.2 Fractional-N PLL Architecture 18 1.3.3 Toward an All-Digital PLL Approach 23 1.4 Implementation of an RF Synthesizer 25 1.4.1 CMOS vs. Traditional RF Process Technologies 25 1.4.2 Deep-Submicron CMOS 25 1.4.3 Digitally Intensive Approach 26 1.4.4 System Integration 27 1.4.5 System Integration Challenges for Deep-Submicron CMOS 29 2 DIGITALLY CONTROLLED OSCILLATOR 30 2.1 Varactor in a Deep-Submicron CMOS Process 31 2.2 Fully Digital Control of Oscillating Frequency 33 2.3 LC Tank 35 2.4 Oscillator Core 37 2.5 Open-Loop Narrowband Digital-to-Frequency Conversion 39 2.6 Example Implementation 45 2.7 Time-Domain Mathematical Model of a DCO 47 2.8 Summary 51 3 NORMALIZED DCO 52 3.1 Oscillator Transfer Function and Gain 52 3.2 DCO Gain Estimation 53 3.3 DCO Gain Normalization 54 3.4 Principle of Synchronously Optimal DCO Tuning Word Retiming 55 3.5 Time Dithering of DCO Tuning Input 56 3.5.1 Oscillator Tune Time Dithering Principle 56 3.5.2 Direct Time Dithering of Tuning Input 57 3.5.3 Update Clock Dithering Scheme 59 3.6 Implementation of PVT and Acquisition DCO Bits 60 3.7 Implementation of Tracking DCO Bits 64 3.7.1 High-Speed Dithering of Fractional Varactors 64 3.7.2 Dynamic Element Matching of Varactors 70 3.7.3 DCO Varactor Rearrangement 71 3.8 Time-Domain Model 73 3.9 Summary 74 4 ALL-DIGITAL PHASE-LOCKED LOOP 76 4.1 Phase-Domain Operation 77 4.2 Reference Clock Retiming 79 4.3 Phase Detection 81 4.3.1 Difference Mode of ADPLL Operation 85 4.3.2 Integer-Domain Operation 86 4.4 Modulo Arithmetic of the Reference and Variable Phases 86 4.4.1 Variable-Phase Accumulator (PV Block) 89 4.5 Time-to-Digital Converter 91 4.5.1 Frequency Reference Edge Estimation 93 4.6 Fractional Error Estimator 94 4.6.1 Fractional-Division Ratio Compensation 96 4.6.2 TDC Resolution Effect on Estimated Frequency Resolution 97 4.6.3 Active Removal of Fractional Spurs Through TDC (Optional) 98 4.7 Frequency Reference Retiming by a DCO Clock 100 4.7.1 Sense Amplifier–Based Flip-Flop 102 4.7.2 General Idea of Clock Retiming 103 4.7.3 Implementation 104 4.7.4 Time-Deferred Calculation of the Variable Phase (Optional) 107 4.8 Loop Gain Factor 109 4.8.1 Phase-Error Dynamic Range 111 4.9 Phase-Domain ADPLL Architecture 112 4.9.1 Close-in Spurs Due to Injection Pulling 114 4.10 PLL Frequency Response 115 4.10.1 Conversion Between the s- and z-Domains 119 4.11 Noise and Error Sources 119 4.11.1 TDC Resolution Effect on Phase Noise 120 4.11.2 Phase Noise Due to DCO SD Dithering 122 4.12 Type II ADPLL 127 4.12.1 PLL Frequency Response of a Type II Loop 130 4.13 Higher-Order ADPLL 133 4.13.1 PLL Stability Analysis 136 4.14 Nonlinear Differential Term of an ADPLL 139 4.14.1 Quality Monitoring of an RF Clock 140 4.15 DCO Gain Estimation Using a PLL 141 4.16 Gear Shifting of PLL Gain 142 4.16.1 Autonomous Gear-Shifting Mechanism 143 4.16.2 Extended Gear-Shifting Scheme with Zero-Phase Restart 148 4.17 Edge Skipping Dithering Scheme (Optional) 154 4.18 Summary 155 5 APPLICATION: ADPLL-BASED TRANSMITTER 156 5.1 Direct Frequency Modulation of a DCO 157 5.1.1 Discrete-Time Frequency Modulation 158 5.1.2 Hybrid of Predictive/Closed PLL Operation 158 5.1.3 Effect of FREF/CKR Clock Misalignment 163 5.2 Just-in-Time DCO Gain Calculation 164 5.3 GFSK Pulse Shaping of Transmitter Data 167 5.3.1 Interpolative Filter Operation 172 5.4 Power Amplifier 175 5.5 Digital Amplitude Modulation 177 5.5.1 Discrete Pulse-Slimming Control 180 5.5.2 Regulation of Transmitting Power 181 5.5.3 Tuning Word Adjustment 182 5.5.4 Fully Digital Amplitude Control 183 5.6 Going Forward: Polar Transmitter 183 5.6.1 Generic Modulator 186 5.6.2 Polar TX Realization 187 5.7 Summary 188 6 BEHAVIORAL MODELING AND SIMULATION 189 6.1 Simulation Methodology 190 6.2 Digital Blocks 191 6.3 Support of Digital Stream Processing 192 6.4 Random Number Generator 192 6.5 Time-Domain Modeling of DCO Phase Noise 192 6.5.1 Modeling Oscillator Jitter 192 6.5.2 Modeling Oscillator Wander 194 6.5.3 Modeling Oscillator Flicker (1/f ) Noise 195 6.5.4 Clock Edge Divider Effects 200 6.5.5 VHDL Model Realization of a DCO 201 6.5.6 Support of Physical KDCO 202 6.6 Modeling Metastability in Flip-Flops 203 6.7 Simulation Results 206 6.7.1 Time-Domain Simulations 206 6.7.2 Frequency-Deviation Simulations 207 6.7.3 Phase-Domain Simulations of Transmitters 209 6.7.4 Synthesizer Phase-Noise Simulations 209 6.8 Summary 212 7 IMPLEMENTATION AND EXPERIMENTAL RESULTS 213 7.1 DSP and Its RF Interface to DRP 213 7.2 Transmitter Core Implementation 214 7.3 IC Chip 216 7.4 Evaluation Board 218 7.5 Measurement Equipment 218 7.6 GFSK Transmitter Performance 219 7.7 Synthesizer Performance 221 7.8 Synthesizer Switching Transients 224 7.9 DSP-Driven Modulation 225 7.10 Performance Summary 226 7.11 Summary 227 APPENDIX A: SPURS DUE TO DCO SWITCHING 228 A.1 Spurs Due to DCO Modulation 229 APPENDIX B: GAUSSIAN PULSE-SHAPING FILTER 232 APPENDIX C: VHDL SOURCE CODE 237 C.1 DCO Level 2 237 C.2 Period-Controlled Oscillator 239 C.3 Tactical Flip-Flop 241 C.4 TDC Pseudo-Thermometer Output Decoder 243 REFERENCES 247 INDEX 253

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Book SynopsisFrom the electronic nose and the intelligent ear to the modern ink jet nozzle, the applications of smart devices incorporating microsensors are increasing rapidly. Microsensors are miniature devices that convert a non--electrical quantity into an electrical signal. By integrating a microsensor with a microprocessor, a smart sensor is produced.Table of ContentsIntroduction Electronic Materials and Processing MEMS Materials and their Preparation Standard Microelectronic Technologies Silicon Micromachining:Bulk Silicon Micromachining: Surface Microstereolithography for MEMS Microsensors Introduction to SAW Devices Surface Acoustic Waves in Solids IDT Microsensor Parameter Measurement IDT Microsensor Fabrication IDT Microsensors MEMS-IDT Microsensors Smart Sensors and MEMS Appendices Index

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Book SynopsisMicrowave devices, circuits and subsystems are used in modern microwave communication systems. These include fixed and mobile microwave communications services as well as terrestrial cellular applications. Volume 1 in this two-volume series provides an up-to-date and comprehensive reference to these communications.Trade Review"…this book is a good reference for [the] microwave engineering community." (IEEE Circuits & Devices Magazine, November/December 2006)Table of ContentsList of contributors. Preface. 1. Overview of the Book (I.A. Glover, S.R. Pennock and P.R. Shepherd). 1.1 Introduction. 1.2 RF Devices. 1.3 Signal Transmission and Network Methods. 1.4 Amplifiers. 1.5 Mixers. 1.6 Filters. 1.7 Oscillators and Frequency Synthesisers. 2. RF Devices: Characteristics and Modelling (A. Suarez and T. Fernandez). 2.1 Introduction 2.2 Semiconductor Properties 2.3 P-N Junction. 2.4 The Schottky Diode. 2.5 PIN Diodes. 2.6 Step-Recovery Diodes. 2.7 Gunn Diodes. 2.8 IMPATT Diodes. 2.9 Transistors. References. 3. Signal Transmission, Network Methods and Impedance Matching (N.J. McEwan, T.C. Edwards, D. Dernikas and I.A. Glover). 3.1 Introduction. 3.2 Transmission Lines: General Considerations. 3.3 The Two-Conductor Transmission Line: Revision of Distributed Circuit Theory. 3.4 Loss, Dispersion, Phase and Group Velocity. 3.5 Field Theory Method for Ideal TEM Case. 3.6 Microstrip. 3.7 Coupled Microstrip Lines. 3.8 Network Methods. 3.9 Impedance Matching. 3.10 Network Analysers. 3.11 Summary. References. 4. Amplifier Design (N.J. McEwan and D. Dernikas). 4.1 Introduction. 4.2 Amplifier Gain Definitions. 4.3 Stability. 4.4. Broadband Amplifier Design. 4.5 Low Noise Amplifier Design. 4.6 Practical Circuit Considerations. 4.7 Computer-Aided Design (CAD). References. 5. Mixers: Theory and Design (A. Tazon and L. de la Fuente). 5.1 Introduction. 5.2 General Properties. 5.3 Devices for Mixers. 5.4 Non-Linear Analysis. 5.5 Diode Mixer Theory. 5.6 FET Mixers. 5.7 IF Amplifier. 5.8 Single-Balanced FET Mixers. 5.9 Double-Balanced FET Mixers. 5.10 Harmonic Mixers. 5.11 Monolithic Mixers. References. 6. Filters (A Mediavilla). 6.1 Introduction. 6.2 Filter Fundamentals. 6.3 Mathematical Filter Responses. 6.4 Low Pass Prototype Filter Design. 6.5 Filter Impedance and Frequency Scaling. 6.6 Elliptic Filter Transformation. 6.7 Filter Normalisation. 7. Oscillators, Frequency Synthesisers and PLL Techniques (E. Artal, J.P. Pascal and J. Portilla). 7.1 Introduction. 7.2 Solid State Microwave Oscillators. 7.3 Negative Resistance Diode Oscillators. 7.4 Transistor Oscillators. 7.5 Voltage-Controlled Oscillators. 7.6 Oscillator Characterisation and Testing, 7.7 Microwave Phase Locked Oscillators. 7.8 Subsystems for Microwave Phase Locked Oscillators (PLOs). 7.9 Phase Noise. 7.10 Examples of PLOs. References. Index.

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Book SynopsisThe VHDL Reference: The essential guide for students and professionals working in computer hardware design and synthesis. The definitive guide to VHDL, this book combines a comprehensive reference of the VHDL syntax with tutorial and workshop materials that guide the reader through the principles of digital hardware design.Trade Review"...combines a comprehensive reference of the VHDL syntax with tutorial and workshop materials that guide readers through the principles f digital hardware design." (SciTech Book News, Vol. 26, No. 2, June 2002)Table of ContentsVHDL TUTORIAL. VHDL: Overview and Application Field. VHDL Language and Syntax. Synthesis. Simulation. Project Management. VHDL-AMS TUTORIAL. VHDL-AMS. VHDL WORKSHOP. VHDL Working Environment. Exercises. REFERENCE. Design Entities and Configurations. Subprograms and Packages. Types. Declarations. Specification. Names. Expressions. Sequential Statements. Concurrent Statements. Miscellaneous. Elaboration and Simulation. Lexical Elements. Predefined Attributes. Package STANDARD. Package TEXTIO. BNF. Literature. Index.

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Book SynopsisProvides the reader with memory fundamentals as well as directions for future research. Examines memory history, current memory technology and offers a glimpse at the future of memories.Table of ContentsThe Strategic Nature of Semiconductor Memories. The Basics of Memories: Market, Technology and Product. Trends in Memory Applications. Memory Device and Process Technology. Basic Memory Architecture and Cell Structure. Dynamic Random Access Memory Trends--4k to 256Mb. Application-Specific DRAMs. Trends in Static RAMs. Future, Fast and Application-Specific SRAMs. MOS ROMs, PROMs and EPLDs. Field Alterable ROMs I: EPROM, OTP, and Flash Memories. Field Alterable ROMs 2: EEPROM, EAROM, NV-RAM. Packaging--Single, Module and Wafer Scale Integration. Memory Electrical and Reliability Testing. Yield, Cost and the Modern Factory. Memory Trends in the Future. Index.

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Book SynopsisBroadband networks based on the ATM standard are gaining global popularity for their flexibility in providing integrated transmission of sound, image and data signals. Research into ATM networks is spreading quickly from academic prototyping, to commercial applications by manufacturers and service providers.Table of ContentsBroadband Integrated Services Digital Network. Interconnection Networks. Rearrangeable Networks. Non-Blocking Networks. ATM Switch Model. ATM Switching with Minimum-Depth Blocking Networks. ATM Switching with Non-Blocking Single-Queueing Networks. ATM Switching with Non-Blocking Multiple-Queueing Networks. ATM Switching with Arbitrary-Depth Blocking Networks. Appendix. Index.

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Book SynopsisReuse in Electronic Design From Information Modelling to Intellectual Properties Peter Conradi Berlin, Germany Reuse of existing IC intellectual property blocks is currently the hot topic in electronic design automation. By cutting development time and improving designer productivity, reuse offers a faster time to market and consequently increased profitability. Conradi encompasses the fundamentals of physical system modelling, design methodologies and basic design architectures plus reuse strategies and tasks. Features include: * Graph-oriented visualisations enabling the reader to understand the requirements of future interdisciplinary design tools * Guidance on information modelling languages, system classification and decomposition of systems under development * Section on reuse strategies and tasks examining the practical aspects of the technique for both analogue and digital design * Data management and retrieval methods including the algebra of the selection procTable of ContentsPhysical System Modelling Basics. Design Methodologies and Basic Design Architectures. Reuse Strategies and Tasks. Conclusion. Appendices. Definitions. References. Index.

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Book SynopsisA transistor-level, design-intensive overview of high speed and high frequency monolithic integrated circuits for wireless and broadband systems from 2 GHz to 200 GHz, this comprehensive text covers high-speed, RF, mm-wave and optical fiber circuits using nanoscale CMOS, SiGe BiCMOS and III-V technologies. Step-by-step design methodologies, end-of-chapter problems and practical simulation and design projects are provided, making this an ideal resource for senior undergraduate and graduate courses in circuit design. With an emphasis on device-circuit topology interaction and optimization, it gives circuit designers and students alike an in-depth understanding of device structures and process limitations affecting circuit performance.Trade Review'… the ideal companion for circuit designers wishing to grasp the challenges of circuit design above RF … takes the reader from system specification down to the transistor and presents the circuit analysis that underlies every RF circuit designer's intuition.' James Buckwalter, University of California, San Diego'Both experienced designers and newcomers in the field will appreciate this book … many detailed design recipes and tricks - often with a link to the underlying IC technologies - that are seldom found in related textbooks.' Piet Wambacq, University of Brussels and IMEC'… a unique encyclopaedic 'dictionary' for an in-depth understanding of high-speed and high-frequency microelectronic design. Original, dense of details, clear and focused on the modern design challenges … the first book of a new class with a profound look at the road ahead.' Domenico Zito, University College Cork'Destined to become a classic reference in high frequency RFICs … comprehensive coverage of a vast array of integrated circuits and systems … exceptional tutorial value … presents the state-of-the-art in microwave and millimeter-wave systems-on-chip.' Gabriel M. Rebeiz, University of California, San Diego'… [an] easy-to-read book on the subject of high-frequency circuits … Highly recommended. Graduate students, researchers/faculty, and practicing engineers working with high-frequency applications.' L. McLauchlan, Choice'If I was a professor looking for a text to use in teaching a microwave integrated circuits course, I would pick this book. When I get asked where to go to learn about all this microwave stuff, Voinigescu's book will be on my shortlist …' IEEE Microwave MagazineTable of Contents1. Introduction; 2. High-frequency and high-data-rate communication systems; 3. High-frequency linear noisy network analysis; 4. High-frequency devices; 5. Circuit analysis techniques for high-frequency integrated circuits; 6. Tuned power amplifier design; 7. Low-noise tuned amplifier design; 8. Broadband low-noise and transimpedance amplifiers; 9. Mixers, switches, modulators, and other control circuits; 10. Design of voltage-controlled oscillators; 11. High-speed digital logic; 12. High-speed digital output drivers with waveshape control; 13. SoC examples; Appendix 1. Trigonometric identities; Appendix 2. Baseband binary data formats and analysis; Appendix 3. Linear matrix transformations; Appendix 4. Fourier series; Appendix 5. Exact noise analysis for a cascode amplifier with inductive degeneration; Appendix 6. Noise analysis of the common-emitter amplifier with transformer feedback; Appendix 7. Common-source amplifier with shunt-series transformer feedback; Appendix 8. HiCUM level 0 model for a SiGe HBT; Appendix 9. Technology parameters; Appendix 10. Analytical study of oscillator phase noise; Appendix 11. Physical constants; Appendix 12. Letter frequency bands; Index.

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Book Synopsis

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