Embedded systems Books

Book SynopsisEmbedded Systems: A Contemporary Design Tool, Second Edition Embedded systems are one of the foundational elements of today?s evolving and growing computer technology. From operating our cars, managing our smart phones, cleaning our homes, or cooking our meals, the special computers we call embedded systems are quietly and unobtrusively making our lives easier, safer, and more connected. While working in increasingly challenging environments, embedded systems give us the ability to put increasing amounts of capability into ever-smaller and more powerful devices. Embedded Systems: A Contemporary Design Tool, Second Edition introduces you to the theoretical hardware and software foundations of these systems and expands into the areas of signal integrity, system security, low power, and hardware-software co-design. The text builds upon earlier material to show you how to apply reliable, robust solutions to a wide range of applications operating in today?s ofTable of ContentsAbout the Author xxxiii Foreword xxxv Preface xlix Acknowledgment lix About the Companion Website lxi Part 1 Hardware and Software Infrastructure 1 The Hardware Side – Part 1: An Introduction 1 2 The Hardware Side – Part 2: Combinational Logic – A Practical View 55 3 The Hardware Side – Part 3: Storage Elements and Finite-State Machines – A Practical View 111 4 Memories and the Memory Subsystem 165 5 An Introduction to Software Modeling 215 6 The Software Side – Part 1: The C Program 243 7 The Software Side – Part 2: Pointers and Functions 279 Part 2 Developing the Foundation 8 Safety, Security, Reliability, and Robust Design 331 9 Embedded Systems Design and Development – Hardware– Software Co-Design 403 10 Hardware Test and Debug 507 Part 3 Doing the Work 11 Real-Time Kernels and Operating Systems 541 12 Tasks and Task Management 573 13 Deadlocks 625 14 Performance Analysis and Optimization 645 Part 4 Developing the Foundation 15 Working Outside of the Processor I: A Model of Interprocess Communication 715 16 Working Outside of the Processor I: Refining the Model of Interprocess Communication 733 17 Working Outside of the Processor II: Interfacing to Local Devices 789 18 Working Outside of the Processor III: Interfacing to Remote Devices 837 19 Programmable Logic Devices 869 20 Practical Considerations Signal Behavior in the Real World – Part 1 – Noise and Crosstalk 893 21 Practical Considerations Signal Behavior in the Real World – Part 2 – High-Speed Signaling 909 A Verilog Overview: The Verilog Hardware Description Language 949 Further Reading 981 Index 991

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Book SynopsisThis book, written by Stephanie Moyerman, a research scientist with Intel's Smart Device Innovation Team, teaches you everything you need to know to get started making things with Edison, the compact and powerful Internet of Things platform.

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Book SynopsisThis practical guide shows hardware and software engineers, makers, and web developers how to talk in JavaScript with a variety of hardware platforms. Authors Patrick Mulder and Kelsey Breseman also delve into the basics of microcontrollers, single-board computers, and other hardware components.

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Book SynopsisThis book presents a system-level analysis of inductive wireless power transfer (WPT) links. The basic requirements, design parameters, and utility of key building blocks used in inductive WPT links are presented, followed by detailed theoretical analysis, design, and optimization procedure, while considering practical aspects for various application domains. Readers are provided with fundamental, yet easy to follow guidelines to help them design high-efficiency inductive links, based on a set of application-specific target specifications. The authors discuss a wide variety of recently proposed approaches to achieve the maximum efficiency point, such as the use of additional resonant coils, matching networks, modulation of the load quality factor (Q-modulation), and adjustable DC-DC converters. Additionally, the attainability of the maximum efficiency point together with output voltage regulation is addressed in a closed-loop power control mechanism. Numerous examples, including MATLAB/Octave calculation scripts and LTspice simulation files, are presented throughout the book. This enables readers to check their own results and test variations, facilitating a thorough understanding of the concepts discussed. The book concludes with real examples demonstrating the practical application of topics discussed. Covers both introductory and advanced levels of theory and practice, providing readers with required knowledge and tools to carry on from simple to advanced wireless power transfer concepts and system designs; Provides theoretical foundation throughout the book to address different design aspects; Presents numerous examples throughout the book to complement the analysis and designs; Includes supplementary material (numerical and circuit simulation files) that provide a "hands-on" experience for the reader; Uses real examples to demonstrate the practical application of topics discussed. Table of ContentsIntroduction to Wireless Power Transfer.- Inductive Wireless Power Transfer.- Inductive Link: Practical Aspects.- Back telemetry.- Achieving the Optimum Operating Point (OOP).- Adaptive circuits to track the Optimum Operating Point (OOP).- Closed-loop WPT links.- System Design Examples.

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Book SynopsisThis book provides readers with a valuable guide to understanding security and the interplay of computer science, microfluidics, and biochemistry in a biochip cyberphysical system (CPS). The authors uncover new, potential threat and trust-issues to address, as this emerging technology is poised to be adapted at a large scale. Readers will learn how to secure biochip CPS by leveraging the available resources in different application contexts, as well as how to ensure intellectual property (IP) is protected against theft and counterfeits. This book enables secure biochip CPS design by helping bridge the knowledge gap at the intersection of the multi-disciplinary technology that drives biochip CPS.Table of ContentsIntroduction.- Threat landscape.- Architecture for Security.- Tools for Security.- Watermarking of Bio-IP.- Obfuscation of Bio-IP.- Conclusion.

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Book SynopsisThis book describes the first comprehensive approach to the optimization of interconnect architectures in 3D systems on chips (SoCs), specially addressing the challenges and opportunities arising from heterogeneous integration. Readers learn about the physical implications of using heterogeneous 3D technologies for SoC integration, while also learning to maximize the 3D-technology gains, through a physical-effect-aware architecture design. The book provides a deep theoretical background covering all abstraction-levels needed to research and architect tomorrow’s 3D-integrated circuits, an extensive set of optimization methods (for power, performance, area, and yield), as well as an open-source optimization and simulation framework for fast exploration of novel designs.Table of ContentsPart I Introduction1 Introduction to 3D Technologies 1.1 Motivation for Heterogenous 3D ICs 1.2 3D Technologies 1.3 TSV Capacitances—A Problem Resistant to Scaling 1.4 Conclusion 2 Interconnect Architectures for 3D Technologies 2.1 Interconnect Architectures 2.2 Overview of Interconnect Architectures for 3D ICs 2.3 Three-dimensional Networks on chips 2.4 Conclusion Part II 3D Technology Modeling 3 Power and Performance Formulas 3.1 High-Level Formula for the Power Consumption 3.2 High-Level Formula for the Propagation Delay 3.3 Matrix Formulations 3.4 Evaluation 3.5 Conclusion 4 Capacitance Estimation 4.1 Existing Capacitance Models 4.2 Edge and MOS Effects on the TSV Capacitances 4.3 TSV Capacitance Model 4.4 Evaluation 4.5 Conclusion Part III System Modeling xiii xiv Contents 5 Application and Simulation Models 5.1 Overview of the Modeling Approach 5.2 Application Traffic Model 5.3 Simulation Model of 3D NoCs 5.4 Simulator Interfaces 5.5 Conclusion 6 Bit-level Statistics 6.1 Existing Approaches to Estimate the Bit-Level Statistics for Single Data Streams 6.2 Data-Stream Multiplexing 6.3 Bit-Level Statistics with Data-Stream Multiplexing 6.4 Evaluation 6.5 Conclusion 7 Ratatoskr Framework 7.1 Ratatoskr for Practitioners 7.2 Implementation 7.3 Evaluation 7.4 Case Study: Link Power Estimation and Optimization 7.5 Conclusion Part IV 3D-Interconnect Optimization 8 Low-Power Technique for 3D Interconnects 8.1 Fundamental Idea 8.2 Power-Optimal TSV assignment 8.3 Systematic Net-to-TSV Assignments 8.4 Combination with Traditional Low-Power Codes 8.5 Evaluation 8.6 Conclusion 9 Low-Power Technique for High-Performance 3D Interconnects. 9.1 Edge-Effect-Aware Crosstalk Classification 9.2 Existing Approaches and Their Limitations 9.3 Proposed Technique 9.4 Extension to a Low-Power 3D CAC 9.5 Evaluation 9.6 Conclusion 10 Low-Power Technique for High-Performance 3D Interconnects (Misaligned) 10.1 Temporal-Misalignment Effect on the Crosstalk 10.2 Exploiting Misalignment to Improve the Performance 10.3 Effect on the TSV Power Consumption Contents xv 10.4 Evaluation 10.5 Conclusion 11 Low-Power Technique for Yield-Enhanced 3D Interconnects 11.1 Existing TSV Yield-Enhancement Techniques 11.2 Preliminaries—Logical Impact of TSV Faults 11.3 Fundamental Idea 11.4 Formal Problem Description 11.5 TSV Redundancy Schemes 11.6 Evaluation 11.7 Case Study 11.8 Conclusion Part V NoC Optimization for Heterogeneous 3D Integration 12 Heterogeneous Buffering for 3D NoCs251 12.1 Buffer Distributions and Depths 12.2 Routers with Optimized Buffer Distribution 12.3 Routers with Optimized Buffer Depths 12.4 Evaluation 12.5 Discussion 12.6 Conclusion 13 Heterogeneous Routing for 3D NoCs 13.1 Heterogeneity and Routing 13.2 Modeling Heterogeneous Technologies 13.3 Modeling Communication 13.4 Routing Limitations from Heterogeneity 13.5 Heterogeneous Routing Algorithms 13.6 Heterogeneous Router Architectures 13.7 Low-Power Routing in Heterogeneous 3D ICs 13.8 Evaluation 13.9 Discussion 13.10Conclusion 14 Heterogeneous Virtualisation for 3D NoCs 14.1 Problem Description 14.2 Heterogeneous Microarchitectures Exploiting Traffic Imbalance 14.3 Evaluation 14.4 Conclusion 15 Network Synthesis and SoC Floor Planning 15.1 Fundamental Idea 15.2 Modelling and Optimization 15.3 Mixed-Integer Linear Program 15.4 Heuristic Solution xvi Contents 15.5 Evaluation 15.6 Conclusion Part VI Finale 16 Conclusion 16.1 Putting it all together 16.2 Impact on Future Work A Appendix B Pseudo Codes C Method to Calculate the Depletion-Region Widths D Modeling Logical OR Relations

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Book SynopsisThis book explains and focuses on analysis of electric circuits using an up-to-date software package. The book is filled with examples that students will see throughout a standard electric circuit course. This book is a good source to accompany and complete theoretical work of professors. The author provides a single-source for anyone who needs to analyse an electric circuit.Table of ContentsIntroduction.- Basic Concepts.- Three Phase Circuits and Magnetic Coupling.- Frequency Response and DC Sweep Analysis.- Exercises.- References for Further Study.

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Book Synopsis​This book serves as a single-source reference to key machine learning (ML) applications and methods in digital and analog design and verification. Experts from academia and industry cover a wide range of the latest research on ML applications in electronic design automation (EDA), including analysis and optimization of digital design, analysis and optimization of analog design, as well as functional verification, FPGA and system level designs, design for manufacturing (DFM), and design space exploration. The authors also cover key ML methods such as classical ML, deep learning models such as convolutional neural networks (CNNs), graph neural networks (GNNs), generative adversarial networks (GANs) and optimization methods such as reinforcement learning (RL) and Bayesian optimization (BO). All of these topics are valuable to chip designers and EDA developers and researchers working in digital and analog designs and verification. Table of Contents1. Introduction2. Analysis of Digital Design: Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning3. RouteNet: Routability Prediction for Mixed-size Designs Using Convolutional Neural Network4. High Performance Graph Convolutional networks with Applications in Testability Analysis5. MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification6. GRANNITE: Graph Neural Network Inference for Transferable Power Estimation7. Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation at Advanced Process Nodes8. Optimization of Digital Design: Chip Placement with Deep Reinforcement learning9. DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement10. TreeNet: Deep Point Cloud Embedding for Routing Tree Construction11. Asynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing12. Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes13. PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning14. GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization15. Analysis and Optimization of Analog Design: Machine Learning Techniques in Analog Layout Automation16. Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks17. ParaGraph: Layout parasitics and device parameter prediction using graph neural network18. GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learn19. Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization20. Logic and Physical Verification: Deep Predictive Coverage Collection/ Dynamically Optimized Test Generation Using Machine Learning21. Novelty-Driven Verification: Using Machine Learning to Identify Novel Stimuli and Close Coverage22. Using Machine Learning Clustering To Find Large Coverage Holes.- GAN-OPC: Mask optimization with lithography-guided generative adversarial nets.- Layout hotspot detection with feature tensor generation and deep biased learning.

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Book SynopsisThis book addresses the challenges associated with efficient Mixed-Criticality (MC) system design. We focus on application analysis through execution time analysis and task scheduling analysis in order to execute more low-criticality tasks in the system, i.e., improving the Quality-of-Service (QoS), while guaranteeing the correct execution of high-criticality tasks. Further, this book addresses the challenge of enhancing QoS using parallelism in multi-processor hardware platforms. Table of ContentsIntroduction.- Preliminaries and Literature Reviews.- Bounding Time in Mixed-Criticality Systems.- Safety- and Task-Drop-Aware Mixed-Criticality Task Scheduling.- Learning-Based Drop-Aware Mixed-Criticality Task Scheduling.- Fault-Tolerance and Power-Aware Multi-Core Mixed-Criticality System Design.- QoS- and Power-Aware Run-Time Scheduler for Multi-Core Mixed-Criticality Systems.- Conclusion.

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Book SynopsisThe Operational Amplifier.- Magnetically Couples Circuits.- Two-Port Networks.- State Space Model of Electrical Circuits.- The Laplace Transform.

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Book SynopsisIntroduction.- Basics and Related Work.- Models.- Single-Path Attack Graph Algorithm.- Multi-Path Attack Graph Algorithm.- Conclusion.- References

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Book SynopsisThis book discusses the latest developments and outlines future trends in the fields of microelectronics, electromagnetics and telecommunication. It contains original research works presented at the International Conference on Microelectronics, Electromagnetics and Telecommunication (ICMEET 2021), held in Bhubaneswar, Odisha, India during 27–28 August, 2021. The papers were written by scientists, research scholars and practitioners from leading universities, engineering colleges and R&D institutes from all over the world and share the latest breakthroughs in and promising solutions to the most important issues facing today’s society.Table of ContentsAnalysis of Throughput & Spectral Efficiency of the CR Users with Channel Allocation.- On Performance Improvement of Wireless Push Systems Via Smart Antennas.- Hybridization of RF Switch and Related Aspects.- Estimation of Gender using Convolutional Neural Network.- Human Abnormal Activity Detection in the ATM Surveillance Video.- Moving object Detection using Optical Flow and HSV.- Propagation of Data Using Free Space Under Different Weather Conditions.- BEP Analysis of Filter Bank Multicarrier UnderIQ Imbalance.- Optical Character Recognition for Roman-Text .- Visual Words based Static Indian Sign Language Alphabet Recognition using KAZE Descriptors.

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Book SynopsisThis book presents high-quality research papers presented at 3rd International Conference on Sustainable and Innovative Solutions for Current Challenges in Engineering and Technology (ICSISCET 2021) held at Madhav Institute of Technology & Science (MITS), Gwalior, India, from November 13–14, 2021. The book extensively covers recent research in artificial intelligence (AI) that knits together nature-inspired algorithms, evolutionary computing, fuzzy systems, computational intelligence, machine learning, deep learning, etc., which is very useful while dealing with real problems due to their model-free structure, learning ability, and flexible approach. These techniques mimic human thinking and decision-making abilities to produce systems that are intelligent, efficient, cost-effective, and fast. The book provides a friendly and informative treatment of the topics which makes this book an ideal reference for both beginners and experienced researchers.Table of ContentsDemand based Land Suitability Prediction Model for Sustainable Agriculture.- Power Generation Forecasting of Wind Farms using Machine Learning Algorithms.- Music Recommendation System Based on Emotion Detection.- Service Analytics on ITSM Processes using Time Series.- Comparative Analysis of Color-based Segmentation Methods Used for Smartphone Camera Captured Fingerphotos.- Prediction of Heart Disease through KNN, Random Forest and Decision Tree Classifier using K-Fold Cross Validation.- Distance Matrix Generation for Dynamic Vehicle Routing Optimization in Transport Fleets Management.- Enhancing Weighted Support Vector Machine for Noise Classification.- Optimized Hysteresis Region Authenticated Handover for 5G HetNets.- Performance Improvement of CTNR Protocol in Wireless Sensor Network Using Machine Learning.

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a huge range and FREE tracked UK delivery on ALL orders.

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a huge range and FREE tracked UK delivery on ALL orders.

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Book SynopsisEmbedded systems are everywhere in contemporary life and are supposed to make our lives more comfortable. In industry, embedded systems are used to manage and control complex systems (e.g. nuclear power plants, telecommunications and flight control) and they are also taking an important place in our daily activities (e.g. smartphones, security alarms and traffic lights). In the design of embedded systems, memory allocation and data assignment are among the main challenges that electronic designers have to face. In fact, they impact heavily on the main cost metrics (power consumption, performance and area) in electronic devices. Thus designers of embedded systems have to pay careful attention in order to minimize memory requirements, thus improving memory throughput and limiting the power consumption by the system’s memory. Electronic designers attempt to minimize memory requirements with the aim of lowering the overall system costs. A state of the art of optimization techniques for memory management and data assignment is presented in this book.Table of ContentsIntroduction ix Chapter 1. Context 1 1.1. Embedded systems 2 1.1.1. Main components of embedded systems 3 1.2. Memory management for decreasing power consumption, performance and area in embedded systems 4 1.3. State of the art in optimization techniques for memory management and data assignment 8 1.3.1. Software optimization 9 1.3.2. Hardware optimization 11 1.3.3. Data binding 16 1.3.3.1. Memory partitioning problem for low energy 17 1.3.3.2. Constraints on memory bank capacities and number of accesses to variables 18 1.3.3.3. Using external memory 19 1.4. Operations research and electronics 21 1.4.1. Main challenges in applying operations research to electronics 23 Chapter 2. Unconstrained Memory Allocation Problem 27 2.1. Introduction 28 2.2. An ILP formulation for the unconstrained memory allocation problem 31 2.3. Memory allocation and the chromatic number 32 2.3.1. Bounds on the chromatic number 33 2.4. An illustrative example 35 2.5. Three new upper bounds on the chromatic number 38 2.6. Theoretical assessment of three upper bounds 45 2.7. Computational assessment of three upper bounds 49 2.8. Conclusion 53 Chapter 3. Memory Allocation Problem With Constraint on the Number of Memory Banks 57 3.1. Introduction 58 3.2. An ILP formulation for the memory allocation problem with constraint on the number of memory banks 61 3.3. An illustrative example 64 3.4. Proposed metaheuristics 65 3.4.1. A tabu search procedure 66 3.4.2. A memetic algorithm 69 3.5. Computational results and discussion 71 3.5.1. Instances 72 3.5.2. Implementation 72 3.5.3. Results 73 3.5.4. Discussion 75 3.6. Conclusion 75 Chapter 4. General Memory Allocation Problem 77 4.1. Introduction 78 4.2. ILP formulation for the general memory allocation problem 80 4.3. An illustrative example 84 4.4. Proposed metaheuristics 85 4.4.1. Generating initial solutions 86 4.4.1.1. Random initial solutions 86 4.4.1.2. Greedy initial solutions 86 4.4.2. A tabu search procedure 89 4.4.3. Exploration of neighborhoods 91 4.4.4. A variable neighborhood search hybridized with a tabu search 93 4.5. Computational results and discussion 94 4.5.1. Instances used 95 4.5.2. Implementation 95 4.5.3. Results 96 4.5.4. Discussion 97 4.5.5. Assessing TabuMemex 101 4.6. Statistical analysis 105 4.6.1. Post hoc paired comparisons 106 4.7. Conclusion 107 Chapter 5. Dynamic Memory Allocation Problem 109 5.1. Introduction 110 5.2. ILP formulation for dynamic memory allocation problem 113 5.3. An illustrative example 116 5.4. Iterative metaheuristic approaches 119 5.4.1. Long-term approach 119 5.4.2. Short-term approach 122 5.5. Computational results and discussion 123 5.5.1. Results 124 5.5.2. Discussion 125 5.6. Statistical analysis 128 5.6.1. Post hoc paired comparisons 129 5.7. Conclusion . 130 Chapter 6. MemExplorer: Cases Studies 131 6.1. The design flow 131 6.1.1. Architecture used 131 6.1.2. MemExplorer design flow 132 6.1.3. Memory conflict graph 134 6.2. Example of MemExplorer utilization 139 Chapter 7. General Conclusions and Future Work 147 7.1. Summary of the memory allocation problem versions 147 7.2. Intensification and diversification 149 7.2.1. Metaheuristics for memory allocation problem with constraint on the number of memory banks 149 7.2.1.1. Tabu-Allocation 149 7.2.1.2. Evo-Allocation 151 7.2.2. Metaheuristic for general memory allocation problem 151 7.2.3. Approaches for dynamic memory allocation problem 152 7.3. Conclusions 152 7.4. Future work 154 7.4.1. Theoretical perspectives 154 7.4.2. Practical perspectives 156 Bibliography 159 Index 181

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Book SynopsisSince the construction of the first embedded system in the 1960s, embedded systems have continued to spread. They provide a continually increasing number of services and are part of our daily life. The development of these systems is a difficult problem which does not yet have a global solution. Another difficulty is that systems are plunged into the real world, which is not discrete (as is generally understood in computing), but has a richness of behaviors which sometimes hinders the formulation of simplifying assumptions due to their generally autonomous nature and they must face possibly unforeseen situations (incidents, for example), or even situations that lie outside the initial design assumptions. Embedded Systems presents the state of the art of the development of embedded systems and, in particular, concentrates on the modeling and analysis of these systems by looking at “model-driven engineering”, (MDE2): SysML, UML/MARTE and AADL. A case study (based on a pacemaker) is presented which enables the reader to observe how the different aspects of a system are addressed using the different approaches. All three systems are important in that they provide the reader with a global view of their possibilities and demonstrate the contributions of each approach in the different stages of the software lifecycle. Chapters dedicated to analyzing the specification and code generation are also presented. Contents Foreword, Brian R. Larson.Foreword, Dominique Potier.Introduction, Fabrice Kordon, Jérôme Hugues, Agusti Canals and Alain Dohet.Part 1. General Concepts1. Elements for the Design of Embedded Computer Systems, Fabrice Kordon, Jérôme Hugues, Agusti Canals and Alain Dohet.2. Case Study: Pacemaker, Fabrice Kordon, Jérôme Hugues, Agusti Canals and Alain Dohet.Part 2. SysML3. Presentation of SysML Concepts, Jean-Michel Bruel and Pascal Roques.4. Modeling of the Case Study Using SysML, Loïc Fejoz, Philippe Leblanc and Agusti Canals.5. Requirements Analysis, Ludovic Apvrille and Pierre De Saqui-Sannes.Part 3. MARTE6. An Introduction to MARTE Concepts, Sébastien Gérard and François Terrier.7. Case Study Modeling Using MARTE, Jérôme Delatour and Joël Champeau.8. Model-Based Analysis, Frederic Boniol, Philippe Dhaussy, Luka Le Roux and Jean-Charles Roger.9. Model-Based Deployment and Code Generation, Chokri Mraidha, Ansgar Radermacher and Sébastien Gérard.Part 4. AADL10. Presentation of the AADL Concepts, Jérôme Hugues and Xavier Renault.11. Case Study Modeling Using AADL, Etienne Borde.12. Model-Based Analysis, Thomas Robert and Jérôme Hugues.13. Model-Based Code Generation, Laurent Pautet and Béchir Zalila.Table of ContentsForeword xiii Brian R. LARSON Foreword xv Dominique POTIER Introduction xix Fabrice KORDON, Jérôme HUGUES, Agusti CANALS and Alain DOHET PART 1. General Concepts 1 Chapter 1. Elements for the Design of Embedded Computer Systems 3 Fabrice KORDON, Jérôme HUGUES, Agusti CANALS and Alain DOHET 1.1. Introduction 3 1.2. System modeling 5 1.3. A brief presentation of UML 6 1.3.1. The UML static diagrams 7 1.3.2. The UML dynamic diagrams 9 1.4. Model-driven development approaches 10 1.4.1. The concepts 10 1.4.2. The technologies 11 1.4.3. The context of the wider field 12 1.5. System analysis 14 1.5.1. Formal verification via proving 15 1.5.2. Formal verification by model-checking 15 1.5.3. The languages to express specifications 16 1.5.4. The actual limits of formal approaches 19 1.6. Methodological aspects of the development of embedded computer systems 20 1.6.1. The main technical processes 22 1.6.2. The importance of the models 23 1.7. Conclusion 24 1.8. Bibliography 25 Chapter 2. Case Study: Pacemaker 29 Fabrice KORDON, Jérôme HUGUES, Agusti CANALS and Alain DOHET 2.1. Introduction 29 2.2. The heart and the pacemaker 30 2.2.1. The heart 30 2.2.2. Presentation of a pacemaker 32 2.3. Case study specification 33 2.3.1. System definition 34 2.3.2. System lifecycle 35 2.3.3. System requirements 36 2.3.4. Pacemaker behavior 39 2.4. Conclusion 42 2.5. Bibliography 43 PART 2. SysML 45 Chapter 3. Presentation of SysML Concepts 47 Jean-Michel BRUEL and Pascal ROQUES 3.1. Introduction 47 3.2. The origins of SysML 48 3.3. General overview: the nine types of diagrams 49 3.4. Modeling the requirements 50 3.4.1. Use case diagram 50 3.4.2. Requirement diagram 51 3.5. Structural modeling 53 3.5.1. Block definition diagram 54 3.5.2. Internal block diagram 56 3.5.3. Package diagram 58 3.6. Dynamic modeling 59 3.6.1. Sequence diagram 59 3.6.2. State machine diagram 61 3.6.3. Activity diagram 63 3.7. Transverse modeling 65 3.7.1. Parametric diagram 65 3.7.2. Allocation and traceability 67 3.8. Environment and tools 68 3.9. Conclusion 68 3.10. Bibliography 68 Chapter 4. Modeling of the Case Study Using SysML 71 Loïc FEJOZ, Philippe LEBLANC and Agusti CANALS 4.1. Introduction 71 4.2. System specification 73 4.2.1. Context 73 4.2.2. Requirements model and operational scenarios 75 4.2.3. Requirements model 78 4.3. System design 80 4.3.1. Functional model 81 4.3.2. Domain-specific data 83 4.3.3. Logical architectural model 86 4.3.4. Physical architectural model 90 4.4. Traceability and allocations 90 4.4.1. “Technical needs: divers” traceability diagram 90 4.4.2. Traceability diagram “technical needs: behavior of the pacemaker” 91 4.4.3. Allocation diagram 92 4.5. Test model 93 4.5.1. Traceability diagram “system test: requirements verification” 93 4.5.2. Sequence diagram for the test game TC-PM-07 94 4.5.3. Diagrams presenting a general view of the requirements 94 4.6. Conclusion 95 4.7. Bibliography 97 Chapter 5. Requirements Analysis 99 Ludovic APVRILLE and Pierre DE SAQUI-SANNES 5.1. Introduction 99 5.2. The AVATAR language and the TTool tool 100 5.2.1. Method 101 5.2.2. AVATAR language and SysML standard 101 5.2.3. The TEPE language for expressing properties 102 5.2.4. TTool 103 5.3. An AVATAR expression of the SysML model of the enhanced pacemaker 103 5.3.1. Functioning of the pacemaker and modeling hypotheses 103 5.3.2. Requirements diagram 104 5.4. Architecture 105 5.5. Behavior 106 5.6. Formal verification of the VVI mode 107 5.6.1. General properties 108 5.6.2. Expressing properties using TEPE 108 5.6.3. The use of temporal logic 109 5.6.4. Observer-guided verification 111 5.6.5. Coming back to the model 112 5.7. Related work 113 5.7.1. Languages 113 5.7.2. Tools 114 5.8. Conclusion 115 5.9. Appendix: TTool 116 5.10. Bibliography 116 PART 3. MARTE 119 Chapter 6. An Introduction to MARTE Concepts 121 Sébastien GÉRARD and François TERRIER 6.1. Introduction 121 6.2. General remarks 121 6.2.1. Possible uses of MARTE 122 6.2.2. How should we read the norm? 123 6.2.3. The MARTE architecture 124 6.2.4. MARTE and SysML 127 6.2.5. An open source support 128 6.3. Several MARTE details 128 6.3.1. Modeling non-functional properties 128 6.3.2. A components model for the real-time embedded system 133 6.4. Conclusion 137 6.5. Bibliography 137 Chapter 7. Case Study Modeling Using MARTE 139 Jérôme DELATOUR and Joël CHAMPEAU 7.1. Introduction 139 7.1.1. Hypotheses used in modeling 139 7.1.2. The modeling methodology used 140 7.1.3. Chapter layout 141 7.2. Software analysis 141 7.2.1. Use case and interface characterization 141 7.2.2. The sphere of application 144 7.3. Preliminary software design – the architectural component 145 7.3.1. The candidate architecture 146 7.3.2. Identifying the components 146 7.3.3. Presentation of the candidate architecture 148 7.3.4. A presentation of the detailed interfaces 150 7.4. Software preliminary design – behavioral component 151 7.4.1. The controller 151 7.4.2. The cardiologist 153 7.4.3. The operating modes of the cardiologist 153 7.5. Conclusion 155 7.6. Bibliography 156 Chapter 8. Model-Based Analysis 157 Frederic BONIOL, Philippe DHAUSSY, Luka LE ROUX and Jean-Charles ROGER 8.1. Introduction 157 8.2. Model and requirements to be verified 161 8.2.1. The UML-MARTE model that needs to be translated in Fiacre 161 8.2.2. Fiacre language 162 8.2.3. The translation principles of the UML model in Fiacre 163 8.2.4. Requirements 165 8.3. Model-checking of the requirements 166 8.3.1. Use case 166 8.3.2. Properties 167 8.3.3. Property check 170 8.3.4. First assessment 172 8.4. Context exploitation 172 8.4.1. Identifying the context scenarios 173 8.4.2. Automatic partitioning of the context graphs 174 8.4.3. CDL language 175 8.4.4. CDL model exploitation in a model-checker 177 8.4.5. Description of a CDL context 178 8.4.6. Results 179 8.5. Assessment 180 8.6. Conclusion 181 8.7. Bibliography 182 Chapter 9. Model-Based Deployment and Code Generation 185 Chokri MRAIDHA, Ansgar RADERMACHER and Sébastien GÉRARD 9.1. Introduction 185 9.2. Input models 187 9.2.1. Description of the executable component-based model 187 9.2.2. Description of the platform model 188 9.2.3. Description of the deployment model 189 9.3. Generation of the implementation model 190 9.3.1. Main concepts 191 9.3.2. Connector pattern 191 9.3.3. Container pattern 193 9.3.4. Implementation of the components 195 9.3.5. Resulting implementation components 197 9.4. Code generation 197 9.4.1. Deployment of the components 198 9.4.2. Transformation into an object-oriented model 199 9.4.3. Generating code 200 9.5. Support tools 201 9.6. Conclusion 202 9.7. Bibliography 202 PART 4. AADL 205 Chapter 10. Presentation of the AADL Concepts 207 Jérôme HUGUES and Xavier RENAULT 10.1. Introduction 207 10.2. General ADL concepts 207 10.3. AADLv2, an ADL for design and analysis 208 10.3.1. A history of the AADL 208 10.3.2. A brief introduction to AADL 209 10.3.3. Tools 211 10.4. Taxonomy of the AADL entities 211 10.4.1. Language elements: the components 212 10.4.2. Connections between the components 214 10.4.3. Language elements: attributes 215 10.4.4. Language elements: extensions and refinements 219 10.5. AADL annexes 220 10.5.1. Data modeling annex 220 10.6. Analysis of AADL models 221 10.6.1. Structural properties 222 10.6.2. Qualitative properties 222 10.6.3. Quantitative properties 223 10.7. Conclusion 224 10.8. Bibliography 225 Chapter 11. Case Study Modeling Using AADL 227 Etienne BORDE 11.1. Introduction 227 11.2. Review of the structure of a pacemaker 229 11.3. AADL modeling of the structure of the pacemaker 230 11.3.1. Decomposition of the system into several subsystems 230 11.3.2. Execution and communication infrastructure 233 11.4. Overview of the functioning of the pacemaker 235 11.4.1. The operational modes of the pacemaker 235 11.4.2. The operational sub-modes of the pacemaker 235 11.4.3. Some functionalities of the pacemaker 237 11.5. AADL modeling of the software architecture of the pulse generator 240 11.5.1. AADL modeling of the operational modes of the pulse generator 240 11.5.2. AADL modeling of the features of the pulse generator in the permanent mode 242 11.6. Modeling of the deployment of the pacemaker 247 11.7. Conclusion 249 11.8. Bibliography 250 Chapter 12. Model-Based Analysis 251 Thomas ROBERT and Jérôme HUGUES 12.1. Introduction 251 12.2. Behavioral validation, per mode and global 252 12.2.1. Validation context and fine tuning of the requirements 253 12.2.2. Translation of the behavioral automata into UPPAAL 253 12.2.3. Refining requirements 22-23/P 258 12.2.4. Study of the permanent/VVT mode 260 12.2.5. Study of the changing of the permanent/VVT→Magnet/VOO mode 261 12.3. Conclusion 262 12.4. Bibliography 263 Chapter 13. Model-Based Code Generation 265 Laurent PAUTET and Béchir ZALILA 13.1. Introduction 265 13.2. Software component generation 268 13.2.1. Data conversion 269 13.2.2. Conversion of subprograms 272 13.2.3. Conversion of execution threads 275 13.2.4. Conversion of the instances of shared data 283 13.3. Middleware components generation 283 13.4. Configuration and deployment of middleware components 284 13.4.1. Deployment 284 13.5. Integration of the compilation chain 285 13.6. Conclusion 287 13.7. Bibliography 287 List of Authors 289 Index 291

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