Computer architecture and logic design Books
Morgan & Claypool Publishers Shared-Memory Parallelism Can Be Simple, Fast,
Book SynopsisParallelism is the key to achieving high performance in computing. However, writing efficient and scalable parallel programs is notoriously difficult, and often requires significant expertise. To address this challenge, it is crucial to provide programmers with high-level tools to enable them to develop solutions easily, and at the same time emphasize the theoretical and practical aspects of algorithm design to allow the solutions developed to run efficiently under many different settings. This thesis addresses this challenge using a three-pronged approach consisting of the design of shared-memory programming techniques, frameworks, and algorithms for important problems in computing. The thesis provides evidence that with appropriate programming techniques, frameworks, and algorithms, shared-memory programs can be simple, fast, and scalable, both in theory and in practice. The results developed in this thesis serve to ease the transition into the multicore era.The first part of this thesis introduces tools and techniques for deterministic parallel programming, including means for encapsulating nondeterminism via powerful commutative building blocks, as well as a novel framework for executing sequential iterative loops in parallel, which lead to deterministic parallel algorithms that are efficient both in theory and in practice. The second part of this thesis introduces Ligra, the first high-level shared memory framework for parallel graph traversal algorithms. The framework allows programmers to express graph traversal algorithms using very short and concise code, delivers performance competitive with that of highly-optimized code, and is up to orders of magnitude faster than existing systems designed for distributed memory. This part of the thesis also introduces Ligra , which extends Ligra with graph compression techniques to reduce space usage and improve parallel performance at the same time, and is also the first graph processing system to support in-memory graph compression.The third and fourth parts of this thesis bridge the gap between theory and practice in parallel algorithm design by introducing the first algorithms for a variety of important problems on graphs and strings that are efficient both in theory and in practice. For example, the thesis develops the first linear-work and polylogarithmic-depth algorithms for suffix tree construction and graph connectivity that are also practical, as well as a work-efficient, polylogarithmic-depth, and cache-efficient shared-memory algorithm for triangle computations that achieves a 2–5x speedup over the best existing algorithms on 40 cores.This is a revised version of the thesis that won the 2015 ACM Doctoral Dissertation Award.Table of Contents Introduction Preliminaries and Notation Programming Techniques for Deterministic Parallelism Internally Deterministic Parallelism: Techniques and Algorithms Deterministic Parallelism in Sequential Iterative Algorithms A Deterministic Phase-Concurrent Parallel Hash Table Priority Updates: A Contention-Reducing Primitive for Deterministic Programming Large-Scale Shared-Memory Graph Analytics Ligra: A Lightweight Graph Processing Framework for Shared Memory Ligra : Adding Compression to Ligra Parallel Graph Algorithms Linear-Work Parallel Graph Connectivity Parallel and Cache-Oblivious Triangle Computations Parallel String Algorithms Parallel Cartesian Tree and Suffix Tree Construction Parallel Computation of Longest Common Prefixes Parallel Lempel-Ziv Factorization Parallel Wavelet Tree Construction Conclusion and Future Work Bibliography
£71.20
Morgan & Claypool Publishers Shared-Memory Parallelism Can Be Simple, Fast,
Book SynopsisParallelism is the key to achieving high performance in computing. However, writing efficient and scalable parallel programs is notoriously difficult, and often requires significant expertise. To address this challenge, it is crucial to provide programmers with high-level tools to enable them to develop solutions easily, and at the same time emphasize the theoretical and practical aspects of algorithm design to allow the solutions developed to run efficiently under many different settings. This thesis addresses this challenge using a three-pronged approach consisting of the design of shared-memory programming techniques, frameworks, and algorithms for important problems in computing. The thesis provides evidence that with appropriate programming techniques, frameworks, and algorithms, shared-memory programs can be simple, fast, and scalable, both in theory and in practice. The results developed in this thesis serve to ease the transition into the multicore era.The first part of this thesis introduces tools and techniques for deterministic parallel programming, including means for encapsulating nondeterminism via powerful commutative building blocks, as well as a novel framework for executing sequential iterative loops in parallel, which lead to deterministic parallel algorithms that are efficient both in theory and in practice. The second part of this thesis introduces Ligra, the first high-level shared memory framework for parallel graph traversal algorithms. The framework allows programmers to express graph traversal algorithms using very short and concise code, delivers performance competitive with that of highly-optimized code, and is up to orders of magnitude faster than existing systems designed for distributed memory. This part of the thesis also introduces Ligra , which extends Ligra with graph compression techniques to reduce space usage and improve parallel performance at the same time, and is also the first graph processing system to support in-memory graph compression.The third and fourth parts of this thesis bridge the gap between theory and practice in parallel algorithm design by introducing the first algorithms for a variety of important problems on graphs and strings that are efficient both in theory and in practice. For example, the thesis develops the first linear-work and polylogarithmic-depth algorithms for suffix tree construction and graph connectivity that are also practical, as well as a work-efficient, polylogarithmic-depth, and cache-efficient shared-memory algorithm for triangle computations that achieves a 2–5x speedup over the best existing algorithms on 40 cores.This is a revised version of the thesis that won the 2015 ACM Doctoral Dissertation Award.Table of Contents Introduction Preliminaries and Notation Programming Techniques for Deterministic Parallelism Internally Deterministic Parallelism: Techniques and Algorithms Deterministic Parallelism in Sequential Iterative Algorithms A Deterministic Phase-Concurrent Parallel Hash Table Priority Updates: A Contention-Reducing Primitive for Deterministic Programming Large-Scale Shared-Memory Graph Analytics Ligra: A Lightweight Graph Processing Framework for Shared Memory Ligra : Adding Compression to Ligra Parallel Graph Algorithms Linear-Work Parallel Graph Connectivity Parallel and Cache-Oblivious Triangle Computations Parallel String Algorithms Parallel Cartesian Tree and Suffix Tree Construction Parallel Computation of Longest Common Prefixes Parallel Lempel-Ziv Factorization Parallel Wavelet Tree Construction Conclusion and Future Work Bibliography
£89.25
Springer Nature Switzerland AG Introduction to Computation: Haskell, Logic and
Book SynopsisComputation, itself a form of calculation, incorporates steps that include arithmetical and non-arithmetical (logical) steps following a specific set of rules (an algorithm). This uniquely accessible textbook introduces students using a very distinctive approach, quite rapidly leading them into essential topics with sufficient depth, yet in a highly intuitive manner. From core elements like sets, types, Venn diagrams and logic, to patterns of reasoning, calculus, recursion and expression trees, the book spans the breadth of key concepts and methods that will enable students to readily progress with their studies in Computer Science.Trade Review“This book is intended as a textbook for an introductory course in computation for students beginning in informatics. No prerequisites are needed, all concepts, even elementary ones ... . it is also very suited for self-study, even if a reader is interested in Haskell or symbolic logic alone. ... Comprehension is supported by exercises for each chapter ... .” (Dieter Riebesehl, zbMATH 1497.68005, 2022)Table of Contents1 Sets 132 Types 193 Simple Computations 274 Venn Diagrams and Logical Connectives 355 Lists and Comprehensions 456 Features and Predicates 557 Testing Your Programs 638 Patterns of Reasoning 739 More Patterns of Reasoning 8110 Lists and Recursion 9111 More Fun with Recursion 10112 Higher-Order Functions 11113 Higher and Higher 12314 Sequent Calculus 13115 Algebraic Data Types 14316 Expression Trees 15717 Karnaugh Maps 17518 Relations and Quantifiers 18319 Checking Satisfiability 19120 Data Representation 20321 Data Abstraction 22122 Efficient CNF Conversion 23723 Counting Satisfying Valuations 24924 Type Classes 26325 Search in Trees 27526 Combinatorial Algorithms 28527 Finite Automata 29928 Deterministic Finite Automata 31129 Non-Deterministic Finite Automata 32130 Input/Output and Monads 34131 Regular Expressions 35932 Non-Regular Languages 369Index 377
£28.49
Springer Nature Switzerland AG Formal Verification of Floating-Point Hardware
Book SynopsisThis is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods. Formal Verification of Floating-Point Hardware Design, Second Edition advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies. The theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations. As a basis for the formal verification of such implementations, high-level specifications of the basic arithmetic instructions of several major industry-standard floating-point architectures are presented, including all details pertaining to the handling of exceptional conditions. The methodology is illustrated in the comprehensive verification of a variety of state-of-the-art commercial floating-point designs developed by Arm Holdings. This revised edition reflects the evolving microarchitectures and increasing sophistication of Arm processors, and the variation in the design goals of execution speed, hardware area requirements, and power consumption. Many new results have been added to Parts I—III (Register-Transfer Logic, Floating-Point Arithmetic, and Implementation of Elementary Operations), extending the theory and describing new techniques. These were derived as required in the verification of the new RTL designs described in Part V. Table of ContentsPart I - Register-Transfer Logic.- Basic Arithmetic Functions.- Bit Vectors.- Logical Operations.- Part II - Floating-Point Arithmetic.- Floating-Point Numbers.- Floating-Point Formats.- Rounding.- IEEE-Compliant Square Root.- Part III - Implementation of Elementary Operations.- Addition.- Multiplication.- SRT Division and Square Root.- FMA-Based Division.- Part IV - Comparative Architectures: SSE, x87, and Arm.- SSE Floating-Point Instructions.- x87 Instructions.- Arm Floating-Point.- Instructions.- Part V - Formal Verification of RTL Designs.- The RAC Modeling Language.- Double-Precision Multiplication and Scaling.- Double-Precision Addition and FMA.- Multi-Precision Radix-8 SRT Division.- 64-bit Integer Division.- Multi-Precision Radix-4 SRT Square Root.- Multi-Precision Radix-2 SRT Division.- Fused Multiply-Add of a Graphics Processor.
£113.99
Springer Nature Switzerland AG VLSI Physical Design: From Graph Partitioning to
Book SynopsisThe complexity of modern chip design requires extensive use of specialized software throughout the process. To achieve the best results, a user of this software needs a high-level understanding of the underlying mathematical models and algorithms. In addition, a developer of such software must have a keen understanding of relevant computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. This book introduces and compares the fundamental algorithms that are used during the IC physical design phase, wherein a geometric chip layout is produced starting from an abstract circuit design. This updated second edition includes recent advancements in the state-of-the-art of physical design, and builds upon foundational coverage of essential and fundamental techniques. Numerous examples and tasks with solutions increase the clarity of presentation and facilitate deeper understanding. A comprehensive set of slides is available on the Internet for each chapter, simplifying use of the book in instructional settings.“This improved, second edition of the book will continue to serve the EDA and design community well. It is a foundational text and reference for the next generation of professionals who will be called on to continue the advancement of our chip design tools and design the most advanced micro-electronics.” Dr. Leon Stok, Vice President, Electronic Design Automation, IBM Systems Group“This is the book I wish I had when I taught EDA in the past, and the one I’m using from now on.” Dr. Louis K. Scheffer, Howard Hughes Medical Institute“I would happily use this book when teaching Physical Design. I know of no other work that’s as comprehensive and up-to-date, with algorithmic focus and clear pseudocode for the key algorithms. The book is beautifully designed!”Prof. John P. Hayes, University of Michigan“The entire field of electronic design automation owes the authors a great debt for providing a single coherent source on physical design that is clear and tutorial in nature, while providing details on key state-of-the-art topics such as timing closure.”Prof. Kurt Keutzer, University of California, Berkeley“An excellent balance of the basics and more advanced concepts, presented by top experts in the field.” Prof. Sachin Sapatnekar, University of MinnesotaTable of Contents1 Introduction. 1.1 Electronic Design Automation (EDA). 1.2 VLSI Design Flow. 1.3 VLSI Design Styles. 1.4 Layout Layers and Design Rules. 1.5 Physical Design Optimizations. 1.6 Algorithms and Complexity. 1.7 Graph Theory Terminology. 1.8 Common EDA Terminology. 2 Netlist and System Partitioning. 2.1 Introduction. 2.2 Terminology. 2.3 Optimization Goals. 2.4 Partitioning Algorithms. 2.5 A Framework for Multilevel Partitioning. 2.6 System Partitioning onto Multiple FPGAs. Chapter 2 Exercises.3 Chip Planning. 3.1 Introduction to Floorplanning. 3.2 Optimization Goals in Floorplanning. 3.3 Terminology. 3.4 Floorplan Representations. 3.5 Floorplanning Algorithms. 3.6 Pin Assignment. 3.7 Power and Ground Routing. Chapter 3 Exercises.4 Global and Detailed Placement. 4.1 Introduction. 4.2 Optimization Objectives. 4.3 Global Placement. 4.4 Legalization and Detailed Placement. Chapter 4 Exercises.5 Global Routing. 5.1 Introduction. 5.2 Terminology and Definitions. 5.3 Optimization Goals. 5.4 Representations of Routing Regions. 5.5 The Global Routing Flow. 5.6 Single-Net Routing. 5.7 Full-Netlist Routing. 5.8 Modern Global Routing. Chapter 5 Exercises.6 Detailed Routing. 6.1 Terminology. 6.2 Horizontal and Vertical Constraint Graphs. 6.3 Channel Routing Algorithms. 6.4 Switchbox Routing. 6.5 Over-the-Cell Routing Algorithms. 6.6 Modern Challenges in Detailed Routing. Chapter 6 Exercises.7 Specialized Routing. 7.1 Introduction to Area Routing. 7.2 Net Ordering in Area Routing. 7.3 Non-Manhattan Routing. 7.4 Basic Concepts in Clock Networks. 7.5 Modern Clock Tree Synthesis. Chapter 7 Exercises.8 Timing Closure. 8.1 Introduction. 8.2 Timing Analysis and Performance Constraints. 8.3 Timing-Driven Placement. 8.4 Timing-Driven Routing. 8.5 Physical Synthesis. 8.6 Performance-Driven Design Flow. 8.7 Conclusions. Chapter 8 Exercises. A Solutions to Chapter Exercises. B Example CMOS Cell Layouts.
£66.49
Springer Nature Switzerland AG 3D Interconnect Architectures for Heterogeneous
Book SynopsisThis book describes the first comprehensive approach to the optimization of interconnect architectures in 3D systems on chips (SoCs), specially addressing the challenges and opportunities arising from heterogeneous integration. Readers learn about the physical implications of using heterogeneous 3D technologies for SoC integration, while also learning to maximize the 3D-technology gains, through a physical-effect-aware architecture design. The book provides a deep theoretical background covering all abstraction-levels needed to research and architect tomorrow’s 3D-integrated circuits, an extensive set of optimization methods (for power, performance, area, and yield), as well as an open-source optimization and simulation framework for fast exploration of novel designs.Table of ContentsPart I Introduction1 Introduction to 3D Technologies 1.1 Motivation for Heterogenous 3D ICs 1.2 3D Technologies 1.3 TSV Capacitances—A Problem Resistant to Scaling 1.4 Conclusion 2 Interconnect Architectures for 3D Technologies 2.1 Interconnect Architectures 2.2 Overview of Interconnect Architectures for 3D ICs 2.3 Three-dimensional Networks on chips 2.4 Conclusion Part II 3D Technology Modeling 3 Power and Performance Formulas 3.1 High-Level Formula for the Power Consumption 3.2 High-Level Formula for the Propagation Delay 3.3 Matrix Formulations 3.4 Evaluation 3.5 Conclusion 4 Capacitance Estimation 4.1 Existing Capacitance Models 4.2 Edge and MOS Effects on the TSV Capacitances 4.3 TSV Capacitance Model 4.4 Evaluation 4.5 Conclusion Part III System Modeling xiii xiv Contents 5 Application and Simulation Models 5.1 Overview of the Modeling Approach 5.2 Application Traffic Model 5.3 Simulation Model of 3D NoCs 5.4 Simulator Interfaces 5.5 Conclusion 6 Bit-level Statistics 6.1 Existing Approaches to Estimate the Bit-Level Statistics for Single Data Streams 6.2 Data-Stream Multiplexing 6.3 Bit-Level Statistics with Data-Stream Multiplexing 6.4 Evaluation 6.5 Conclusion 7 Ratatoskr Framework 7.1 Ratatoskr for Practitioners 7.2 Implementation 7.3 Evaluation 7.4 Case Study: Link Power Estimation and Optimization 7.5 Conclusion Part IV 3D-Interconnect Optimization 8 Low-Power Technique for 3D Interconnects 8.1 Fundamental Idea 8.2 Power-Optimal TSV assignment 8.3 Systematic Net-to-TSV Assignments 8.4 Combination with Traditional Low-Power Codes 8.5 Evaluation 8.6 Conclusion 9 Low-Power Technique for High-Performance 3D Interconnects. 9.1 Edge-Effect-Aware Crosstalk Classification 9.2 Existing Approaches and Their Limitations 9.3 Proposed Technique 9.4 Extension to a Low-Power 3D CAC 9.5 Evaluation 9.6 Conclusion 10 Low-Power Technique for High-Performance 3D Interconnects (Misaligned) 10.1 Temporal-Misalignment Effect on the Crosstalk 10.2 Exploiting Misalignment to Improve the Performance 10.3 Effect on the TSV Power Consumption Contents xv 10.4 Evaluation 10.5 Conclusion 11 Low-Power Technique for Yield-Enhanced 3D Interconnects 11.1 Existing TSV Yield-Enhancement Techniques 11.2 Preliminaries—Logical Impact of TSV Faults 11.3 Fundamental Idea 11.4 Formal Problem Description 11.5 TSV Redundancy Schemes 11.6 Evaluation 11.7 Case Study 11.8 Conclusion Part V NoC Optimization for Heterogeneous 3D Integration 12 Heterogeneous Buffering for 3D NoCs251 12.1 Buffer Distributions and Depths 12.2 Routers with Optimized Buffer Distribution 12.3 Routers with Optimized Buffer Depths 12.4 Evaluation 12.5 Discussion 12.6 Conclusion 13 Heterogeneous Routing for 3D NoCs 13.1 Heterogeneity and Routing 13.2 Modeling Heterogeneous Technologies 13.3 Modeling Communication 13.4 Routing Limitations from Heterogeneity 13.5 Heterogeneous Routing Algorithms 13.6 Heterogeneous Router Architectures 13.7 Low-Power Routing in Heterogeneous 3D ICs 13.8 Evaluation 13.9 Discussion 13.10Conclusion 14 Heterogeneous Virtualisation for 3D NoCs 14.1 Problem Description 14.2 Heterogeneous Microarchitectures Exploiting Traffic Imbalance 14.3 Evaluation 14.4 Conclusion 15 Network Synthesis and SoC Floor Planning 15.1 Fundamental Idea 15.2 Modelling and Optimization 15.3 Mixed-Integer Linear Program 15.4 Heuristic Solution xvi Contents 15.5 Evaluation 15.6 Conclusion Part VI Finale 16 Conclusion 16.1 Putting it all together 16.2 Impact on Future Work A Appendix B Pseudo Codes C Method to Calculate the Depletion-Region Widths D Modeling Logical OR Relations
£94.99
Springer International Publishing AG Performance Analysis and Tuning for General Purpose Graphics Processing Units (GPGPU)
Book SynopsisGeneral-purpose graphics processing units (GPGPU) have emerged as an important class of shared memory parallel processing architectures, with widespread deployment in every computer class from high-end supercomputers to embedded mobile platforms. Relative to more traditional multicore systems of today, GPGPUs have distinctly higher degrees of hardware multithreading (hundreds of hardware thread contexts vs. tens), a return to wide vector units (several tens vs. 1-10), memory architectures that deliver higher peak memory bandwidth (hundreds of gigabytes per second vs. tens), and smaller caches/scratchpad memories (less than 1 megabyte vs. 1-10 megabytes). In this book, we provide a high-level overview of current GPGPU architectures and programming models. We review the principles that are used in previous shared memory parallel platforms, focusing on recent results in both the theory and practice of parallel algorithms, and suggest a connection to GPGPU platforms. We aim to provide hints to architects about understanding algorithm aspect to GPGPU. We also provide detailed performance analysis and guide optimizations from high-level algorithms to low-level instruction level optimizations. As a case study, we use n-body particle simulations known as the fast multipole method (FMM) as an example. We also briefly survey the state-of-the-art in GPU performance analysis tools and techniques. Table of Contents: GPU Design, Programming, and Trends / Performance Principles / From Principles to Practice: Analysis and Tuning / Using Detailed Performance Analysis to Guide OptimizationTable of ContentsGPU Design, Programming, and Trends.- Performance Principles.- From Principles to Practice: Analysis and Tuning.- Using Detailed Performance Analysis to Guide Optimization.
£23.74
Springer International Publishing AG Completion Detection in Asynchronous Circuits:
Book SynopsisThis book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits.Table of Contents1) Introduction to asynchronous circuit design2) "Preliminary considerations for asynchronous circuit design"3) "Completion detection schemes for asynchronous design style"4) Case Studies: Barrel shifter and binary adders5) "Generic Architecture of deterministic completion detection scheme"6) "Architecture optimization using deterministic completion detection"7) Simulations
£66.49
Springer International Publishing AG Engineering Design: A Survival Guide to Senior
Book SynopsisEngineering Senior Design is perhaps the course that most resembles what an engineering professional will be required to do during their career; it is the bridge between the academic classroom and the engineering profession. This textbook will support students as they learn to apply their previously-developed skills to solve a complex engineering problem during a senior-level design course. This textbook follows the design life cycle from project initiation to completion and introduces students to many soft engineering skills, such as communication, scheduling, and technical writing, in the context of an engineering design. Students are instructed how to define an engineering problem with a valid problem statement and requirements document. They will conceptualize a complex solution and divide that solution into manageable subsystems. More importantly, they will be introduced to Project Management techniques that will help students organize workloads, develop functional engineering-teams, and validate solutions, all while increasing the likelihood of a successful completion to the project. Throughout the experience, students are instructed that a well-intentioned solution is not particularly useful unless it can be communicated and documented. To that end, this textbook will help students document their work in a professional manner and to present their ideas to stakeholders in a variety of formal design-reviews. With the support of this textbook, by the end of a student’s senior design experience, each individual will be ready to communicate with other engineering professionals, effectively support engineering design-teams, and manage complex project to solve the next generation’s engineering challenges.Table of Contents1. Introduction to Senior Design2. Meeting your design team for the first time (How to run an effective meeting)3. Daily Documentation (Engineering Notebooks)4. The Initiation Phase5. The Planning Phase6. The Execution Phase7. The Closing Phase.
£52.24
Springer International Publishing AG Bio/CMOS Interfaces and Co-Design
Book SynopsisThis textbook demonstrates new paradigms for the interface between CMOS circuits and the biological world. A deep theoretical description of such an interface is defined and discussed, while various real applications are demonstrated by also discussing several analog CMOS circuits. Electrochemical techniques are proposed in detail to learn how to design integrated biosensors. Biological materials are described to provide devices selectivity. Nanoscale materials are discussed to provide device sensitivity. CMOS circuits are analyzed to provide real applications. Extensive examples with solutions are provided, as well as exercises at the end of each chapter. This book introduces students to the state-of-the-art in Bio/CMOS interfaces, describing leading-edge research in CMOS design and VLSI development for applications requiring intimate integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in biosensing applications.Table of ContentsIntroduction.- Chemistry of Conductive Solutions.- Biochemistry of Targets and Probes.- Target/Probe interactions.- Surface Immobilization of Probes.- Nano Technology to prevent Electron Transfer.- Bio/CMOS interface for Label-free Capacitance Sensing.- nanotechnology to enhance electron transfer.- Bio/CMOS interface in Constant Bias.-Bio/CMOS interface in Voltage Scan.- Appendix 1 - Basic Chemistry.- Appendix 2 - Basic Configurations of Operational Amplifiers.- Appendix 3 - The Fourier Theorem.- Appendix 4 - The Fourier and Laplace Transforms.
£89.99
Springer International Publishing AG Reversible Computation: 15th International
Book SynopsisThis book constitutes the refereed proceedings of the 15th International Conference on Reversible Computation, RC 2023, held in Giessen, Germany, during July 18–19, 2023.The 11 full papers and 3 short papers included in this book were carefully reviewed and selected from 19 submissions. They were organized in topical sections as follows: Foundations; Reversible Programming; Quantum Computing; and Quantum Circuits.Table of ContentsInvited Paper.- Energy complexity of computation.- Foundations.- Replications in Reversible Concurrent Calculi.- Towards a Taxonomy for Reversible Computation Approaches.- Computational Complexity of Reversible Reaction Systems.- Reversible Programming.- Optimization of Reversible Control Flow Graphs.- Tail recursion transformation for invertible functions.- Saving Memory Space in Deep Neural Networks by Recomputing: A Survey.- Towards a Dereversibilizer: Fewer Asserts, Statically.- Quantum Computing.- Quantum String Matching Unfolded and Extended.- Optimizing Quantum Space using Spooky Pebble Games.- Uncomputation in the Qrisp high-level Quantum Programming Framework.- Quantum Circuits.- Improved Synthesis of Tooli-Hadamard Circuits.- Implementation of a Reversible Distributed Calculus.- Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture.- Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures.
£47.49
Springer International Publishing AG Reversible Computation
Book Synopsis
£76.03
Springer Neuromorphic Computing Principles and Organization
Book SynopsisFoundations of Neuromorphic Computing.- Neuromorphic System Design Fundamentals.- Learning in Neuromorphic Computing Systems.- Emerging Memory Devices for Neuromorphic Systems.- Communication Networks for Neuromorphic Systems.- Fault-Tolerant Neuromorphic System Design.- Reconfigurable Neuromorphic Computing Systems.- Practical Design and Implementation of 3D-NoC-Based NeuromorphicSystem (RNASH).- Case Study: Advanced Neuromorphic Prosthetic Design.- Comprehensive Review of Neuromorphic Systems.- Index.
£61.74
Springer International Publishing AG FPGAs for Software Programmers
Book SynopsisThis book makes powerful Field Programmable Gate Array (FPGA) and reconfigurable technology accessible to software engineers by covering different state-of-the-art high-level synthesis approaches (e.g., OpenCL and several C-to-gates compilers). It introduces FPGA technology, its programming model, and how various applications can be implemented on FPGAs without going through low-level hardware design phases. Readers will get a realistic sense for problems that are suited for FPGAs and how to implement them from a software designer’s point of view. The authors demonstrate that FPGAs and their programming model reflect the needs of stream processing problems much better than traditional CPU or GPU architectures, making them well-suited for a wide variety of systems, from embedded systems performing sensor processing to large setups for Big Data number crunching. This book serves as an invaluable tool for software designers and FPGA design engineers who are interested in high design productivity through behavioural synthesis, domain-specific compilation, and FPGA overlays. Introduces FPGA technology to software developers by giving an overview of FPGA programming models and design tools, as well as various application examples; Provides a holistic analysis of the topic and enables developers to tackle the architectural needs for Big Data processing with FPGAs; Explains the reasons for the energy efficiency and performance benefits of FPGA processing; Provides a user-oriented approach and a sense for where and how to apply FPGA technology. Table of ContentsIntroduction.- CPUs, GPUs, CGRAs, Vector Processing, Systolic Arrays, FPGAs.- The von Neuman Model versus data stream processing.- FPGAs for software designers.- Languages, libraries, and compilers for specific problems.- Behavioral Compiler Capabilities and optimization strategies.- Mapping Approaches and Tools for Heterogeneous FPGAs.- Automatic Tool Flows.- Design frameworks, tools, and tool interaction.- Hardware Platforms.- Parallel Architectures and Overlays.- FPGA Virtualization.- Applications from a Programmers Point of View.- Future Directions.
£113.99
Springer International Publishing AG ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies
Book SynopsisThis book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.Table of ContentsChapter 1.Introduction.- Chapter 2.Functional Verification- Challeenges and Solution.- Chapter 3.SystemVerilog Paradigm.- Chapter 4. UVM.- Chapter 5.CRV.- Chapter 6.SVA.- Chapter 7.SFC.- Chapter 8.CDC.- Chapter 9.Low Power Verification.- Chapter 10. Static Verification.- Chapter 11.ESL.- Chapter 12. Hardware/Software Co-verification.- Chapter 13.- Analog Mixed Signals Verification.- Chapter 14.- SOC Interconnect Verification.- Chapter 15. The Complete Product Design Lifecycle.- Chapter 16. Voice Over IP.- Chapter 17. Cache Memory Subsystem Verification: UVM Agent Based.- Chapter 18. Cache Memory Subsystem Verification: ISS Based.
£113.99
Springer Fachmedien Wiesbaden Eigenschaftsorientierte Beschreibung der
Book SynopsisDavid Trachtenherz entwickelt einen Lösungsansatz zur eigenschaftsorientierten Beschreibung der logischen Architektur eingebetteter Systeme, der eine präzise deklarative Spezifikation funktionaler Eigenschaften mit wählbarem Grad der Abstraktion für unterschiedliche Entwicklungsphasen und -ebenen ermöglicht.Table of ContentsLogische Architektur; Formale Grundlagen; Grundlagen eigenschaftsorientierter Architekturbeschreibung; Anschauliche Darstellung eigenschaftsorientierter Architekturspezifikation; Fallstudie ; Ströme und temporale Logik in Isabelle/HOL
£61.19
Springer Fachmedien Wiesbaden Logikkalküle in der Informatik: Wie wird Logik
Book SynopsisIm Mittelpunkt steht das Spannungsverhältnis zwischen einerseits dem herkömmlichen Logikansatz mit Begriffen wie Signatur, Struktur, Wahrheitswert und andererseits dem eher dynamisch ausgerichteten Begriff des Kalküls, also zwischen Semantik und Syntax. Wie dieser Graben überwunden wird, wird für verschiedene auch nicht-klassische Logiken vorgeführt: Prädikatenlogik, modale, temporale, nichtmonotone, epistemische Logik und andere. Dadurch wird insbesondere auch eine einführende Übersicht über Logiken gegeben, die an manchen Stellen der Informatik benötigt werden, zu deren Verständnis man sich aber kein ganzes spezielles Buch anschaffen möchte. Das Buch enthält einen einheitlichen Ansatz für verschiedene Logiken. Table of ContentsAussagenlogik - Prädikatenlogik – SLD-Kalkül – Modale Logik – Temporale Logik – Epistemische Logik – Deontische Logik – Nichtmonotone Logik – Default-Logik
£23.74
Springer Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications
Book SynopsisThis work is a comprehensive study of the field. It provides an entry point to the novice willing to move in the research field reconfigurable computing, FPGA and system on programmable chip design. The book can also be used as teaching reference for a graduate course in computer engineering, or as reference to advance electrical and computer engineers. It provides a very strong theoretical and practical background to the field, from the early Estrin’s machine to the very modern architecture such as embedded logic devices.Trade ReviewThe book by Christophe Bobda, however, has also been written for people with a software background, substantially reducing the educational leap by bridging the gap. His book has the potential to become a best-seller and to stimulate the urgently needed transformation of the software developer population’s mind set, by playing a similar role as known from the famous historic Mead-&-Conway textbook for the VLSI design revolution. Reiner Hartenstein, IEEE fellow, Professor, TU Kaiserslautern "Table of ContentsForeword. Preface. List of Figures. List of Tables. 1. INTRODUCTION. 1 General Purpose Computing. 2 Domain Specific Processors. 3 Application Specific Processors. 4 Reconfigurable Computing. 5 Fields of Application. 6 Organization of the book. 2. RECONFIGURABLE ARCHITECTURES. 1 Early Work. 2 Simple Programmable Logic Devices. 3 Complex Programmable Logic Device. 4 Field Programmable Gate Arrays. 5 Coarse-grained reconfigurable devices. 6 Conclusion. 3. IMPLEMENTATION. 1 Integration. 2 FPGA Design Flow. 3 Logic Synthesis. 4 Conclusion. 4. HIGH-LEVEL SYNTHESIS FOR RECONFIGURABLE DEVICES. 1 Modelling. 2 Temporal partitioning algorithms. 3 Conclusion. 5. TEMPORAL PLACEMENT. 1 Off-Line Temporal Placement. 2 On-Line Temporal Placement. 3 Managing the Device’s Free Space with Empty Rectangles. 4 Managing the Device’s Occupied Space. 5 Conclusion. 6. ON-LINE COMMUNICATION. 1 Direct Communication. 2 Communication Over Third Party. 3 Bus-based Communication. 4 Circuit Switching. 5 Network on Chip. 6 The Dynamic Network on Chip (DyNoC). 7 Routing Packets. 8 Analysis of efficiency. 9 DyNoC Implementation on FPGAs. 10 Conclusion. 7. PARTIAL RECONFIGURATION DESIGN. 1 Partial Reconfiguration on Virtex Devices. 2 Bitstream Manipulation with JBits. 3 The Modular Design Flow. 4 The Early Access Design Flow. 5 Creating partially reconfigurable designs. 6 Partial Reconfiguration using Handel-C Designs. 7 Platform design. 8 Enhancement in the Platform Design. 9 Conclusion. 8. SYSTEM ONA PROGRAMMABLE CHIP. 1 Introduction to SoPC. 2 Adaptive Multiprocessing on Chip. 3 Conclusion. 9. APPLICATIONS. 1 Pattern Matching. 2 Video Streaming. 3 Distributed Arithmetic. 4 Adaptive controller. 5 Adaptive Cryptographic Systems. 6 Software Defined Radio. 7 High Performance Computing. 8 Conclusion References. Appendices. A Hints to Labs. 1 Prerequisites. 2 Reorganization of the project Video8nonpr. B Party. C QuickPart-YTutorial.
£80.99
Springer Verlag, Singapore Compact and Fast Machine Learning Accelerator for
Book SynopsisThis book presents the latest techniques for machine learning based data analytics on IoT edge devices. A comprehensive literature review on neural network compression and machine learning accelerator is presented from both algorithm level optimization and hardware architecture optimization. Coverage focuses on shallow and deep neural network with real applications on smart buildings. The authors also discuss hardware architecture design with coverage focusing on both CMOS based computing systems and the new emerging Resistive Random-Access Memory (RRAM) based systems. Detailed case studies such as indoor positioning, energy management and intrusion detection are also presented for smart buildings.Table of ContentsComputing on Edge Devices in Internet-of-things (IoT).- The Rise of Machine Learning in IoT system.- Least-squares-solver for Shadow Neural Network.- Tensor-solver for Deep Neural Network.- Distributed-solver for Networked Neural Network.- Conclusion.
£98.99
Springer Verlag, Singapore Proceedings of International Conference on
Book SynopsisThis book gathers a collection of high-quality peer-reviewed research papers presented at First International Conference on Innovations in Software Architecture and Computational Systems (ISACS 2021), held at Guru Nanak Institute of Technology, Kolkata, India, during 2 – 3 April 2021. The book primarily focuses on developing artificial intelligence-based algorithms and methodologies for enabling intelligent hardware and software systems. This book brings together the latest findings on efficient technological solutions for developing intelligent and hybrid systems, intelligent software architecture, machine intelligence-based analytical tools and also smart sensors and networks. The prime focus is on solving technological problems using state-of-the-art research finding like fuzzy computing, evolutionary and hybrid frameworks, neuro-computing, etc., along with other AI-based computation platforms. The book offers a valuable resource for all undergraduate, postgraduate students and researchers interested in exploring solution frameworks for social good problems using artificial intelligence. Table of ContentsText to Image Classification using Attn: Gan With Dense Net Architecture.- Cyclone Detection and Forecasting Using Deep Neural Networks through Satellite Data.- An Improved Differential Evolution Scheme for Multilevel Image Thresholding Aided with Fuzzy Entropy.- Clustered Fault Repairing Architecture for 3D ICs using Redundant TSV.- The Implementation of Similarity Measures in Group Decision-Making Problems by Signless Laplacian Energy of an Intuitionistic Fuzzy Graph.- Uniform Grid Formation by Asynchronous Fat Robots.- A LSB Substitution based Steganography Technique using DNA Computing for Color Images.- An Approach of Safe Stock Prediction using Genetic Algorithm.- Suicide Ideation Detection in Online Social Networks: A Comparative Review.- An Improved K-Means Algorithm for Effective Medical Image Segmentation.- Breast Cancer Histopathological Image Classification using Convolutional Neural Networks.- A Framework for Predicting Placement of a Graduate using Machine Learning Techniques.
£179.99
Springer Verlag, Singapore Computer Architecture and Organization:
Book SynopsisIn today’s workplace, computer and cybersecurity professionals must understand both hardware and software to deploy effective security solutions. This book introduces readers to the fundamentals of computer architecture and organization for security, and provides them with both theoretical and practical solutions to design and implement secure computer systems. Offering an in-depth and innovative introduction to modern computer systems and patent-pending technologies in computer security, the text integrates design considerations with hands-on lessons learned to help practitioners design computer systems that are immune from attacks. Studying computer architecture and organization from a security perspective is a new area. There are many books on computer architectures and many others on computer security. However, books introducing computer architecture and organization with security as the main focus are still rare. This book addresses not only how to secure computer components (CPU, Memory, I/O, and network) but also how to secure data and the computer system as a whole. It also incorporates experiences from the author’s recent award-winning teaching and research. The book also introduces the latest technologies, such as trusted computing, RISC-V, QEMU, cache security, virtualization, cloud computing, IoT, and quantum computing, as well as other advanced computing topics into the classroom in order to close the gap in workforce development. The book is chiefly intended for undergraduate and graduate students in computer architecture and computer organization, as well as engineers, researchers, cybersecurity professionals, and middleware designers.Table of Contents
£47.49
Springer Verlag, Singapore Digital Design from the VLSI Perspective:
Book SynopsisThis volume covers digital design techniques, exercises and applications. The book discusses digital design and implementation in the context of VLSI and embedded system design. It covers basic digital design techniques to high speed design techniques. The contents also cover performance improvement, optimization concepts and design case studies. It includes pedagogical features such as design examples and illustrations. This book will be a useful guide for hardware engineers, logic design engineers, professionals and hobbyists looking to learn and use the digital design to develop VLSI based algorithms, architectures and products.Table of Contents
£42.74
Springer Verlag, Singapore Parallel and Distributed Computing, Applications
Book SynopsisThis book constitutes the refereed proceedings of the International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT) which was held in Jeju, Korea in August, 2023. The papers of this volume are organized in topical sections on wired and wireless communication systems, high dimensional data representation and processing, networks and information security, computing techniques for efficient networks design, electronic circuits for communication systems.Table of ContentsTrack 1. Networking and Architectures.- Track 2. Software Systems and Technologies.- Track 3. Algorithms and Applications.- Track 4. Security and Privacy
£123.49
Taylor & Francis ObjectOriented Engineering Building Engineering Systems Using Smalltalk80 Building Engineering Systems Usig Smalltalk80
a huge range and FREE tracked UK delivery on ALL orders.
£25.99
Taylor & Francis Ltd Building Enterprise IoT Applications
a huge range and FREE tracked UK delivery on ALL orders.
£175.75
Taylor & Francis Ltd The Virtual and the Real in Planning and Urban Design Perspectives Practices and Applications Routledge Research in Planning
a huge range and FREE tracked UK delivery on ALL orders.
£43.99
Taylor & Francis Organizational Network Analysis Auditing Intangible Resources Routledge Studies in Business Organizations and Networks
a huge range and FREE tracked UK delivery on ALL orders.
£128.25
Taylor & Francis Ltd Building Enterprise Systems with ODP
a huge range and FREE tracked UK delivery on ALL orders.
£56.99
Taylor & Francis Ltd The SIM Guide to Enterprise Architecture
a huge range and FREE tracked UK delivery on ALL orders.
£56.99
Taylor & Francis Ltd Embedded Linux System Design and Development
a huge range and FREE tracked UK delivery on ALL orders.
£54.14
Taylor & Francis Ltd Performance Evaluation and Benchmarking
a huge range and FREE tracked UK delivery on ALL orders.
£58.89
Taylor & Francis Ltd Scalable and Secure Internet Services and Architecture Chapman HallCRC Computer and Information Science Series
a huge range and FREE tracked UK delivery on ALL orders.
£56.99
Taylor & Francis Ltd Parallel Computing
a huge range and FREE tracked UK delivery on ALL orders.
£56.99
Taylor & Francis Voice Technology in Healthcare
a huge range and FREE tracked UK delivery on ALL orders.
£56.04
Taylor & Francis Ltd ComponentBased Systems
a huge range and FREE tracked UK delivery on ALL orders.
£47.49
Taylor & Francis Ltd Unmatched
a huge range and FREE tracked UK delivery on ALL orders.
£99.75
Taylor & Francis Ltd Systems Approach to the Design of Commercial Aircraft
a huge range and FREE tracked UK delivery on ALL orders.
£77.89
Taylor & Francis Ltd Wireless and Mobile Networking
Book SynopsisThere has been phenomenal uptake of wireless and mobile networking technologies in the past decades. Significant developments have taken place during this time making the wireless technology more affordable, effective, and reliable. This book explains the fundamental principles and protocols of key existing and emerging wireless networking technologies. The book begins with a review of the fundamentals of wireless communications. It covers the basic theories and terminologies of coding and modulation, which maps digital information to the underlying signal, as well as the models to capture the dynamics of wireless signal propagation in the environment. It provides in-depth coverage of the WiFi evolution covering both the mainstream WiFi, which operates in 2.4/5GHz with new versions targeting 6GHz, as well as some of the niche WiFi standards that operate outside the mainstream bands such as 802.11af in 700MHz TV bands, 802.11ah in 900MHz to connect the Internet of Things (IoT), and 8Table of ContentsPart I: Introduction 1. Wireless and Mobile Networking: From Past to Present Part II: Physical Layer Fundamentals 2. Wireless Coding and Modulation 3. Wireless Signal Propagation Part III: WiFi and Wireless Local Area Networks 4. WiFi Basics 5. Mainstream WiFi Standards 6. Niche WiFi Part IV: Cellular Networks 7. Cellular Networks 8. 5G Networks Part V: Internet of Things 9. Internet of Things 10.Bluetooth 11. LoRa and LoRaWAN Part VI: Next Frontiers in Wireless Networking 12. Artificial Intelligence-assisted Wireless Networking 13.Wireless Sensing 14.Aerial Wireless Networks
£137.75
Taylor & Francis Ltd Remote Delivery
Book SynopsisThis book records the author's years of experience in the software industry. In his own practices, the author has found that the distributed work pattern has become increasingly popular in more and more work environments, either between vendors and customers or between different teams inside a company. This means that all practitioners in the software industry need to adapt to this new way of communication and collaboration and get skilled enough to meet the greater challenges in integrating the distributed work pattern with agile software delivery. By centering on the difficulties in communication and collaboration between distributed teams, this book digs into the reasons why so many remote delivery projects end up anticlimactic and provides solutions for readers' reference. It also cites successful cases in promoting agile development in distributed teams, which has been a vexing problem for many software development companies. In addition, readers can find suggestions andTable of ContentsForeword 1: Taking Up Delivery Wholeheartedly. Foreword 2: Pursue Ideal Software Delivery. Preface. Chapter 1 Current Situation of Distributed Teams. Chapter 2 Communication between Distributed Teams. Chapter 3 Collaboration between Distributed Teams. Chapter 4 Application of Visualization. Chapter 5 Waste in Distributed Teams. Chapter 6 Self-Managed Offshore Teams. Chapter 7 Customer-Oriented Offshore Teams. Chapter 8 The Future of Distributed Teams. Postscript. References. Index.
£107.57
Taylor & Francis Ltd Iot and AI Technologies for Sustainable Living
a huge range and FREE tracked UK delivery on ALL orders.
£94.99
Taylor & Francis Ltd Edge Computing and CapabilityOriented Architecture
a huge range and FREE tracked UK delivery on ALL orders.
£75.99
Taylor & Francis Ltd DevicetoDevice based Proximity Service
a huge range and FREE tracked UK delivery on ALL orders.
£42.74
Taylor & Francis Handbook of SCADAControl Systems Security
a huge range and FREE tracked UK delivery on ALL orders.
£39.99
Taylor & Francis Ltd Computational Intelligence for Wireless Sensor Networks
a huge range and FREE tracked UK delivery on ALL orders.
£85.49
Taylor & Francis Ltd Secure Searchable Encryption and Data Management
a huge range and FREE tracked UK delivery on ALL orders.
£46.54
Taylor & Francis Ltd Artificial Intelligence for Business Optimization
a huge range and FREE tracked UK delivery on ALL orders.
£78.84
Taylor & Francis Ltd Toward Solving Complex Human Problems
978-0367638481
£50.34
Taylor & Francis Ltd Applied Soft Computing and Embedded System Applications in Solar Energy
a huge range and FREE tracked UK delivery on ALL orders.
£45.99
