Description
Book SynopsisThis book serves as a single-source reference to key machine learning (ML) applications and methods in digital and analog design and verification. Experts from academia and industry cover a wide range of the latest research on ML applications in electronic design automation (EDA), including analysis and optimization of digital design, analysis and optimization of analog design, as well as functional verification, FPGA and system level designs, design for manufacturing (DFM), and design space exploration. The authors also cover key ML methods such as classical ML, deep learning models such as convolutional neural networks (CNNs), graph neural networks (GNNs), generative adversarial networks (GANs) and optimization methods such as reinforcement learning (RL) and Bayesian optimization (BO). All of these topics are valuable to chip designers and EDA developers and researchers working in digital and analog designs and verification.
Table of Contents1. Introduction2. Analysis of Digital Design: Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning3. RouteNet: Routability Prediction for Mixed-size Designs Using Convolutional Neural Network4. High Performance Graph Convolutional networks with Applications in Testability Analysis5. MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification6. GRANNITE: Graph Neural Network Inference for Transferable Power Estimation7. Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation at Advanced Process Nodes8. Optimization of Digital Design: Chip Placement with Deep Reinforcement learning9. DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement10. TreeNet: Deep Point Cloud Embedding for Routing Tree Construction11. Asynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing12. Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes13. PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning14. GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization15. Analysis and Optimization of Analog Design: Machine Learning Techniques in Analog Layout Automation16. Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks17. ParaGraph: Layout parasitics and device parameter prediction using graph neural network18. GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learn19. Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization20. Logic and Physical Verification: Deep Predictive Coverage Collection/ Dynamically Optimized Test Generation Using Machine Learning21. Novelty-Driven Verification: Using Machine Learning to Identify Novel Stimuli and Close Coverage22. Using Machine Learning Clustering To Find Large Coverage Holes.- GAN-OPC: Mask optimization with lithography-guided generative adversarial nets.- Layout hotspot detection with feature tensor generation and deep biased learning.
