Description

Book Synopsis

This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs.

  • Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;
  • Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;
  • Enables designers to build hardware implementations that are resilient to a variety of side-channels.


Table of Contents

Introduction.- qTESLA.- CRYSTALS –Dilithium.- MQDSS.- SPHINCS.- Luov.- Falcon.- Picnic.- GeMSS.- Power, Performance, Area, and Security (PPAS) Comparison of the PQC Algorithms.- Conclusions.

Hardware Architectures for Post-Quantum Digital

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A Hardback by Deepraj Soni, Kanad Basu, Mohammed Nabeel

15 in stock


    View other formats and editions of Hardware Architectures for Post-Quantum Digital by Deepraj Soni

    Publisher: Springer Nature Switzerland AG
    Publication Date: 28/10/2020
    ISBN13: 9783030576813, 978-3030576813
    ISBN10: 3030576817

    Description

    Book Synopsis

    This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs.

    • Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;
    • Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;
    • Enables designers to build hardware implementations that are resilient to a variety of side-channels.


    Table of Contents

    Introduction.- qTESLA.- CRYSTALS –Dilithium.- MQDSS.- SPHINCS.- Luov.- Falcon.- Picnic.- GeMSS.- Power, Performance, Area, and Security (PPAS) Comparison of the PQC Algorithms.- Conclusions.

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