Description
Book SynopsisThis book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits.
Table of Contents1) Introduction to asynchronous circuit design2) "Preliminary considerations for asynchronous circuit design"3) "Completion detection schemes for asynchronous design style"4) Case Studies: Barrel shifter and binary adders5) "Generic Architecture of deterministic completion detection scheme"6) "Architecture optimization using deterministic completion detection"7) Simulations
