Description

This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits.

Completion Detection in Asynchronous Circuits: Toward Solution of Clock-Related Design Challenges

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Hardback by Pallavi Srivastava

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This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in... Read more

    Publisher: Springer International Publishing AG
    Publication Date: 10/11/2022
    ISBN13: 9783031183966, 978-3031183966
    ISBN10: 3031183967

    Number of Pages: 119

    Non Fiction , Technology, Engineering & Agriculture , Education

    Description

    This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits.

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