Description

Book Synopsis

Reconfigurable computing techniques and adaptive systems are some of the most promising architectures for microprocessors. Reconfigurable and Adaptive Computing: Theory and Applications explores the latest research activities on hardware architecture for reconfigurable and adaptive computing systems.

The first section of the book covers reconfigurable systems. The book presents a software and hardware codesign flow for coarse-grained systems-on-chip, a video watermarking algorithm for the H.264 standard, a solution for regular expressions matching systems, and a novel field programmable gate array (FPGA)-based acceleration solution with MapReduce framework on multiple hardware accelerators.

The second section discusses network-on-chip, including an implementation of a multiprocessor system-on-chip platform with shared memory access, end-to-end quality-of-service metrics modeling based on a multi-application environment in network-on-chip, a

Table of Contents

Reconfigurable Systems. Network-on-Chip. Systems Codesign.

Reconfigurable and Adaptive Computing

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A Hardback by Nadia Nedjah, Chao Wang

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    View other formats and editions of Reconfigurable and Adaptive Computing by Nadia Nedjah

    Publisher: Taylor & Francis Inc
    Publication Date: 1/1/2015 12:12:00 AM
    ISBN13: 9781498731751, 978-1498731751
    ISBN10: 1498731759

    Description

    Book Synopsis

    Reconfigurable computing techniques and adaptive systems are some of the most promising architectures for microprocessors. Reconfigurable and Adaptive Computing: Theory and Applications explores the latest research activities on hardware architecture for reconfigurable and adaptive computing systems.

    The first section of the book covers reconfigurable systems. The book presents a software and hardware codesign flow for coarse-grained systems-on-chip, a video watermarking algorithm for the H.264 standard, a solution for regular expressions matching systems, and a novel field programmable gate array (FPGA)-based acceleration solution with MapReduce framework on multiple hardware accelerators.

    The second section discusses network-on-chip, including an implementation of a multiprocessor system-on-chip platform with shared memory access, end-to-end quality-of-service metrics modeling based on a multi-application environment in network-on-chip, a

    Table of Contents

    Reconfigurable Systems. Network-on-Chip. Systems Codesign.

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