Description
Book SynopsisCMOS manufacturing environments are surrounded with symptoms that can indicate serious test, design, or reliability problems, which, in turn, can affect the financial as well as the engineering bottom line. This book will teach readers, including non-engineers involved in CMOS manufacture, to identify and remedy these causes.
Trade Review"...an essential text for practitioners in the CMOS industry or for students headed there…" (
IEEE Solid-State Circuits Society Newsletter, October 2004)
Table of ContentsForeword.
Preface.
PART I: CMOS FUNDAMENTALS.
1 Electrical Circuit Analysis.
1.1 Introduction.
1.2 Voltage and Current Laws.
1.3 Capacitors.
1.4 Diodes.
1.5 Summary.
Bibliography.
Exercises.
2 Semiconductor Physics.
2.1 Semiconductor Fundamentals.
2.2 Intrinsic and Extrinsic Semiconductors.
2.3 Carrier Transport in Semiconductors.
2.4 The pn Junction.
2.5 Biasing the pn Junction: I–V Characteristics.
2.6 Parasitics in the Diode.
2.7 Summary.
Bibliography.
Exercises.
3 MOSFET Transistors.
3.1 Principles of Operation: Long-Channel Transistors.
3.2 Threshold Voltage in MOS Transistors.
3.3 Parasitic Capacitors in MOS Transistors.
3.4 Device Scaling: Short-Channel MOS Transistors.
3.5 Summary.
References.
Exercises.
4 CMOS Basic Gates.
4.1 Introduction.
4.2 The CMOS Inverter.
4.3 NAND Gates.
4.4 NOR Gates.
4.5 CMOS Transmission Gates.
4.6 Summary.
Bibliography.
Exercises.
5 CMOS Basic Circuits.
5.1 Combinational logic.
5.2 Sequential Logic.
5.3 Input–Output (I/O) Circuitry.
5.4 Summary.
References.
Exercises.
PART II FAILURE MODES, DEFECTS, AND TESTING OF CMOS Ics.
6 Failure Mechanisms in CMOS IC Materials.
6.1 Introduction.
6.2 Materials Science of IC Metals.
6.3 Metal Failure Modes.
6.4 Oxide Failure Modes.
6.5 Conclusion.
Acknowledgments.
Bibliography.
Exercises.
7 Bridging Defects.
7.1 Introduction.
7.2 Bridges in ICs: Critical Resistance and Modeling.
7.3 Gate Oxide Shorts (GOS).
7.4 Bridges in Combinational Circuits.
7.5 Bridges in Sequential Circuits.
7.6 Bridging Faults and Technology Scaling.
7.7 Conclusion.
References.
Exercises.
8 Open Defects.
8.1 Introduction.
8.2 Modeling Floating Nodes in ICs.
8.3 Open Defect Classes.
8.4 Summary.
References.
Exercises.
9 Parametric Failures.
9.1 Introduction.
9.2 Intrinsic Parametric Failures.
9.3 Intrinsic Parametric Failure Impact on IC Behavior.
9.4 Extrinsic Parametric Failure.
9.5 Conclusion.
References.
Exercises.
10 Defect-Based Testing.
10.1 Introduction.
10.2 Digital IC Testing: The Basics.
10.3 Design for Test.
10.4 Defect-Based Testing (DBT).
10.5 Testing Nanometer ICs.
10.6 Conclusions.
Bibliography.
References.
Exercises.
Appendix A: Solutions to Self-Exercises.
A.1 Chapter 1.
A.2 Chapter 3.
A.3 Chapter 4.
A.4 Chapter 5.
A.5 Chapter 6.
A.6 Chapter 7.
A.8 Chapter 8.
A.8 Chapter 10.
Index.
About the Authors.
