Description
Book SynopsisWhich came first, the system or the chip? While integrated circuits enable technology for the modern information age, computing, communication, and network chips fuel it. As soon as the integration ability of modern semiconductor technology offers presents opportunities, issues in power consumption, reliability, and form-factor present challenges. The demands of emerging software applications can only be met with unique systems and chips. Drawing on contributors from academia, research, and industry, Unique Systems and Chips explores unique approaches to designing future computing and communication chips and systems.
The book focuses on specialized hardware and systems as opposed to general-purpose chips and systems. It covers early conception and simulation, mid-development, application, testing, and performance. The chapter authors introduce new ideas and innovations in unique aspects of chips and system design, then go on to provide in-depth analysis of these ideas. They expl
Table of ContentsAspects of the Cell Processor. TRIPS: A Unique ISA and Microarchitecture for Concurrency. Visualization by Subdivision: Two Applications for Future Graphics Platforms. A High Throughput Self-Timed FPGA Core Architecture. Evaluation of Delay Queues for a Ravenscar Hardware Kernel. Forward Error Correction for On-chip Interconnection Networks. Analysis of Wavefront Algorithms on Large-scale Two-level Heterogeneous Processing Systems. Measurement Based Power Phase Analysis of a Commercial Workload. Microarchitectural Characteristics and Implications of Alignment of Multiple Bioinformatics Sequences. Extended Analog Computers: A Unifying Paradigm for VLSI, Plastic, and Colloidal Computing Systems. Integrated High Performance Security in a x86 Processor. Alleviating Thermal Constraints while Maintaining Performance via Silicon-based On-Chip Optical Interconnects. Power Management in RAID Server Disk System Using Multiple Idle States. Micro-threaded Row and Column Operations in a DRAM Core. A processor with Dual Thread Execution Models.
