Description
Book SynopsisThis book focuses on FPGA EDA tools, the very foundation of FPGA technology. Instead of illustrating how to use them, this book dives into the tools themselves, revealing how these tools are being designed and how they may improve. Unlike other semiconductors, FPGA has a distinctive two-stage EDA system: chip design EDA and application design EDA.State-of-the-art algorithms, data models and design methodologies/standards are the main concerns of this book, and these will be very helpful for FPGA EDA engineers and researchers to obtain a bird’s eye view of this complicated knowledge system. In the chip design EDA part, full-custom and semicustom methodologies bring up ASIC-like EDA tools, and in the application design EDA side, typical topics including high-level synthesis, logic synthesis, physical implementation, bitstream configuration, etc., are well discussed.
Table of ContentsPart I: Introduction
Chapter1: Introduction
1.1 FPGA Hardware Brief Introduction
1.1.1 FPGA Concept
1.1.2 FPGA Hardware Evolution
1.1.3 FPGA Compares With Other Architectures
1.2 FPGA EDA Brief Introduction
1.2.1 FPGA EDA Concept .
1.2.2 FPGA chip design EDA
1.2.3 FPGA application design EDA
Part II: FPGA Chip Design EDA
Chapter2: Full-custom EDA
Chapter3: Semi-custom EDA
Part III: FPGA Application Design EDA Chapter4: FPGA Device Modelling
3.1 Device Info Description Level
3.2 Device Info Model Classification
3.3 Device Info Model Instances
3.4 Device Info Data Structure
Chapter5:FPGA Design Modelling
4.1 Design Info Description Level
4.2 Design Info Model Classification
4.3 Design Info Model Instances
4.4 Design Info Data Structure
Chapter6: High Level Synthesis (HLS)
5.1. HLS Concept( Introduction)
5.2. HLS Data Models and General Techniques
5.3. HLS Advanced Techniques
5.3.1 SDC-Based Modulo Scheduling
5.3.2 Dynamic Scheduling
5.3.3 Polyhedral Analysis and Optimization
5.4. Current Status and Future Outlook
5.4.1 Where is HLS Used Today
5.4.2 Comercial HLS Tools
5.4.3 Academic HLS Tools
5.4.4 What Are We Still Missing?
Chapter7: Logic Synthesis (LGS)
6.1 LGS Concept(Introduction)
6.2 Boolean Logic Fundamentals
6.2.1 Functional Representations
6.2.2 Directed-Acyclic-Graph(DAG) Boolean Networks
6.2.3 Formal methods
6.3 LGS Data Models and General Techniques
6.3.1 Data Models
6.3.2 Front End
6.3.3 Elaboration
-DAG aware methods
-Exact methods
-Sequential methods
6.3.4 Mapping
-Flow-based methods
-Cut-based methods
-Exact methods
6.3.5 Back End
6.4 LGS Advanced Techniques
6.4.1 Machine Learning
6.4.2 HPC Accelerated
6.5 Current Status and Future Outlook
6.4.2 Comercial LGS Tools
6.4.3 Academic LGS Tools
6.4.4 What Are We Still Missing?
Chapter8: Physical Implementation
7.1 Packing
7.2 Placement
7.3 Routing
7.4 Performance(Timing) Analysis
7.5 Power Analysis
7.6 Area(Resource) Analysis
7.7 Engine Fusion
Chapter9: Bitstream Configuration
8.1 Bitstream Generation
8.2 Bitstream Compression
8.3 Bitstream Encryption
8.4 Device Programming
8.5 Partial Reconfiguration
Chapter10: Generic GUI Framework .
Part IV: Summary and Outlook
Chapter11: Summary and Outlook
