{"product_id":"verilog-coding-for-logic-synthesis-9780471429760","title":"Verilog Coding for Logic Synthesis","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eVerilog is a Hardware Description Language (HDL) used to design and document electronic systems. Verilog HDL allows designers to virtually design systems without expending time or resources on physical models. It is the most widely used HDL with a user community of more than 50,000 active designers.\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003eTable of Figures.  \u003cp\u003eTable of Examples.\u003c\/p\u003e \u003cp\u003eList of Tables.\u003c\/p\u003e \u003cp\u003ePreface.\u003c\/p\u003e \u003cp\u003eAcknowledgments.\u003c\/p\u003e \u003cp\u003eTrademarks.\u003c\/p\u003e \u003cp\u003eIntroduction.\u003c\/p\u003e \u003cp\u003eAsic Design Flow.\u003c\/p\u003e \u003cp\u003eVerilog Coding.\u003c\/p\u003e \u003cp\u003eCoding Style: Best-Known Method for Synthesis.\u003c\/p\u003e \u003cp\u003eDesign Example of Programmable Timer.\u003c\/p\u003e \u003cp\u003eDesign Example of Programmable Logic Block for Peripheral Interface.\u003c\/p\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default Title","offer_id":49402591707479,"sku":"9780471429760","price":118.76,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9780471429760.jpg?v=1730480884","url":"https:\/\/bookcurl.com\/products\/verilog-coding-for-logic-synthesis-9780471429760","provider":"Book Curl","version":"1.0","type":"link"}