{"product_id":"three-dimensional-integration-of-semiconductors-processing-materials-and-applications-9783319186740","title":"Three-Dimensional Integration of Semiconductors:","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eThis book starts with background concerning three-dimensional integration - including their low energy consumption and high speed image processing - and then proceeds to how to construct them and which materials to use in particular situations. The book covers numerous applications, including next generation smart phones, driving assistance systems, capsule endoscopes, homing missiles, and many others. The book concludes with recent progress and developments in three dimensional packaging, as well as future prospects.\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003eChapter 1 - Research and Development History of Three Dimensional (3D) Integration Technology 1.1\tIntroduction 1.1.1\tThe International Technology Roadmap for Semiconductors 1.1.2\tThree-dimensional Integration Technology 1.2\tMotivation for 3D Integration Technology y 1.3\tResearch and Development History of 3D Integration Technology R\u0026amp;D History of 3D Packaging Technology 1.3.1\t3D Packaging Technology 1.3.2\tOrigin of the TSV Concept 1.3.3\tResearch and Development History of 3D Technology in Organizations 1.3.3.1\tJapan 1.3.3.2\tJapanese 3D Integration Technology Research and Development Project (Dream Chip)  1.3.3.3\tUSA 1.3.3.4\tEurope 1.3.3.5\tAsia 1.3.3.6\tInternational 1.4\tResearch and Development History of 3D Integration Technology for Applications 1.4.1\tCMOS Image Sensor and MEMS 1.4.2\tDRAM 1.4.3\t2.5D with Interposer  1.4.4\tOthers  Chapter 2- Recent Research and Development Activities of Three Dimensional (3D) Integration Technology 2.1\tRecent Announcement of Research and Development Activities 2.2\tDynamic Random-Access Memory (DRAM) 2.2.1\tThrough-Silicon Via (TSV) Technology for DRAM 2.2.2\tWide I\/O and Wide I\/O2 Mobile DRAM 2.3\tHybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) DRAM  2.3.1\tHybrid Memory Cube (HMC)High Bandwidth Memory (HBM) DRAM 2.3.2\tHigh Bandwidth Memory (HBM) DRAM 2.4\tFPGA and 2.5D 2.5\tOthers 2.6\tNew Energy and Industrial Technology Development Organization (NEDO) Japan 2.6.1\tNext Generation “Smart Device” Project 2.6.2\tBackground, Purpose and Target of “Smart Device” Project  Chapter 3- TSV Processes 3.1\tDeep Silicon Etching by Bosch process 3.1.1\tIntroduction 3.1.2\tBasic characteristics of the Bosch process 3.1.3\tBosch Etching Equipment for TSV 3.1.4\tConclusions 3.2\tHigh Rate Silicon-Via Etching and Basics of Sidewall Etch Reaction by Steady-State Etch Process 3.2.1\tIntroduction 3.2.2\tMERIE Process for TSV Application 3.2.2.1\tEffect of RF Frequency 3.2.2.2\tEffect of Pressure 3.2.2.3\tEffect of Oxygen Addition 3.2.3\tInvestigation of Sidewall Etch Reaction Induced by SF6\/O2 Plasma 3.2.3.1\tEffect of Oxygen Addition 3.2.3.2\tEffect of Temperature 3.2.3.3\tEffect of SiF4 Addition 3.2.4\tConclusion 3.3\tLow Temperature CVD Technology 3.3.1\tIntroduction 3.3.2\tCathode-Coupled PECVD (LS-CVD) 3.3.3\tLow Temperature SiO2 Deposition 3.3.3.1\tWafer Temperature During Low Temperature Deposition 3.3.3.2\tStep Coverage in Si Via Holes 3.3.3.3\tElectrical Characteristics of SiO2 Film Deposited at Low Temperature 3.3.3.4\tStress Control of SiO2 Film Deposited Using LS-CVD 3.3.4\tConclusion 3.4\tElectrodeposition for Via-Filling 3.4.1\tCu+ Ion as an Accelerant Additive of Copper Electrodeposition 3.4.2\tRelation between via Filling and Cu+ Ion by Periodical Reverse Current Waveform  3.4.3\tSimulation of Cu+ Ion Distribution inside the Via 3.4.4\tHigh Speed via Filling Electrodeposition by Other Organizations 3.4.5\tReduction of Thermal Expansion Coefficient of Electrodeposited Copper for TSV by Additive  Chapter 4 - Wafer Handling and Thinning Processes 4.1\tWafer Thinning Solution for TSV Devices 4.1.1\tIntroduction 4.1.2\tGeneral Thinning 4.1.3\tWafer Thinning for TSV devices 4.1.4\tTTV control 4.1.5\tSummary 4.2\tA Novel Via Middle TSV Thinning Technology by Si\/Cu Grinding and CMP 4.2.1\tIntroduction 4.2.2\tMethods 4.2.3\tResults and Discussion 4.2.3.1\tSi\/Cu Same Rate CMP (1st CMP) 4.2.3.2\tTSV Protrusion CMP (2nd CMP) 4.2.3.3\tPost CMP Cleaning after 2nd CMP 4.2.4\tConclusion 4.3\tTemporally Bonding 4.3.1\tBackground 4.3.2\tThe 3MTM Temporary Bonding Materials 4.3.3\tThe 3MTM Temporary Adhesive 4.3.4\tLaser Absorbing Layer 4.3.5\tThe Next Steps 4.4\tTemporary Bonding and Debonding for Through-Silicon Via (TSV) Processing 4.4.1\tIntroduction 4.4.2\tTemporary Bonding and Debonding Process 4.4.3\tDebonding Method 4.4.4\tFunctions and Performance Requirements for Temporary Bonding Device 4.4.5\tAbility and Performance Requirements for Debonding Devices 4.4.6\tTokyo Electron’s Temporary Bonder and Debonder Device Concept and Lineup 4.4.7\tFuture Outlook  Chapter 5- Wafer and Die Bonding Processes 5.1\tPermanent Wafer Bonding 5.1.1\tIntroduction 5.1.2\tLow Temperature or Room Temperature Wafer Direct Bonding Method and Application 5.1.2.1\tFusion Bonding 5.1.2.2\tSurface Activated Bonding 5.1.2.3\tAnodic Bonding 5.1.2.4\tCu2Cu\/Oxide Hybrid bonding 5.1.2.5\tConclusion of Low Temperature or Room Temperature Wafer Direct Bonding Methods and Their Applications 5.1.2.6\tFuture Outlook for Bonding Application Using Low Temperature or Normal Room Temperature Wafer Direct Bonding Methods 5.1.3\tRequests Made to Equipment Makers and Initiatives Regarding Low Temperature or Room Temperature Wafer Direct Bonding Methods 5.1.3.1\tPost BAA 5.1.3.2\tScaling 5.1.3.3\tDistortion 5.1.3.4\tBonding strength 5.1.3.5\tVoid 5.1.4\tTokyo Electron Initiatives 5.1.5\tConclusion 5.2\tUnderfill Materials 5.2.1\tTechnical Trend for Three Dimensional Integration Packages and Underfill Materials 5.2.2\tRequirements for Underfill Materials 5.2.2.1\tRequirements for CUF and Material Technology Trend 5.2.2.2\tRequirements for NCP and Material Technology Trend 5.2.3 Application to CUF between the Stacked Chips 5.3\tNon-Conductive Films 5.3.1\tIntroduction 5.3.2\tRequired Material Feature from Bonding Process 5.3.3\tVoiding Issue in NC 5.3.4\tHigh Through Put NCF-TCB  Chapter 6- Metrology and Inspection 6.1\tPrinciples of Spectroscopic Reflectometry 6.1.1\tIntroduction 6.1.2\tMeasurement 6.1.3\tSetup  6.1.4\tAnalysis 6.1.5\tConclusion 6.2\tLow Coherence Interferometry for 3D-IC TSV 6.2.1\tOptical Measurement of Topographies and Thicknesses 6.2.1.1\t3D-IC TSV Needs Tomography 6.2.1.2\tTomography with Low Coherence Interferometry 6.2.2\tTheory of Optical Coherence Tomography 6.2.2.1\tBasic Principle 6.2.2.2\tTime Domain OCT 6.2.2.3\tFourier Domain OCT 6.2.3\tPractical Considerations 6.2.4\tConclusion 6.3\tSilicon and Glue Thickness Measurement for Grinding 6.3.1\tIntroduction 6.3.2\tTSV Wafer Manufacturing Method and Challenges of Grinding 6.3.3\tFeatures of BGM300 6.3.4\tVerifying BGM300 Measurement Results 6.3.5\tMeasurement after Grinding 6.3.6\tOptimized wafer Grinding Based on Via Height Information from BGM300 6.3.7\tConclusion 6.4\t3D X-ray Microscopy Technology for Non-Destructive Analysis of Through-Silicon Vias 6.4.1\tIntroduction 6.4.2\tFundamentals of X-ray Microscopy 6.4.2.1\tPhysics of X-ray Imaging 6.4.2.2\t3D X-ray Microscopy 6.4.3\tApplications for TSV Process Development 6.4.4\tApplications for TSV Failure Analysis 6.4.5\tSummary 6.5\tWafer Warpage and Local Distortion Measurement 6.5.1\tIntroduction 6.5.2\tBasic Functions of WDM300 6.5.3\tMeasurement and Analysis of Local Deformations 6.5.4\tApplication 6.5.5\tSummary  Chapter 7 - TSV Characteristics and Reliability: Impact of 3D Integration Processes on Device Reliability 7.1\tIntroduction 7.2\tImpact of Cu Contamination on Device Reliabilities in Thinned 3D-IC Chip 7.2.1\tImpact of Cu Diffusion at Backside Surface in Thinned 3D-IC Chip 7.2.1.1\tEffect of Intrinsic Gettering (IG) layer 7.2.1.2\tEffect of Extrinsic Gettering (EG) layer 7.2.2\tImpact of Cu Diffusion from Cu Via 7.2.2.1\tEffect of the Barrier Thickness and the Scallop Roughness 7.2.2.2\tEffect of the Annealing Temperature 7.2.2.3\tKeep Out Zone (KOZ) Characterization by Cu Diffusion from Cu Via 7.3\tImpact of Mechanical Stress\/Strain on Device Reliability in Stacked IC 7.3.1\tMicro-Bump Induced Local Stress in Stacked IC 7.3.2\tSi Mechanical Strength Reduction by Thinning  7.4\tImpact of 3D Integration Process on DRAM Retention Characteristics 7.4.1\tImpact of Mechanical Strength on Retention Characteristics in Thinn DRAM Chip 7.4.2\tImpact of Cu Contamination on Memory Retention Characteristics in DRAM Chip  Chapter 8 - Trends in 3D Integrated Circuit (3D-IC) Testing Technology 8.1\tCrucial Issues and Key Technologies for 3D-IC Testing 8.2\tResearch Trends in Pre-bond Test for 3D-IC 8.3\tResearch Trends in Post-bond Test for 3D-IC 8.4\tResearch Trends in Automatic Test Pattern Generator (ATPG) and Test Scheduling for TSVs in 3D-IC 8.5\tAn Accurate Resistance Measuring Method for TSVs in 3D-IC 8.5.1\tBackground of Our Study 8.5.2\tProblems of Conventional Analog Boundary-Scan for TSV Resistance Measurement 8.5.2.1\tAnalog Boundary-Scan 8.5.2.2\tStandard resistance measuring method by 1149.4  8.5.2.3\tProblems of conventional Analog Boundary-Scan for TSV resistance measuring 8.5.3\tProposed Measuring Method 8.5.3.1\tFloating Measurement method 8.5.3.2\tComplete isolation of the current path and the voltage path 8.5.3.3\tSegmenting the internal analog BUS (AB1, AB2) 8.5.4\tSummary 8.6\tDelay Measurement Circuits for Detecting TSV Delay Faults 8.6.1\tApplication of Time-to-Digital Converter Embedded in Boundary-Scan for 3D-IC Testing 8.6.2\tDelay Measurement Circuit Using the Vernier Delay Line 8.6.3\tEstimation of Defect Size Detectable by the Test Method 8.6.4\tSummary 8.7\tElectrical Interconnect Tests of Open Defects in a 3D-IC with a Built-in Supply Current Test Circuit 8.7.1\tElectrical Tests with a Built-in Supply Current Test Circuit 8.7.2\tExperimental Evaluation of Our Electrical Test Method 8.7.3\tSummary  Chapter 9 - Dream Chip Project at ASET 9.1\tOverview of Japanese 3D Integration Technology R\u0026amp;D Project (Dream Chip) 9.2\tThermal Management and Chip Stacking Technology 9.2.1\tBackground 9.2.2\tChip Stacking\/Joining Technology 9.2.2.1\tMetal Bump Materials and Structure 9.2.2.2\tReliability Study of Micro Bump 9.2.2.3\tElectro Migration Test to Understand Current Density of Micro Bump Joint 9.2.2.4\tFlip Chip Bonding Density Towards 10 μm Connection Bump Pitch 9.2.2.5\tStack and Gang Bonding 9.2.2.6\tNon-destructive Inspection Technologies of Micro Joint 9.2.3\tThermal Management Study 9.2.3.1\tEvaluation Technology of 3D Integrated Chip Stack 9.2.3.2\tTV200 Measurement Result and Correlation with Simulation 9.2.3.3\tThermal Conductivity Anisotropy Induced by Cu TSV 9.2.4\tDevelopment of Automobile Drive Assistance Camera 9.2.4.1\tDevelopment of Integration Process 9.2.4.2\tDevelopment of Cooling System for Automobile Drive Assistance Camera 9.2.5\tSummery 9.3\tThin Wafer Technology 9.3.1\tBack Ground of Wafer Thinning Technology 9.3.2\tIssues of Wafer Thinning 9.3.3\tUltrathin Wafer Thinning Process 9.3.3.1\tWafer Support System (WSS) 9.3.3.2\tThermal Resistance of the Resin Used for WSS Temporary Bonding 9.3.3.3\tDicing Technology of Thin Chip 9.3.3.4\tDie Pick-up Technology of Thin Chip 9.3.3.5\tThin Wafer Processing Technique in the Wafer Stacking Process 9.3.4\tIssues on Wafer Thinning to Prevent Device Characteristics Change and Metal Contamination 9.3.4.1\tEvaluation Method of a Crystal Defect and Metal Pollution in the Thin Wafer 9.3.4.2\tBackside Grinding Methods and Their EG Effect 9.3.4.3\tElectrical Characteristics Deviation by Mechanical Stress 9.3.5\tStandardization 9.3.6\tSummary 9.4\t3D Integration Technology 9.4.1\tBackground and Scope 9.4.2\tC2C Process 9.4.2.1\tC2C Integration Overview 9.4.2.2\tC2C Integration Results 9.4.3\tW2W Process 9.4.3.1\tW2W Integration Overview 9.4.3.2\tWafer Bonding Technology 9.4.3.3\tW2W Integration Results 9.4.4\tSummary 9.5\tUltra-wide Bus 3D-System-in Package (3D-SiP) Technology 9.5.1\tBackground 9.5.2\tThe Test Vehicle Fabrication 9.5.3\tEvaluation 9.5.4\tSummary 9.6\tMixed Signal (Digital and Analog) 3D Integration Technology for Automotive Application 9.6.1\tIntroduction 9.6.2\tChallenges 9.6.3\tResult of Basic Technology Development on Mixed-Signal 3D Integration Technology 9.6.3.1\tBasic Technology Development on 3D Integrated Imaging Sensor Module for In-Vehicle 9.6.3.2\tRealization of Mixed-Signal (CIS\/CDS\/ADC\/IF) Integrated Structure by TSV Connection 9.6.3.3\tDevelopment of Si Interposer Which Allotted TSV Type Decoupling Capacitor 9.6.3.4\tA Trial production and Evaluation of Car Drive Assist Image Processing System for Cars 9.6.4\tConclusion 9.7\tHeterogeneous 3D Integration Technology for Radio Frequency Micro Electro Mechanical Systems RF MEMS (RF MEMS) 9.7.1\tBackground and Issues 9.7.2\tDevelopment Result 9.7.2.1\tStructure of 3D integration RF Module 9.7.2.2\tMEMS Tunable Filter 9.7.2.3\tMEMS Switch 9.7.2.4\tCMOS Driving IC 9.7.2.5\t3D Integration of Tunable Filter Module 9.7.2.6\tRF and Tuning Performances of the Fabricated 3D Tunable Filter Module 9.7.3\tSummary","brand":"Springer International Publishing AG","offers":[{"title":"Default Title","offer_id":51043864772951,"sku":"9783319186740","price":80.99,"currency_code":"GBP","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9783319186740.jpg?v=1750959750","url":"https:\/\/bookcurl.com\/products\/three-dimensional-integration-of-semiconductors-processing-materials-and-applications-9783319186740","provider":"Book Curl","version":"1.0","type":"link"}