{"product_id":"realtime-embedded-systems-9781118116173","title":"RealTime Embedded Systems","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eOffering comprehensive coverage of the convergence of real-time embedded systems scheduling, resource access control, software design and development, and high-level system modeling, analysis and verification     Following an introductory overview, Dr.\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003ePreface xiii\u003c\/p\u003e \u003cp\u003eBook Layout xv\u003c\/p\u003e \u003cp\u003eAcknowledgments xvii\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Introduction to Real-Time Embedded Systems 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Real-Time Embedded Systems 1\u003c\/p\u003e \u003cp\u003e1.2 Example: Automobile Antilock Braking System 3\u003c\/p\u003e \u003cp\u003e1.2.1 Slip Rate and Brake Force 3\u003c\/p\u003e \u003cp\u003e1.2.2 ABS Components 4\u003c\/p\u003e \u003cp\u003e1.2.2.1 Sensors 4\u003c\/p\u003e \u003cp\u003e1.2.2.2 Valves and Pumps 5\u003c\/p\u003e \u003cp\u003e1.2.2.3 Electrical Control Unit 7\u003c\/p\u003e \u003cp\u003e1.2.3 ABS Control 8\u003c\/p\u003e \u003cp\u003e1.3 Real-Time Embedded System Characteristics 10\u003c\/p\u003e \u003cp\u003e1.3.1 System Structure 10\u003c\/p\u003e \u003cp\u003e1.3.2 Real-Time Response 10\u003c\/p\u003e \u003cp\u003e1.3.3 Highly Constrained Environments 11\u003c\/p\u003e \u003cp\u003e1.3.4 Concurrency 12\u003c\/p\u003e \u003cp\u003e1.3.5 Predictability 12\u003c\/p\u003e \u003cp\u003e1.3.6 Safety and Reliability 13\u003c\/p\u003e \u003cp\u003e1.4 Hard and Soft Real-Time Embedded Systems 13\u003c\/p\u003e \u003cp\u003eExercises 14\u003c\/p\u003e \u003cp\u003eSuggestions for Reading 15\u003c\/p\u003e \u003cp\u003eReferences 15\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Hardware Components 17\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Processors 17\u003c\/p\u003e \u003cp\u003e2.1.1 Microprocessors 17\u003c\/p\u003e \u003cp\u003e2.1.2 Microcontrollers 19\u003c\/p\u003e \u003cp\u003e2.1.3 Application-Specific Integrated Circuits (ASICs) 19\u003c\/p\u003e \u003cp\u003e2.1.4 Field-Programmable Gate Arrays (FPGAs) 19\u003c\/p\u003e \u003cp\u003e2.1.5 Digital Signal Processors (DSPs) 20\u003c\/p\u003e \u003cp\u003e2.1.6 Application-Specific Instruction Set Processors (ASIPs) 20\u003c\/p\u003e \u003cp\u003e2.1.7 Multicore Processors 20\u003c\/p\u003e \u003cp\u003e2.1.8 Von Neumann Architecture and Harvard Architecture 21\u003c\/p\u003e \u003cp\u003e2.1.9 Complex Instruction Set Computing and Reduced Instruction Set Computing 22\u003c\/p\u003e \u003cp\u003e2.2 Memory and Cache 23\u003c\/p\u003e \u003cp\u003e2.2.1 Read-Only Memory (ROM) 23\u003c\/p\u003e \u003cp\u003e2.2.2 Random-Access Memory (RAM) 24\u003c\/p\u003e \u003cp\u003e2.2.3 Cache Memory 24\u003c\/p\u003e \u003cp\u003e2.3 I\/O Interfaces 26\u003c\/p\u003e \u003cp\u003e2.4 Sensors and Actuators 27\u003c\/p\u003e \u003cp\u003e2.5 Timers and Counters 29\u003c\/p\u003e \u003cp\u003eExercises 30\u003c\/p\u003e \u003cp\u003eSuggestions for Reading 31\u003c\/p\u003e \u003cp\u003eReferences 31\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 Real-Time Operating Systems 33\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Main Functions of General-Purpose Operating Systems 33\u003c\/p\u003e \u003cp\u003e3.1.1 Process Management 34\u003c\/p\u003e \u003cp\u003e3.1.2 Memory Management 36\u003c\/p\u003e \u003cp\u003e3.1.3 Interrupts Management 39\u003c\/p\u003e \u003cp\u003e3.1.4 Multitasking 39\u003c\/p\u003e \u003cp\u003e3.1.5 File System Management 39\u003c\/p\u003e \u003cp\u003e3.1.6 I\/O Management 41\u003c\/p\u003e \u003cp\u003e3.2 Characteristics of RTOS Kernels 42\u003c\/p\u003e \u003cp\u003e3.2.1 Clocks and Timers 42\u003c\/p\u003e \u003cp\u003e3.2.2 Priority Scheduling 44\u003c\/p\u003e \u003cp\u003e3.2.3 Intertask Communication and Resource Sharing 45\u003c\/p\u003e \u003cp\u003e3.2.3.1 Real-Time Signals 45\u003c\/p\u003e \u003cp\u003e3.2.3.2 Semaphores 46\u003c\/p\u003e \u003cp\u003e3.2.3.3 Message Passing 46\u003c\/p\u003e \u003cp\u003e3.2.3.4 Shared Memory 46\u003c\/p\u003e \u003cp\u003e3.2.4 Asynchronous I\/O 47\u003c\/p\u003e \u003cp\u003e3.2.5 Memory Locking 47\u003c\/p\u003e \u003cp\u003e3.3 RTOS Examples 48\u003c\/p\u003e \u003cp\u003e3.3.1 LynxOS 48\u003c\/p\u003e \u003cp\u003e3.3.2 OSE 49\u003c\/p\u003e \u003cp\u003e3.3.3 QNX 49\u003c\/p\u003e \u003cp\u003e3.3.4 VxWorks 49\u003c\/p\u003e \u003cp\u003e3.3.5 Windows Embedded Compact 50\u003c\/p\u003e \u003cp\u003eExercises 50\u003c\/p\u003e \u003cp\u003eSuggestions for Reading 52\u003c\/p\u003e \u003cp\u003eReferences 52\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Task Scheduling 53\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Tasks 53\u003c\/p\u003e \u003cp\u003e4.1.1 Task Specification 54\u003c\/p\u003e \u003cp\u003e4.1.2 Task States 56\u003c\/p\u003e \u003cp\u003e4.1.3 Precedence Constraints 58\u003c\/p\u003e \u003cp\u003e4.1.4 Task Assignment and Scheduling 59\u003c\/p\u003e \u003cp\u003e4.2 Clock-Driven Scheduling 59\u003c\/p\u003e \u003cp\u003e4.2.1 Structured Clock-Driven Scheduling 62\u003c\/p\u003e \u003cp\u003e4.2.1.1 Frames 62\u003c\/p\u003e \u003cp\u003e4.2.1.2 Task Slicing 65\u003c\/p\u003e \u003cp\u003e4.2.2 Scheduling Aperiodic Tasks 66\u003c\/p\u003e \u003cp\u003e4.2.3 Scheduling Sporadic Tasks 68\u003c\/p\u003e \u003cp\u003e4.3 Round-Robin Approach 69\u003c\/p\u003e \u003cp\u003e4.4 Priority-Driven Scheduling Algorithms 70\u003c\/p\u003e \u003cp\u003e4.4.1 Fixed-Priority Algorithms 70\u003c\/p\u003e \u003cp\u003e4.4.1.1 Schedulability Test Based on Time Demand Analysis 72\u003c\/p\u003e \u003cp\u003e4.4.1.2 Deadline-Monotonic Algorithm 76\u003c\/p\u003e \u003cp\u003e4.4.2 Dynamic-Priority Algorithms 76\u003c\/p\u003e \u003cp\u003e4.4.2.1 Earliest-Deadline-First (EDF) Algorithm 76\u003c\/p\u003e \u003cp\u003e4.4.2.2 Optimality of EDF 78\u003c\/p\u003e \u003cp\u003e4.4.3 Priority-Driven Scheduling of Aperiodic and Sporadic Tasks 82\u003c\/p\u003e \u003cp\u003e4.4.3.1 Scheduling of Aperiodic Tasks 82\u003c\/p\u003e \u003cp\u003e4.4.3.2 Scheduling of Sporadic Tasks 85\u003c\/p\u003e \u003cp\u003e4.4.4 Practical Factors 85\u003c\/p\u003e \u003cp\u003e4.4.4.1 Nonpreemptivity 85\u003c\/p\u003e \u003cp\u003e4.4.4.2 Self-Suspension 86\u003c\/p\u003e \u003cp\u003e4.4.4.3 Context Switches 87\u003c\/p\u003e \u003cp\u003e4.4.4.4 Schedulability Test 87\u003c\/p\u003e \u003cp\u003e4.5 Task Assignment 89\u003c\/p\u003e \u003cp\u003e4.5.1 Bin-Packing Algorithms 89\u003c\/p\u003e \u003cp\u003e4.5.1.1 First-Fit Algorithm 90\u003c\/p\u003e \u003cp\u003e4.5.1.2 First-Fit Decreasing Algorithm 91\u003c\/p\u003e \u003cp\u003e4.5.1.3 Rate-Monotonic First-Fit (RMFF) Algorithm 91\u003c\/p\u003e \u003cp\u003e4.5.2 Assignment with Communication Cost 92\u003c\/p\u003e \u003cp\u003eExercises 94\u003c\/p\u003e \u003cp\u003eSuggestions for Reading 97\u003c\/p\u003e \u003cp\u003eReferences 97\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 Resource Sharing and Access Control 99\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Resource Sharing 99\u003c\/p\u003e \u003cp\u003e5.1.1 Resource Operation 100\u003c\/p\u003e \u003cp\u003e5.1.2 Resource Requirement Specification 100\u003c\/p\u003e \u003cp\u003e5.1.3 Priority Inversion and Deadlocks 101\u003c\/p\u003e \u003cp\u003e5.1.4 Resource Access Control 103\u003c\/p\u003e \u003cp\u003e5.2 Nonpreemptive Critical Section Protocol 103\u003c\/p\u003e \u003cp\u003e5.3 Priority Inheritance Protocol 106\u003c\/p\u003e \u003cp\u003e5.3.1 Rules of Priority Inheritance Protocol 106\u003c\/p\u003e \u003cp\u003e5.3.2 Properties of Priority Inheritance Protocol 109\u003c\/p\u003e \u003cp\u003e5.4 Priority Ceiling Protocol 111\u003c\/p\u003e \u003cp\u003e5.4.1 Rules of Priority Ceiling Protocol 112\u003c\/p\u003e \u003cp\u003e5.4.2 Properties of Priority Ceiling Protocol 114\u003c\/p\u003e \u003cp\u003e5.4.3 Worst-Case Blocking Time 116\u003c\/p\u003e \u003cp\u003e5.5 Stack-Sharing Priority Ceiling Protocol 119\u003c\/p\u003e \u003cp\u003e5.5.1 Rules of Stack-Sharing Priority Ceiling Protocol 119\u003c\/p\u003e \u003cp\u003e5.5.2 Properties of Stack-Sharing Priority Ceiling Protocol 121\u003c\/p\u003e \u003cp\u003eExercises 122\u003c\/p\u003e \u003cp\u003eSuggestion for Reading 125\u003c\/p\u003e \u003cp\u003eReferences 125\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Concurrent Programming 127\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Introduction 127\u003c\/p\u003e \u003cp\u003e6.2 POSIX Threads 128\u003c\/p\u003e \u003cp\u003e6.3 Synchronization Primitives 133\u003c\/p\u003e \u003cp\u003e6.3.1 Race Conditions and Critical Sections 133\u003c\/p\u003e \u003cp\u003e6.3.2 Mutex 134\u003c\/p\u003e \u003cp\u003e6.3.3 Condition Variables 137\u003c\/p\u003e \u003cp\u003e6.3.4 Semaphores 142\u003c\/p\u003e \u003cp\u003e6.4 Communication among Tasks 148\u003c\/p\u003e \u003cp\u003e6.4.1 Message Queues 149\u003c\/p\u003e \u003cp\u003e6.4.2 Shared Memory 155\u003c\/p\u003e \u003cp\u003e6.4.3 Shared Memory Protection 157\u003c\/p\u003e \u003cp\u003e6.5 Real-Time Facilities 162\u003c\/p\u003e \u003cp\u003e6.5.1 Real-Time Signals 162\u003c\/p\u003e \u003cp\u003e6.5.1.1 Blocking Signals 163\u003c\/p\u003e \u003cp\u003e6.5.1.2 Dealing with Signals 164\u003c\/p\u003e \u003cp\u003e6.5.2 Timers 165\u003c\/p\u003e \u003cp\u003e6.5.3 Implement Periodic Tasks 169\u003c\/p\u003e \u003cp\u003e6.5.3.1 Using sleep() Function 169\u003c\/p\u003e \u003cp\u003e6.5.3.2 Using Timers 172\u003c\/p\u003e \u003cp\u003e6.5.4 Implement an Application with Multiple Periodic Tasks 173\u003c\/p\u003e \u003cp\u003eExercises 173\u003c\/p\u003e \u003cp\u003eSuggestions for Reading 177\u003c\/p\u003e \u003cp\u003eReferences 177\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Finite-State Machines 179\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Finite State Machine Basics 179\u003c\/p\u003e \u003cp\u003e7.2 Deterministic Finite Automation (DFA) 181\u003c\/p\u003e \u003cp\u003e7.2.1 Moore Machines 182\u003c\/p\u003e \u003cp\u003e7.2.2 Mealy Machines 184\u003c\/p\u003e \u003cp\u003e7.3 Nondeterministic Finite Automation 188\u003c\/p\u003e \u003cp\u003e7.4 Programming Finite-State Machines 188\u003c\/p\u003e \u003cp\u003eExercises 191\u003c\/p\u003e \u003cp\u003eSuggestions for Reading 194\u003c\/p\u003e \u003cp\u003eReferences 195\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 UML State Machines 197\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 States 198\u003c\/p\u003e \u003cp\u003e8.2 Transitions 200\u003c\/p\u003e \u003cp\u003e8.3 Events 201\u003c\/p\u003e \u003cp\u003e8.4 Composite States 202\u003c\/p\u003e \u003cp\u003e8.4.1 Hierarchy 203\u003c\/p\u003e \u003cp\u003e8.4.2 Orthogonality 205\u003c\/p\u003e \u003cp\u003e8.4.3 Submachine States 206\u003c\/p\u003e \u003cp\u003e8.5 Pseudostates 206\u003c\/p\u003e \u003cp\u003e8.5.1 History Pseudostates 206\u003c\/p\u003e \u003cp\u003e8.5.2 Entry and Exit Points 208\u003c\/p\u003e \u003cp\u003e8.5.3 Fork and Join Pseudostates 210\u003c\/p\u003e \u003cp\u003e8.5.4 Terminate Pseudostates 210\u003c\/p\u003e \u003cp\u003e8.6 UML State Machine of Antilock Braking System 211\u003c\/p\u003e \u003cp\u003eExercises 215\u003c\/p\u003e \u003cp\u003eSuggestions for Reading 217\u003c\/p\u003e \u003cp\u003eReferences 217\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 Timed Petri Nets 219\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Petri Net Definition 219\u003c\/p\u003e \u003cp\u003e9.1.1 Transition Firing 221\u003c\/p\u003e \u003cp\u003e9.1.2 Modeling Power 222\u003c\/p\u003e \u003cp\u003e9.2 Petri Net Properties 225\u003c\/p\u003e \u003cp\u003e9.2.1 Behavioral Properties 225\u003c\/p\u003e \u003cp\u003e9.2.1.1 Reachability 225\u003c\/p\u003e \u003cp\u003e9.2.1.2 ;; Markings 226\u003c\/p\u003e \u003cp\u003e9.2.1.3 Reachability Analysis Algorithm 227\u003c\/p\u003e \u003cp\u003e9.2.1.4 Boundedness and Safeness 229\u003c\/p\u003e \u003cp\u003e9.2.1.5 Liveness 229\u003c\/p\u003e \u003cp\u003e9.2.2 Structural Properties 230\u003c\/p\u003e \u003cp\u003e9.2.2.1 T-Invariants and S-Invariants 230\u003c\/p\u003e \u003cp\u003e9.2.2.2 Siphons and Traps 233\u003c\/p\u003e \u003cp\u003e9.3 Timed Petri Nets 234\u003c\/p\u003e \u003cp\u003e9.3.1 Deterministic Timed Petri Nets 234\u003c\/p\u003e \u003cp\u003e9.3.1.1 Performance Evaluation Based on DTPNs 237\u003c\/p\u003e \u003cp\u003e9.3.2 Time Petri Nets 240\u003c\/p\u003e \u003cp\u003e9.3.2.1 States in a Time Petri Net 241\u003c\/p\u003e \u003cp\u003e9.3.2.2 Enabling and Firing Conditions of Transitions 242\u003c\/p\u003e \u003cp\u003e9.3.2.3 Firing Rules 243\u003c\/p\u003e \u003cp\u003eExercises 244\u003c\/p\u003e \u003cp\u003eSuggestions for Reading 250\u003c\/p\u003e \u003cp\u003eReferences 251\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 Model Checking 253\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Introduction to Model Checking 253\u003c\/p\u003e \u003cp\u003e10.2 Temporal Logic 254\u003c\/p\u003e \u003cp\u003e10.2.1 Linear Temporal Logic 256\u003c\/p\u003e \u003cp\u003e10.2.1.1 Syntax of LTL 256\u003c\/p\u003e \u003cp\u003e10.2.1.2 Parse Trees for LTL Formulas 257\u003c\/p\u003e \u003cp\u003e10.2.1.3 Semantics of LTL 258\u003c\/p\u003e \u003cp\u003e10.2.1.4 Equivalencies of LTL Formulas 262\u003c\/p\u003e \u003cp\u003e10.2.1.5 System Property Specification 263\u003c\/p\u003e \u003cp\u003e10.2.2 Computation Tree logic 264\u003c\/p\u003e \u003cp\u003e10.2.2.1 Syntax of CTL 264\u003c\/p\u003e \u003cp\u003e10.2.2.2 Semantics of CTL 265\u003c\/p\u003e \u003cp\u003e10.2.2.3 Equivalencies of CTL Formulas 268\u003c\/p\u003e \u003cp\u003e10.2.3 LTL versus CTL 268\u003c\/p\u003e \u003cp\u003e10.3 The NuSMV Model Checking Tool 269\u003c\/p\u003e \u003cp\u003e10.3.1 Description Language 269\u003c\/p\u003e \u003cp\u003e10.3.1.1 Single-Module SMV Program 269\u003c\/p\u003e \u003cp\u003e10.3.1.2 Multimodule SMV Program 271\u003c\/p\u003e \u003cp\u003e10.3.1.3 Asynchronous Systems 273\u003c\/p\u003e \u003cp\u003e10.3.2 Specifications 274\u003c\/p\u003e \u003cp\u003e10.3.3 Running NuSMV 275\u003c\/p\u003e \u003cp\u003e10.4 Real-Time Computation Tree Logic 279\u003c\/p\u003e \u003cp\u003eExercises 285\u003c\/p\u003e \u003cp\u003eSuggestions for Reading 290\u003c\/p\u003e \u003cp\u003eReferences 290\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 Practical Issues 293\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Software Reliability 293\u003c\/p\u003e \u003cp\u003e11.1.1 Software Faults 293\u003c\/p\u003e \u003cp\u003e11.1.2 ReliabilityMeasurement 294\u003c\/p\u003e \u003cp\u003e11.1.3 Improving Software Reliability 295\u003c\/p\u003e \u003cp\u003e11.1.3.1 Fault Avoidance 295\u003c\/p\u003e \u003cp\u003e11.1.3.2 Fault Removal 295\u003c\/p\u003e \u003cp\u003e11.1.3.3 Fault Tolerance 295\u003c\/p\u003e \u003cp\u003e11.1.3.4 Fault Recovery 296\u003c\/p\u003e \u003cp\u003e11.2 Software Aging and Rejuvenation 296\u003c\/p\u003e \u003cp\u003e11.3 Security 297\u003c\/p\u003e \u003cp\u003e11.3.1 Challenges 297\u003c\/p\u003e \u003cp\u003e11.3.2 Common Vulnerabilities 298\u003c\/p\u003e \u003cp\u003e11.3.3 Secure Software Design 299\u003c\/p\u003e \u003cp\u003e11.4 Safety 300\u003c\/p\u003e \u003cp\u003e11.5 Power Conservation 301\u003c\/p\u003e \u003cp\u003eSuggestions for Reading 302\u003c\/p\u003e \u003cp\u003eReferences 302\u003c\/p\u003e \u003cp\u003eIndex 305\u003c\/p\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default Title","offer_id":49528822202711,"sku":"9781118116173","price":95.36,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9781118116173.jpg?v=1731873151","url":"https:\/\/bookcurl.com\/products\/realtime-embedded-systems-9781118116173","provider":"Book Curl","version":"1.0","type":"link"}