{"product_id":"realtime-electromagnetic-transient-simulation-of-acdc-networks-ieee-press-series-on-power-and-energy-systems-9781119695448","title":"RealTime Electromagnetic Transient Simulation of","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eAbout the Authors xix\u003c\/p\u003e \u003cp\u003ePreface xxi\u003c\/p\u003e \u003cp\u003eAcknowledgments xxv\u003c\/p\u003e \u003cp\u003eList of Acronyms xxvii\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Field Programmable Gate Arrays \u003c\/b\u003e\u003cb\u003e1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Overview 1\u003c\/p\u003e \u003cp\u003e1.1.1 FPGA Hardware Architecture 2\u003c\/p\u003e \u003cp\u003e1.1.2 Configurable Logic Block 3\u003c\/p\u003e \u003cp\u003e1.1.3 Block RAM 4\u003c\/p\u003e \u003cp\u003e1.1.4 Digital Signal Processing Slice 4\u003c\/p\u003e \u003cp\u003e1.2 Multiprocessing System-on-Chip Architecture 6\u003c\/p\u003e \u003cp\u003e1.3 Communication 7\u003c\/p\u003e \u003cp\u003e1.4 HIL Emulation 9\u003c\/p\u003e \u003cp\u003e1.4.1 Vivado\u003csup\u003e®\u003c\/sup\u003e High-Level Synthesis Tool 9\u003c\/p\u003e \u003cp\u003e1.4.2 Vivado\u003csup\u003e®\u003c\/sup\u003e Top-Level Design 11\u003c\/p\u003e \u003cp\u003e1.4.3 Number Representation and Operations 13\u003c\/p\u003e \u003cp\u003e1.4.4 FPGA Design Schemes 14\u003c\/p\u003e \u003cp\u003e1.4.4.1 Pipeline Design Architecture 14\u003c\/p\u003e \u003cp\u003e1.4.4.2 Parallel Design Architecture 14\u003c\/p\u003e \u003cp\u003e1.4.5 FPGA Experiment 15\u003c\/p\u003e \u003cp\u003e1.5 Summary 16\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Hardware Emulation Building Blocks for Power System Components \u003c\/b\u003e\u003cb\u003e17\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Overview 17\u003c\/p\u003e \u003cp\u003e2.2 Concept of HEBB 18\u003c\/p\u003e \u003cp\u003e2.3 Numerical Integration 18\u003c\/p\u003e \u003cp\u003e2.4 Linear Lumped Passive Elements 20\u003c\/p\u003e \u003cp\u003e2.4.1 Model Formulation 20\u003c\/p\u003e \u003cp\u003e2.4.1.1 Resistance \u003ci\u003eR \u003c\/i\u003e20\u003c\/p\u003e \u003cp\u003e2.4.1.2 Inductance \u003ci\u003eL \u003c\/i\u003e20\u003c\/p\u003e \u003cp\u003e2.4.1.3 Capacitance \u003ci\u003eC \u003c\/i\u003e22\u003c\/p\u003e \u003cp\u003e2.4.1.4 \u003ci\u003eRL \u003c\/i\u003eBranch 23\u003c\/p\u003e \u003cp\u003e2.4.1.5 \u003ci\u003eLC \u003c\/i\u003eBranch 23\u003c\/p\u003e \u003cp\u003e2.4.1.6 \u003ci\u003eRLCG \u003c\/i\u003eBranch 24\u003c\/p\u003e \u003cp\u003e2.4.2 Hardware Emulation of Linear Lumped Passive Elements 26\u003c\/p\u003e \u003cp\u003e2.5 Sources 27\u003c\/p\u003e \u003cp\u003e2.5.1 Hardware Emulation of Sources 28\u003c\/p\u003e \u003cp\u003e2.6 Switches 30\u003c\/p\u003e \u003cp\u003e2.6.1 Hardware Emulation of Switches 30\u003c\/p\u003e \u003cp\u003e2.7 Transmission Lines 32\u003c\/p\u003e \u003cp\u003e2.7.1 Traveling Waves 32\u003c\/p\u003e \u003cp\u003e2.7.2 Traveling Wave Model 35\u003c\/p\u003e \u003cp\u003e2.7.2.1 Modal Transformation 36\u003c\/p\u003e \u003cp\u003e2.7.3 Hardware Emulation of the TWM 39\u003c\/p\u003e \u003cp\u003e2.7.3.1 \u003ci\u003eTransformation Unit \u003c\/i\u003e39\u003c\/p\u003e \u003cp\u003e2.7.3.2 \u003ci\u003eUpdate Unit \u003c\/i\u003e39\u003c\/p\u003e \u003cp\u003e2.7.4 Frequency Dependent Line Model 41\u003c\/p\u003e \u003cp\u003e2.7.5 Hardware Emulation of FDLM 46\u003c\/p\u003e \u003cp\u003e2.7.5.1 \u003ci\u003eConvolution \u003c\/i\u003eUnit 46\u003c\/p\u003e \u003cp\u003e2.7.5.2 \u003ci\u003eUpdate \u003c\/i\u003eUnit 47\u003c\/p\u003e \u003cp\u003e2.7.6 Universal Line Model 48\u003c\/p\u003e \u003cp\u003e2.7.6.1 Frequency-Domain Formulation 48\u003c\/p\u003e \u003cp\u003e2.7.6.2 Time-Domain Formulation 49\u003c\/p\u003e \u003cp\u003e2.7.7 Hardware Emulation of the ULM 51\u003c\/p\u003e \u003cp\u003e2.7.7.1 \u003ci\u003eUpdate \u003cb\u003ex \u003c\/b\u003e\u003c\/i\u003eUnit 52\u003c\/p\u003e \u003cp\u003e2.7.7.2 \u003ci\u003eConvolution \u003c\/i\u003eUnit 52\u003c\/p\u003e \u003cp\u003e2.7.7.3 \u003ci\u003eInterpolation \u003c\/i\u003eUnit 54\u003c\/p\u003e \u003cp\u003e2.8 Network Solver 54\u003c\/p\u003e \u003cp\u003e2.8.1 Hardware Emulation of Network Solver 55\u003c\/p\u003e \u003cp\u003e2.8.2 Paralleled EMT Solution Algorithm 55\u003c\/p\u003e \u003cp\u003e2.8.3 \u003ci\u003eMain Control \u003c\/i\u003eModule 58\u003c\/p\u003e \u003cp\u003e2.8.4 Real-Time Emulation Case Study 59\u003c\/p\u003e \u003cp\u003e2.9 Nonlinear Elements: Iterative Real-Time EMT Solver 63\u003c\/p\u003e \u003cp\u003e2.9.1 Compensation Method 64\u003c\/p\u003e \u003cp\u003e2.9.2 Newton–Raphson Method 65\u003c\/p\u003e \u003cp\u003e2.9.3 Hardware Emulation of Nonlinear Solver 67\u003c\/p\u003e \u003cp\u003e2.9.3.1 Nonlinear Function Evaluation 68\u003c\/p\u003e \u003cp\u003e2.9.3.2 Parallel Calculation of \u003cb\u003e\u003ci\u003eJ \u003c\/i\u003e\u003c\/b\u003eand \u003ci\u003eF\u003c\/i\u003e(\u003ci\u003ei\u003csub\u003ekm\u003c\/sub\u003e\u003c\/i\u003e) 68\u003c\/p\u003e \u003cp\u003e2.9.3.3 Parallel Gauss–Jordan Elimination 71\u003c\/p\u003e \u003cp\u003e2.9.3.4 Computing \u003ci\u003ev\u003csub\u003ec\u003c\/sub\u003e \u003c\/i\u003e71\u003c\/p\u003e \u003cp\u003e2.9.4 Case Studies 71\u003c\/p\u003e \u003cp\u003e2.10 Summary 77\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 Power Transformers \u003c\/b\u003e\u003cb\u003e79\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Overview 79\u003c\/p\u003e \u003cp\u003e3.2 Nonlinear Admittance-Based Real-Time Transformer Model 80\u003c\/p\u003e \u003cp\u003e3.2.1 Linear Model Formulation 80\u003c\/p\u003e \u003cp\u003e3.2.2 Linear Module Hardware Design 82\u003c\/p\u003e \u003cp\u003e3.2.3 Inode Unit Module 84\u003c\/p\u003e \u003cp\u003e3.2.4 Nonlinear Model Solution 85\u003c\/p\u003e \u003cp\u003e3.2.4.1 Preisach Hysteresis Model 88\u003c\/p\u003e \u003cp\u003e3.2.4.2 Nonlinear Module Hardware Design 89\u003c\/p\u003e \u003cp\u003e3.2.5 Frequency-Dependent Eddy Current Model 90\u003c\/p\u003e \u003cp\u003e3.2.6 Hardware Emulation of Power Transformer 91\u003c\/p\u003e \u003cp\u003e3.2.7 Real-Time Emulation Case Studies 94\u003c\/p\u003e \u003cp\u003e3.2.7.1 Case I 94\u003c\/p\u003e \u003cp\u003e3.2.7.2 Case II 99\u003c\/p\u003e \u003cp\u003e3.3 Nonlinear Magnetic Equivalent Circuit Based Real-time  Multi-Winding Transformer Model 100\u003c\/p\u003e \u003cp\u003e3.3.1 Topological ST EMT Model 102\u003c\/p\u003e \u003cp\u003e3.3.1.1 ST Operating Principle 102\u003c\/p\u003e \u003cp\u003e3.3.1.2 Tap-selection Algorithm 102\u003c\/p\u003e \u003cp\u003e3.3.1.3 High-Fidelity Nonlinear MEC-Based ST Model 102\u003c\/p\u003e \u003cp\u003e3.3.1.4 Iron Core Hysteresis and Eddy Currents 107\u003c\/p\u003e \u003cp\u003e3.3.2 High-Fidelity Nonlinear MEC-Based ST Hardware Emulation 109\u003c\/p\u003e \u003cp\u003e3.3.2.1 Network Transient Emulation with Embedded ST 109\u003c\/p\u003e \u003cp\u003e3.3.3 Real-Time Emulation Case Studies 112\u003c\/p\u003e \u003cp\u003e3.3.3.1 Finite Element Modeling and Validation 112\u003c\/p\u003e \u003cp\u003e3.3.3.2 Case Studies 112\u003c\/p\u003e \u003cp\u003e3.4 Real-Time Finite-Element Model of Power Transformer 123\u003c\/p\u003e \u003cp\u003e3.4.1 Magnetodynamic Problem Formulation 123\u003c\/p\u003e \u003cp\u003e3.4.1.1 Refined TLM Solution 126\u003c\/p\u003e \u003cp\u003e3.4.1.2 Field-Circuit Coupling 130\u003c\/p\u003e \u003cp\u003e3.4.2 Hardware Emulation of Finite Element Model 132\u003c\/p\u003e \u003cp\u003e3.4.3 Case Studies 136\u003c\/p\u003e \u003cp\u003e3.4.3.1 Results and Validation 137\u003c\/p\u003e \u003cp\u003e3.4.3.2 Speed-up and Scalability 140\u003c\/p\u003e \u003cp\u003e3.5 Summary 141\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Rotating Machines \u003c\/b\u003e\u003cb\u003e143\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Overview 143\u003c\/p\u003e \u003cp\u003e4.2 Lumped Universal Machine (UM) Model 144\u003c\/p\u003e \u003cp\u003e4.2.1 UM Model Formulation 144\u003c\/p\u003e \u003cp\u003e4.2.2 Interfacing UM Model with Network 146\u003c\/p\u003e \u003cp\u003e4.2.3 UM HEBB 148\u003c\/p\u003e \u003cp\u003e4.2.3.1 \u003ci\u003eSpeed \u0026amp; Angle \u003c\/i\u003eUnit 149\u003c\/p\u003e \u003cp\u003e4.2.3.2 \u003ci\u003eFrmTran \u003c\/i\u003eUnit 150\u003c\/p\u003e \u003cp\u003e4.2.3.3 \u003ci\u003eComp\u003c\/i\u003ei\u003ci\u003e\u003csub\u003edq\u003c\/sub\u003e\u003c\/i\u003e\u003csub\u003e0\u003c\/sub\u003e Unit 151\u003c\/p\u003e \u003cp\u003e4.2.3.4 \u003ci\u003eFlux \u0026amp; Torque \u003c\/i\u003eUnit 151\u003c\/p\u003e \u003cp\u003e4.2.3.5 \u003ci\u003eUpdate \u0026amp; CompVc \u003c\/i\u003eUnit 151\u003c\/p\u003e \u003cp\u003e4.2.4 Real-Time Emulation Case Study 152\u003c\/p\u003e \u003cp\u003e4.2.5 Overall Power System HEBB for Real-Time EMT Emulation 154\u003c\/p\u003e \u003cp\u003e4.3 General Framework for State-Space Electrical Machine Emulation 158\u003c\/p\u003e \u003cp\u003e4.3.1 FPGA Design Approaches for Electrical Machine Emulation 159\u003c\/p\u003e \u003cp\u003e4.3.2 State-Space Representation of Machine Models 160\u003c\/p\u003e \u003cp\u003e4.3.3 System Configuration on FPGA 161\u003c\/p\u003e \u003cp\u003e4.3.3.1 Number Representation 161\u003c\/p\u003e \u003cp\u003e4.3.3.2 Floating-Point Implementation by VHDL 162\u003c\/p\u003e \u003cp\u003e4.3.3.3 Fixed-Point Implementation by Schematic 167\u003c\/p\u003e \u003cp\u003e4.3.4 Evaluation of Designed Architectures 170\u003c\/p\u003e \u003cp\u003e4.3.4.1 Real-Time Emulation Accuracy Assessment 170\u003c\/p\u003e \u003cp\u003e4.3.4.2 Off-line Validation 171\u003c\/p\u003e \u003cp\u003e4.3.4.3 Hardware Resource Utilization 172\u003c\/p\u003e \u003cp\u003e4.3.5 Real-Time Emulation Case Studies 174\u003c\/p\u003e \u003cp\u003e4.3.5.1 Case I: Induction Motor Transients 174\u003c\/p\u003e \u003cp\u003e4.3.5.2 Case II: Synchronous Generator Transients 174\u003c\/p\u003e \u003cp\u003e4.3.5.3 Case III: Line Start-Permanent Magnet Synchronous Motor Transients 176\u003c\/p\u003e \u003cp\u003e4.3.5.4 Case IV: DC Motor Transients 177\u003c\/p\u003e \u003cp\u003e4.4 Nonlinear Magnetic Equivalent Circuit Based Induction Machine Model 178\u003c\/p\u003e \u003cp\u003e4.4.1 Magnetic Circuit 179\u003c\/p\u003e \u003cp\u003e4.4.2 Interfacing of Magnetic and Electric Circuits 181\u003c\/p\u003e \u003cp\u003e4.4.3 Electric Circuit 182\u003c\/p\u003e \u003cp\u003e4.4.4 Nonlinear Solution of Detailed MEC 182\u003c\/p\u003e \u003cp\u003e4.4.5 Hardware Emulation of Nonlinear MEC 183\u003c\/p\u003e \u003cp\u003e4.4.5.1 Parallel Gauss–Jordan Elimination Unit 185\u003c\/p\u003e \u003cp\u003e4.4.5.2 Parallel Computational Unit for Residual Vector 187\u003c\/p\u003e \u003cp\u003e4.4.5.3 Nonlinear Evaluation Unit 187\u003c\/p\u003e \u003cp\u003e4.4.6 Evaluation of Real-Time Emulation of Induction Machine 187\u003c\/p\u003e \u003cp\u003e4.5 Summary 190\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 Protective Relays \u003c\/b\u003e\u003cb\u003e193\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Overview 193\u003c\/p\u003e \u003cp\u003e5.2 Hardware Emulation of Multifunction Protection System 195\u003c\/p\u003e \u003cp\u003e5.2.1 Signal Processing HEBB 196\u003c\/p\u003e \u003cp\u003e5.2.1.1 CORDIC HEBB 196\u003c\/p\u003e \u003cp\u003e5.2.1.2 Symmetrical Components HEBB 198\u003c\/p\u003e \u003cp\u003e5.2.1.3 DFT HEBB 198\u003c\/p\u003e \u003cp\u003e5.2.1.4 Zero-Crossing Detection HEBB 199\u003c\/p\u003e \u003cp\u003e5.2.2 Multifunction Protective System HEBB 203\u003c\/p\u003e \u003cp\u003e5.2.2.1 Fault Detection HEBB 203\u003c\/p\u003e \u003cp\u003e5.2.2.2 Directional Overcurrent Protection HEBB 205\u003c\/p\u003e \u003cp\u003e5.2.2.3 Over\/Under Voltage Protection HEBB 205\u003c\/p\u003e \u003cp\u003e5.2.2.4 Distance Protection HEBB 205\u003c\/p\u003e \u003cp\u003e5.2.2.5 Under\/Over Frequency Protection HEBB 209\u003c\/p\u003e \u003cp\u003e5.3 Test Setup and Real-Time Results 209\u003c\/p\u003e \u003cp\u003e5.3.1 Case I 210\u003c\/p\u003e \u003cp\u003e5.3.2 Case II 213\u003c\/p\u003e \u003cp\u003e5.4 Summary 214\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Adaptive Time-Stepping Based Real-Time EMT Emulation \u003c\/b\u003e\u003cb\u003e217\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Overview 217\u003c\/p\u003e \u003cp\u003e6.2 Nonlinear Solution and Adaptive Time-Stepping Schemes 219\u003c\/p\u003e \u003cp\u003e6.2.1 Nonlinear Element Solution Methods 219\u003c\/p\u003e \u003cp\u003e6.2.1.1 Newton–Raphson Method 219\u003c\/p\u003e \u003cp\u003e6.2.1.2 Piecewise Linearization (PWL) Method 219\u003c\/p\u003e \u003cp\u003e6.2.1.3 Piecewise N-R Method 220\u003c\/p\u003e \u003cp\u003e6.2.2 Adaptive Time-Stepping Schemes 220\u003c\/p\u003e \u003cp\u003e6.2.2.1 Local Truncation Error Method 220\u003c\/p\u003e \u003cp\u003e6.2.2.2 Iteration Count Method 221\u003c\/p\u003e \u003cp\u003e6.2.2.3 DVDT or DIDT Method 221\u003c\/p\u003e \u003cp\u003e6.2.3 Combinations of Adaptive Time-Stepping Schemes 222\u003c\/p\u003e \u003cp\u003e6.2.3.1 Measurements and Restrictions for Real-Time Emulation 222\u003c\/p\u003e \u003cp\u003e6.2.4 Case Studies 223\u003c\/p\u003e \u003cp\u003e6.2.4.1 Diode Full-Bridge Circuit 224\u003c\/p\u003e \u003cp\u003e6.2.4.2 Power Transmission System 225\u003c\/p\u003e \u003cp\u003e6.2.4.3 FPGA Implementation 229\u003c\/p\u003e \u003cp\u003e6.2.4.4 Real-Time Emulation Results 234\u003c\/p\u003e \u003cp\u003e6.3 Adaptive Time-Stepping Universal Line Model and Universal Machine Model for Real-Time Hardware Emulation 236\u003c\/p\u003e \u003cp\u003e6.3.1 Subsystem-Based Adaptive Time-Stepping Scheme 237\u003c\/p\u003e \u003cp\u003e6.3.2 Adaptive Time-Stepping ULM and UM Models 238\u003c\/p\u003e \u003cp\u003e6.3.2.1 ULM Computation 238\u003c\/p\u003e \u003cp\u003e6.3.2.2 Universal Machine Model Computation 242\u003c\/p\u003e \u003cp\u003e6.3.3 Real-Time Emulation Case Study 243\u003c\/p\u003e \u003cp\u003e6.3.3.1 Hardware Implementation 243\u003c\/p\u003e \u003cp\u003e6.3.3.2 Latency and Hardware Resource Utilization 246\u003c\/p\u003e \u003cp\u003e6.3.4 Results and Validation 247\u003c\/p\u003e \u003cp\u003e6.3.4.1 Validation of the ULM Model 247\u003c\/p\u003e \u003cp\u003e6.3.4.2 Real-Time Emulation Results 248\u003c\/p\u003e \u003cp\u003e6.4 Summary 252\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Power Electronic Switches \u003c\/b\u003e\u003cb\u003e253\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Overview 253\u003c\/p\u003e \u003cp\u003e7.2 IGBT\/Diode Nonlinear Behavioral Model 255\u003c\/p\u003e \u003cp\u003e7.2.1 Power Diode 256\u003c\/p\u003e \u003cp\u003e7.2.1.1 Mathematical Model 256\u003c\/p\u003e \u003cp\u003e7.2.1.2 Hardware Module Architecture 257\u003c\/p\u003e \u003cp\u003e7.2.2 IGBT 259\u003c\/p\u003e \u003cp\u003e7.2.2.1 Model Formulation 259\u003c\/p\u003e \u003cp\u003e7.2.2.2 Hardware Module Architecture 263\u003c\/p\u003e \u003cp\u003e7.2.2.3 Multiple Parallel Devices 265\u003c\/p\u003e \u003cp\u003e7.2.3 Electro-Thermal Network 267\u003c\/p\u003e \u003cp\u003e7.2.4 Hardware Emulation Results 268\u003c\/p\u003e \u003cp\u003e7.3 Physics-Based Nonlinear IGBT\/Diode Model 270\u003c\/p\u003e \u003cp\u003e7.3.1 Physics-Based Nonlinear p–i–n Diode Model 271\u003c\/p\u003e \u003cp\u003e7.3.1.1 Model Formulation 271\u003c\/p\u003e \u003cp\u003e7.3.1.2 Model Discretization and Linearization 272\u003c\/p\u003e \u003cp\u003e7.3.1.3 Hardware Emulation on FPGA 274\u003c\/p\u003e \u003cp\u003e7.3.2 Physics-Based Nonlinear IGBT Model 276\u003c\/p\u003e \u003cp\u003e7.3.2.1 Model Formulation 276\u003c\/p\u003e \u003cp\u003e7.3.2.2 Model Discretization and Linearization 279\u003c\/p\u003e \u003cp\u003e7.3.2.3 Hardware Emulation on FPGA 281\u003c\/p\u003e \u003cp\u003e7.3.3 Hardware Emulation Results 285\u003c\/p\u003e \u003cp\u003e7.3.3.1 Test circuit 285\u003c\/p\u003e \u003cp\u003e7.3.3.2 Results and comparison 286\u003c\/p\u003e \u003cp\u003e7.4 IGBT\/Diode Curve-Fitting Model 292\u003c\/p\u003e \u003cp\u003e7.4.1 Linear Static Curve-fitting Model 293\u003c\/p\u003e \u003cp\u003e7.4.1.1 Static Characteristics 293\u003c\/p\u003e \u003cp\u003e7.4.1.2 Switching Transients 293\u003c\/p\u003e \u003cp\u003e7.4.2 Nonlinear Dynamic Curve-fitting Model 296\u003c\/p\u003e \u003cp\u003e7.4.3 Hardware Emulation Results 298\u003c\/p\u003e \u003cp\u003e7.5 Summary 300\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 AC–DC Converters \u003c\/b\u003e\u003cb\u003e301\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Overview 301\u003c\/p\u003e \u003cp\u003e8.2 Detailed Model 303\u003c\/p\u003e \u003cp\u003e8.2.1 Detailed Equivalent Circuit Model 304\u003c\/p\u003e \u003cp\u003e8.3 Equivalenced Device-Level Model 305\u003c\/p\u003e \u003cp\u003e8.3.1 Power Loss Calculation 307\u003c\/p\u003e \u003cp\u003e8.3.2 Thermal Network Calculation 309\u003c\/p\u003e \u003cp\u003e8.3.3 Hardware Emulation of SM Model on FPGA 311\u003c\/p\u003e \u003cp\u003e8.3.4 MMC System Hardware Emulation 314\u003c\/p\u003e \u003cp\u003e8.3.5 Real-Time Emulation Results 316\u003c\/p\u003e \u003cp\u003e8.3.5.1 Test Circuit and Hardware Resource Utilization 316\u003c\/p\u003e \u003cp\u003e8.3.5.2 Results and Comparison for Single-Phase Five-Level MMC 318\u003c\/p\u003e \u003cp\u003e8.3.5.3 Results for Three-Phase Nine-Level MMC 324\u003c\/p\u003e \u003cp\u003e8.4 Virtual-Line-Partitioned Device-Level Models 324\u003c\/p\u003e \u003cp\u003e8.4.1 TLM-Link Partitioning 326\u003c\/p\u003e \u003cp\u003e8.4.2 Hardware Design on FPGA 328\u003c\/p\u003e \u003cp\u003e8.4.2.1 Hardware Platform 329\u003c\/p\u003e \u003cp\u003e8.4.2.2 Controller Emulation 329\u003c\/p\u003e \u003cp\u003e8.4.2.3 MMC Emulation on FPGA 330\u003c\/p\u003e \u003cp\u003e8.4.3 Real-Time Emulation Results 335\u003c\/p\u003e \u003cp\u003e8.4.3.1 MMC 335\u003c\/p\u003e \u003cp\u003e8.4.3.2 Induction Machine Driven by Five-Level MMC 342\u003c\/p\u003e \u003cp\u003e8.5 MMC Partitioned by Coupled Voltage–Current Sources 344\u003c\/p\u003e \u003cp\u003e8.5.1 \u003ci\u003eV\u003c\/i\u003e–\u003ci\u003eI \u003c\/i\u003eCoupling 344\u003c\/p\u003e \u003cp\u003e8.5.2 Hardware Emulation Case of NBM-Based MMC 346\u003c\/p\u003e \u003cp\u003e8.5.2.1 Power Converter HIL Emulation 346\u003c\/p\u003e \u003cp\u003e8.5.2.2 HIL Emulation Results and Validation 347\u003c\/p\u003e \u003cp\u003e8.5.2.3 Islanded MMC Performance 348\u003c\/p\u003e \u003cp\u003e8.5.2.4 MMC–MVDC Performance 355\u003c\/p\u003e \u003cp\u003e8.6 Clamped Double Submodule MMC 355\u003c\/p\u003e \u003cp\u003e8.6.1 Operation Principles of CDSM 357\u003c\/p\u003e \u003cp\u003e8.6.2 Device-Level Modeling Scheme 359\u003c\/p\u003e \u003cp\u003e8.6.2.1 Temperature-Dependent Electrical Interface Parameter Calculation 359\u003c\/p\u003e \u003cp\u003e8.6.2.2 Device-Level Linearized Transient Waveform Calculation 361\u003c\/p\u003e \u003cp\u003e8.6.3 SM-Level Modeling Scheme 362\u003c\/p\u003e \u003cp\u003e8.6.4 Converter-Level Modeling Scheme 362\u003c\/p\u003e \u003cp\u003e8.6.5 Case Study and Hardware Implementation 363\u003c\/p\u003e \u003cp\u003e8.6.5.1 Design Partition 365\u003c\/p\u003e \u003cp\u003e8.6.5.2 Latency and Resource Consumption 367\u003c\/p\u003e \u003cp\u003e8.6.6 Real-Time Emulation Results and Analysis 368\u003c\/p\u003e \u003cp\u003e8.6.6.1 Steady-State Results 368\u003c\/p\u003e \u003cp\u003e8.6.6.2 DC Power Flow Control 368\u003c\/p\u003e \u003cp\u003e8.6.6.3 DC Fault Transient Results 371\u003c\/p\u003e \u003cp\u003e8.7 Summary 374\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 DC-DC Converters \u003c\/b\u003e\u003cb\u003e377\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Overview 377\u003c\/p\u003e \u003cp\u003e9.2 Buck–Boost Converter 379\u003c\/p\u003e \u003cp\u003e9.2.1 System-Level Modeling 379\u003c\/p\u003e \u003cp\u003e9.2.2 Hardware Implementation 380\u003c\/p\u003e \u003cp\u003e9.3 Solid-State Transformer Modeling 381\u003c\/p\u003e \u003cp\u003e9.3.1 MMC Arm Models 382\u003c\/p\u003e \u003cp\u003e9.3.1.1 TLM-Stub Model (TLM-S) 382\u003c\/p\u003e \u003cp\u003e9.3.1.2 Nonlinear Switch-Based Model (NSM) 383\u003c\/p\u003e \u003cp\u003e9.3.1.3 Hybrid Arm Model 384\u003c\/p\u003e \u003cp\u003e9.3.2 Three-Phase Saturable Transformer Model 385\u003c\/p\u003e \u003cp\u003e9.3.3 SST EMT Model 385\u003c\/p\u003e \u003cp\u003e9.3.4 SST HIL Emulation 386\u003c\/p\u003e \u003cp\u003e9.3.5 SST Real-Time HIL Emulation Results 390\u003c\/p\u003e \u003cp\u003e9.3.5.1 Device-Level Behavior 390\u003c\/p\u003e \u003cp\u003e9.3.5.2 Converter Performance 391\u003c\/p\u003e \u003cp\u003e9.3.5.3 System Tests 392\u003c\/p\u003e \u003cp\u003e9.4 Summary 394\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 DC Circuit Breakers \u003c\/b\u003e\u003cb\u003e397\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Overview 397\u003c\/p\u003e \u003cp\u003e10.2 HHB in MTDC System 399\u003c\/p\u003e \u003cp\u003e10.2.1 MTDC Test System Schematic 399\u003c\/p\u003e \u003cp\u003e10.2.2 DC Line Protection 401\u003c\/p\u003e \u003cp\u003e10.2.2.1 Voltage Derivative Protection 401\u003c\/p\u003e \u003cp\u003e10.2.2.2 Over Current Protection 401\u003c\/p\u003e \u003cp\u003e10.3 Proactive Hybrid HVDC Breaker 402\u003c\/p\u003e \u003cp\u003e10.3.1 HHB EMT Model 403\u003c\/p\u003e \u003cp\u003e10.3.2 Varistor Model 404\u003c\/p\u003e \u003cp\u003e10.3.3 General HHB Unit Model 406\u003c\/p\u003e \u003cp\u003e10.3.4 Two-Node IGBT Models 407\u003c\/p\u003e \u003cp\u003e10.3.5 IGBT Low-Order Nonlinear Behavioral Model 409\u003c\/p\u003e \u003cp\u003e10.3.5.1 IGBT Fourth-Order Behavioral Model 409\u003c\/p\u003e \u003cp\u003e10.3.5.2 Parameters Extraction 409\u003c\/p\u003e \u003cp\u003e10.3.5.3 Sensitivity Analysis 410\u003c\/p\u003e \u003cp\u003e10.3.5.4 Model Parallelization 411\u003c\/p\u003e \u003cp\u003e10.3.6 Electro-Thermal Network 412\u003c\/p\u003e \u003cp\u003e10.3.7 HHB Hardware Implementation on FPGA 412\u003c\/p\u003e \u003cp\u003e10.3.8 HHB HIL Emulation Results 416\u003c\/p\u003e \u003cp\u003e10.3.8.1 Device-Level Performance 416\u003c\/p\u003e \u003cp\u003e10.3.8.2 System-Level Performance 424\u003c\/p\u003e \u003cp\u003e10.4 Ultrafast Mechatronic Circuit Breaker 426\u003c\/p\u003e \u003cp\u003e10.4.1 Nonlinear Device-Level Thyristor Model 426\u003c\/p\u003e \u003cp\u003e10.4.1.1 Basic Device Characteristics 426\u003c\/p\u003e \u003cp\u003e10.4.1.2 Scalable Cascaded Thyristor Model 428\u003c\/p\u003e \u003cp\u003e10.4.2 UFMCB Modeling 431\u003c\/p\u003e \u003cp\u003e10.4.3 Relaxed Scalar Newton–Raphson (RSNR) 433\u003c\/p\u003e \u003cp\u003e10.4.4 UFMCB Hardware Design 435\u003c\/p\u003e \u003cp\u003e10.4.5 UFMCB Real-Time Tests and Validation 438\u003c\/p\u003e \u003cp\u003e10.4.5.1 Four-Terminal DC Grid Test Case 438\u003c\/p\u003e \u003cp\u003e10.4.5.2 UFMCB Design Evaluation by HIL System 438\u003c\/p\u003e \u003cp\u003e10.4.5.3 UFMCB in HVDC Grid 442\u003c\/p\u003e \u003cp\u003e10.5 Summary 444\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 Large-Scale AC and DC Networks \u003c\/b\u003e\u003cb\u003e447\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Overview 447\u003c\/p\u003e \u003cp\u003e11.2 Spatial Decomposition and Parallelism 449\u003c\/p\u003e \u003cp\u003e11.2.1 Functional Decomposition for Large-Scale Real-Time Emulation 449\u003c\/p\u003e \u003cp\u003e11.2.2 Hardware Module Parallelism 451\u003c\/p\u003e \u003cp\u003e11.3 Multi-FPGA Hardware Design for Real-Time EMT Emulation 453\u003c\/p\u003e \u003cp\u003e11.3.1 Case I: 3-FPGA Hardware Design 454\u003c\/p\u003e \u003cp\u003e11.3.2 Case II: 10-FPGA Hardware Design 457\u003c\/p\u003e \u003cp\u003e11.3.3 Performance and Scalability of the Real-Time EMT Emulator 460\u003c\/p\u003e \u003cp\u003e11.4 CIGRÉ DC Grid Hybrid Modeling Methodology 465\u003c\/p\u003e \u003cp\u003e11.4.1 Network Topology 467\u003c\/p\u003e \u003cp\u003e11.4.2 Control Scheme 467\u003c\/p\u003e \u003cp\u003e11.4.3 Hybrid Modeling Methodology 468\u003c\/p\u003e \u003cp\u003e11.4.3.1 Device-Level Electrothermal Model 469\u003c\/p\u003e \u003cp\u003e11.4.3.2 Equivalent Circuit Model 469\u003c\/p\u003e \u003cp\u003e11.4.3.3 Average Value Model 471\u003c\/p\u003e \u003cp\u003e11.4.3.4 Transmission Line Model 471\u003c\/p\u003e \u003cp\u003e11.4.4 Real-Time MPSoC-FPGA Based DC Grid Emulator 471\u003c\/p\u003e \u003cp\u003e11.4.4.1 System Decomposition 471\u003c\/p\u003e \u003cp\u003e11.4.4.2 Hardware Resource Allocation and Task Partitioning 472\u003c\/p\u003e \u003cp\u003e11.4.4.3 Design and Implementation 474\u003c\/p\u003e \u003cp\u003e11.4.5 Real-Time Emulation Results and Validation 475\u003c\/p\u003e \u003cp\u003e11.4.5.1 Steady-State Operation 475\u003c\/p\u003e \u003cp\u003e11.4.5.2 Power Flow Command Change 477\u003c\/p\u003e \u003cp\u003e11.4.5.3 DC Fault 477\u003c\/p\u003e \u003cp\u003e11.5 Real-Time Co-Emulation Framework for Cyber-Physical Systems 479\u003c\/p\u003e \u003cp\u003e11.5.1 Communication Network Simulation and Co-Simulation 481\u003c\/p\u003e \u003cp\u003e11.5.2 Real-Time Co-Emulation Framework 484\u003c\/p\u003e \u003cp\u003e11.5.2.1 RTCE Hardware Architecture 484\u003c\/p\u003e \u003cp\u003e11.5.3 Hardware Implementation of RTCE 487\u003c\/p\u003e \u003cp\u003e11.5.3.1 Multi-Board EMT Emulation 488\u003c\/p\u003e \u003cp\u003e11.5.3.2 Communication Protocol and Implementation 489\u003c\/p\u003e \u003cp\u003e11.5.4 Real-Time Emulation Results and Verification 491\u003c\/p\u003e \u003cp\u003e11.5.4.1 Processing Delay and Hardware Resource Cost 491\u003c\/p\u003e \u003cp\u003e11.5.4.2 Case Study 1: Over-Current Fault 492\u003c\/p\u003e \u003cp\u003e11.5.4.3 Case Study 2: Communication Link Failure 493\u003c\/p\u003e \u003cp\u003e11.6 Faster-Than-Real-Time Hybrid Dynamic-EMT Emulation of AC–DC Grids 495\u003c\/p\u003e \u003cp\u003e11.6.1 Flexible Time-Stepping Algorithm for Dynamic Emulation 496\u003c\/p\u003e \u003cp\u003e11.6.1.1 Transient Stability Emulation Methodology 496\u003c\/p\u003e \u003cp\u003e11.6.1.2 Local Equipment Based Flexible Time-stepping 497\u003c\/p\u003e \u003cp\u003e11.6.2 AC–DC Grid Component Modeling 498\u003c\/p\u003e \u003cp\u003e11.6.2.1 AC–DC Grid Interface 498\u003c\/p\u003e \u003cp\u003e11.6.2.2 AC Grid Modeling 499\u003c\/p\u003e \u003cp\u003e11.6.2.3 DC Grid Modeling 501\u003c\/p\u003e \u003cp\u003e11.6.3 FTRT Emulation on FPGAs 503\u003c\/p\u003e \u003cp\u003e11.6.4 FTRT Emulation Results and Validation 505\u003c\/p\u003e \u003cp\u003e11.6.4.1 Three-Phase-to-Ground Fault 506\u003c\/p\u003e \u003cp\u003e11.6.4.2 Generator Outage and Sudden Load Change 507\u003c\/p\u003e \u003cp\u003e11.7 Summary 510\u003c\/p\u003e \u003cp\u003eBibliography 513\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix A Parameters for Case Studies \u003c\/b\u003e\u003cb\u003e531\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA.1 Chapter 2 531\u003c\/p\u003e \u003cp\u003eA.1.1 Case in Section 2.7 531\u003c\/p\u003e \u003cp\u003eA.1.2 Cases in Section 2.8 531\u003c\/p\u003e \u003cp\u003eA.2 Chapter 3 531\u003c\/p\u003e \u003cp\u003eA.2.1 Cases in Section 3.2 531\u003c\/p\u003e \u003cp\u003eA.2.1.1 Cases Study I 531\u003c\/p\u003e \u003cp\u003eA.2.1.2 Cases Study II 532\u003c\/p\u003e \u003cp\u003eA.2.2 Cases in Section 3.3 532\u003c\/p\u003e \u003cp\u003eA.2.2.1 Transformer 532\u003c\/p\u003e \u003cp\u003eA.2.2.2 System 532\u003c\/p\u003e \u003cp\u003eA.2.3 Cases in Section 3.4 532\u003c\/p\u003e \u003cp\u003eA.3 Chapter 4 533\u003c\/p\u003e \u003cp\u003eA.3.1 UM Case in Section 4.2 533\u003c\/p\u003e \u003cp\u003eA.3.2 Cases in Section 4.3 534\u003c\/p\u003e \u003cp\u003eA.3.2.1 State-Space Matrices of Rotating Machines 534\u003c\/p\u003e \u003cp\u003eA.3.2.2 Parameters of Rotating Machines 538\u003c\/p\u003e \u003cp\u003eA.3.3 MEC Case in Section 4.4 538\u003c\/p\u003e \u003cp\u003eA.4 Chapter 5 538\u003c\/p\u003e \u003cp\u003eA.5 Chapter 6 539\u003c\/p\u003e \u003cp\u003eA.5.1 Cases in Section 6.2 539\u003c\/p\u003e \u003cp\u003eA.5.2 Cases in Section 6.3 540\u003c\/p\u003e \u003cp\u003eA.6 Chapter 7 540\u003c\/p\u003e \u003cp\u003eA.7 Chapter 8 541\u003c\/p\u003e \u003cp\u003eA.7.1 Equivalenced Device-Level Model in Section 8.3 541\u003c\/p\u003e \u003cp\u003eA.7.2 MMC-IM Case in Section 8.4 541\u003c\/p\u003e \u003cp\u003eA.7.3 MVDC Case in Section 8.5 541\u003c\/p\u003e \u003cp\u003eA.7.4 MTDC Case in Section 8.6 541\u003c\/p\u003e \u003cp\u003eA.8 Chapter 9 541\u003c\/p\u003e \u003cp\u003eA.9 Chapter 10 542\u003c\/p\u003e \u003cp\u003eA.9.1 HHB Case 542\u003c\/p\u003e \u003cp\u003eA.9.2 UFMCB Case 542\u003c\/p\u003e \u003cp\u003eA.10 Chapter 11 543\u003c\/p\u003e \u003cp\u003eA.10.1 CIGRÉ B4 DC Grid Test System 543\u003c\/p\u003e \u003cp\u003eIndex 545\u003c\/p\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default 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