{"product_id":"nanocmos-circuit-and-physical-design-9780471466109","title":"NanoCMOS Circuit and Physical Design","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eBased on the authors'' expansive collection of notes taken over the years, \u003ci\u003eNano-CMOS Circuit and Physical Design\u003c\/i\u003e bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength optical lithography; impact of process scaling on circuit and physical implementation and low power with leaky transistors; and DFM, yield, and the impact of physical implementation.\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003eFOREWORD.  \u003cp\u003ePREFACE.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Design Methodology in the Nano-CMOS Era.\u003c\/p\u003e \u003cp\u003e1.2 Innovations Needed to Continue Performance Scaling.\u003c\/p\u003e \u003cp\u003e1.3 Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography.\u003c\/p\u003e \u003cp\u003e1.4 Process Control and Reliability.\u003c\/p\u003e \u003cp\u003e1.5 Lithographic Issues and Mask Data Explosion.\u003c\/p\u003e \u003cp\u003e1.6 New Breed of Circuit and Physical Design Engineers.\u003c\/p\u003e \u003cp\u003e1.7 Modeling Challenges.\u003c\/p\u003e \u003cp\u003e1.8 Need for Design Methodology Changes.\u003c\/p\u003e \u003cp\u003e1.9 Summary.\u003c\/p\u003e \u003cp\u003eReferences.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART I: PROCESS TECHNOLOGY AND SUBWAVELENGTH OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION, ISSUES, AND SOLUTIONS.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 CMOS DEVICE AND PROCESS TECHNOLOGY.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Equipment Requirements for Front-End Processing.\u003c\/p\u003e \u003cp\u003e2.2 Front-End-Device Problems in CMOS Scaling.\u003c\/p\u003e \u003cp\u003e2.3 Back-End-of-Line Technology.\u003c\/p\u003e \u003cp\u003eReferences.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 THEORY AND PRACTICALITIES OF SUBWAVELENGTH OPTICAL LITHOGRAPHY.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Introduction and Simple Imaging Theory.\u003c\/p\u003e \u003cp\u003e3.2 Challenges for the 100-nm Node.\u003c\/p\u003e \u003cp\u003e3.3 Resolution Enhancement Techniques: Physics.\u003c\/p\u003e \u003cp\u003e3.4 Physical Design Style Impact on RET and OPC Complexity.\u003c\/p\u003e \u003cp\u003e3.5 The Road Ahead: Future Lithographic Technologies.\u003c\/p\u003e \u003cp\u003eReferences.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART II: PROCESS SCALING IMPACT ON DESIGN 4 MIXED-SIGNAL CIRCUIT DESIGN.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Introduction.\u003c\/p\u003e \u003cp\u003e4.2 Design Considerations.\u003c\/p\u003e \u003cp\u003e4.3 Device Modeling.\u003c\/p\u003e \u003cp\u003e4.4 Passive Components.\u003c\/p\u003e \u003cp\u003e4.5 Design Methodology.\u003c\/p\u003e \u003cp\u003e4.6 Low-Voltage Techniques.\u003c\/p\u003e \u003cp\u003e4.7 Design Procedures.\u003c\/p\u003e \u003cp\u003e4.8 Electrostatic Discharge Protection.\u003c\/p\u003e \u003cp\u003e4.9 Noise Isolation.\u003c\/p\u003e \u003cp\u003e4.10 Decoupling.\u003c\/p\u003e \u003cp\u003e4.11 Power Busing.\u003c\/p\u003e \u003cp\u003e4.12 Integration Problems.\u003c\/p\u003e \u003cp\u003e4.13 Summary.\u003c\/p\u003e \u003cp\u003eReferences.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 ELECTROSTATIC DISCHARGE PROTECTION DESIGN.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Introduction.\u003c\/p\u003e \u003cp\u003e5.2 ESD Standards and Models.\u003c\/p\u003e \u003cp\u003e5.3 ESD Protection Design.\u003c\/p\u003e \u003cp\u003e5.4 Low-\u003ci\u003eC\u003c\/i\u003e ESD Protection Design for High-Speed I\/O.\u003c\/p\u003e \u003cp\u003e5.5 ESD Protection Design for Mixed-Voltage I\/O.\u003c\/p\u003e \u003cp\u003e5.6 SCR Devices for ESD Protection.\u003c\/p\u003e \u003cp\u003e5.7 Summary.\u003c\/p\u003e \u003cp\u003eReferences.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 INPUT\/OUTPUT DESIGN.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Introduction.\u003c\/p\u003e \u003cp\u003e6.2 I\/O Standards.\u003c\/p\u003e \u003cp\u003e6.3 Signal Transfer.\u003c\/p\u003e \u003cp\u003e6.4 ESD Protection.\u003c\/p\u003e \u003cp\u003e6.5 I\/O Switching Noise.\u003c\/p\u003e \u003cp\u003e6.6 Termination.\u003c\/p\u003e \u003cp\u003e6.7 Impedance Matching.\u003c\/p\u003e \u003cp\u003e6.8 Preemphasis.\u003c\/p\u003e \u003cp\u003e6.9 Equalization.\u003c\/p\u003e \u003cp\u003e6.10 Conclusion.\u003c\/p\u003e \u003cp\u003eReferences.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 DRAM.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Introduction.\u003c\/p\u003e \u003cp\u003e7.2 DRAM Basics.\u003c\/p\u003e \u003cp\u003e7.3 Scaling the Capacitor.\u003c\/p\u003e \u003cp\u003e7.4 Scaling the Array Transistor.\u003c\/p\u003e \u003cp\u003e7.5 Scaling the Sense Amplifier.\u003c\/p\u003e \u003cp\u003e7.6 Summary.\u003c\/p\u003e \u003cp\u003eReferences.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 SIGNAL INTEGRITY PROBLEMS IN ON-CHIP INTERCONNECTS.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Introduction.\u003c\/p\u003e \u003cp\u003e8.2 Interconnect Parasitics Extraction.\u003c\/p\u003e \u003cp\u003e8.3 Signal Integrity Analysis.\u003c\/p\u003e \u003cp\u003e8.4 Design Solutions for Signal Integrity.\u003c\/p\u003e \u003cp\u003e8.5 Summary.\u003c\/p\u003e \u003cp\u003eReferences.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 ULTRALOW POWER CIRCUIT DESIGN.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Introduction.\u003c\/p\u003e \u003cp\u003e9.2 Design-Time Low-Power Techniques.\u003c\/p\u003e \u003cp\u003e9.3 Run-Time Low-Power Techniques.\u003c\/p\u003e \u003cp\u003e9.4 Technology Innovations for Low-Power Design.\u003c\/p\u003e \u003cp\u003e9.5 Perspectives for Future Ultralow-Power Design.\u003c\/p\u003e \u003cp\u003eReferences.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART III: IMPACT OF PHYSICAL DESIGN ON MANUFACTURING\/YIELD AND PERFORMANCE.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 DESIGN FOR MANUFACTURABILITY.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Introduction.\u003c\/p\u003e \u003cp\u003e10.2 Comparison of Optimal and Suboptimal Layouts.\u003c\/p\u003e \u003cp\u003e10.3 Global Route DFM.\u003c\/p\u003e \u003cp\u003e10.4 Analog DFM.\u003c\/p\u003e \u003cp\u003e10.5 Some Rules of Thumb.\u003c\/p\u003e \u003cp\u003e10.6 Summary.\u003c\/p\u003e \u003cp\u003eReferences.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 DESIGN FOR VARIABILITY.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Impact of Variations on Future Design.\u003c\/p\u003e \u003cp\u003e11.2 Strategies to Mitigate Impact Due to Variations.\u003c\/p\u003e \u003cp\u003e11.3 Corner Modeling Methodology for Nano-CMOS Processes.\u003c\/p\u003e \u003cp\u003e11.4 New Features of the BSIM4 Model.\u003c\/p\u003e \u003cp\u003e11.5 Summary.\u003c\/p\u003e \u003cp\u003eReferences.\u003c\/p\u003e \u003cp\u003eINDEX.\u003c\/p\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default 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