{"product_id":"multivoltage-cmos-circuit-design-9780470010235","title":"Multivoltage CMOS Circuit Design","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eThis book presents an in-depth treatment of various power reduction and speed enhancement techniques based on multiple supply and threshold voltages.\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eAbout the Authors xi\u003c\/p\u003e \u003cp\u003ePreface xiii\u003c\/p\u003e \u003cp\u003eAcknowledgments xv\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 1 Introduction 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Evolution of Integrated Circuits 3\u003c\/p\u003e \u003cp\u003e1.2 Outline of the Book 14\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 2 Sources of Power Consumption in CMOS ICs 19\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Dynamic Switching Power 19\u003c\/p\u003e \u003cp\u003e2.2 Leakage Power 22\u003c\/p\u003e \u003cp\u003e2.2.1 Subthreshold Leakage Current 22\u003c\/p\u003e \u003cp\u003e2.2.1.1 Short-Channel Effects 23\u003c\/p\u003e \u003cp\u003e2.2.1.2 Drain-Induced Barrier-Lowering 25\u003c\/p\u003e \u003cp\u003e2.2.1.3 Characterization of Subthreshold Leakage Current 25\u003c\/p\u003e \u003cp\u003e2.2.2 Gate Oxide Leakage Current 28\u003c\/p\u003e \u003cp\u003e2.2.2.1 Effect of Technology Scaling on Gate Oxide Leakage 29\u003c\/p\u003e \u003cp\u003e2.2.2.2 Characterization of Gate Oxide Leakage Current 32\u003c\/p\u003e \u003cp\u003e2.2.2.3 Alternative Gate Dielectric Materials 38\u003c\/p\u003e \u003cp\u003e2.3 Short-Circuit Power 39\u003c\/p\u003e \u003cp\u003e2.4 Static DC Power 43\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 3 Supply and Threshold Voltage Scaling Techniques 45\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Dynamic Supply Voltage Scaling 48\u003c\/p\u003e \u003cp\u003e3.2 Multiple Supply Voltage CMOS 51\u003c\/p\u003e \u003cp\u003e3.3 Threshold Voltage Scaling 54\u003c\/p\u003e \u003cp\u003e3.3.1 Body Bias Techniques 58\u003c\/p\u003e \u003cp\u003e3.3.1.1 Reverse Body Bias 58\u003c\/p\u003e \u003cp\u003e3.3.1.2 Forward Body Bias 64\u003c\/p\u003e \u003cp\u003e3.3.1.3 Bidirectional Body Bias 71\u003c\/p\u003e \u003cp\u003e3.3.2 Multiple Threshold Voltage CMOS 74\u003c\/p\u003e \u003cp\u003e3.4 Multiple Supply and Threshold Voltage CMOS 77\u003c\/p\u003e \u003cp\u003e3.5 Dynamic Supply and Threshold Voltage Scaling 80\u003c\/p\u003e \u003cp\u003e3.6 Circuits with Multiple Voltage and Clock Domains 81\u003c\/p\u003e \u003cp\u003e3.7 Summary 83\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 4 Low-Voltage Power Supplies 85\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Linear DC–DC Converters 87\u003c\/p\u003e \u003cp\u003e4.2 Switched-Capacitor DC–DC Converters 90\u003c\/p\u003e \u003cp\u003e4.3 Switching DC–DC Converters 91\u003c\/p\u003e \u003cp\u003e4.3.1 Operation of a Buck Converter 92\u003c\/p\u003e \u003cp\u003e4.3.2 Power Reduction Techniques for Switching DC–DC Converters 95\u003c\/p\u003e \u003cp\u003e4.4 Summary 95\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 5 Buck Converters for On-Chip Integration 99\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Circuit Model of a Buck Converter 101\u003c\/p\u003e \u003cp\u003e5.1.1 MOSFET-Related Power Losses 101\u003c\/p\u003e \u003cp\u003e5.1.2 Filter Inductor-Related Power Losses 103\u003c\/p\u003e \u003cp\u003e5.1.3 Filter Capacitor-Related Power Losses 103\u003c\/p\u003e \u003cp\u003e5.1.4 Total Power Consumption of a Buck Converter 104\u003c\/p\u003e \u003cp\u003e5.2 Efficiency Analysis of a Buck Converter 104\u003c\/p\u003e \u003cp\u003e5.2.1 Circuit Analysis for Global Maximum Efficiency 105\u003c\/p\u003e \u003cp\u003e5.2.2 Circuit Analysis with Limited Filter Capacitance 108\u003c\/p\u003e \u003cp\u003e5.2.3 Output Voltage Ripple Constraint 109\u003c\/p\u003e \u003cp\u003e5.3 Simulation Results 109\u003c\/p\u003e \u003cp\u003e5.4 Summary 112\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 6 Low-Voltage Swing Monolithic DC–DC Conversion 115\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Circuit Model of a Low-Voltage Swing Buck Converter 116\u003c\/p\u003e \u003cp\u003e6.1.1 MOSFET Power Dissipation 118\u003c\/p\u003e \u003cp\u003e6.1.2 MOSFET Model 119\u003c\/p\u003e \u003cp\u003e6.1.3 Filter Inductor Power Dissipation 120\u003c\/p\u003e \u003cp\u003e6.2 Low-Voltage Swing Buck Converter Analysis 121\u003c\/p\u003e \u003cp\u003e6.2.1 Full Swing Circuit Analysis for Global Maximum Efficiency 121\u003c\/p\u003e \u003cp\u003e6.2.2 Low Swing Circuit Analysis for Global Maximum Efficiency 123\u003c\/p\u003e \u003cp\u003e6.3 Summary 126\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 7 High Input Voltage Step-Down DC–DC Converters 127\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Cascode Bridge Circuits 129\u003c\/p\u003e \u003cp\u003e7.1.1 Cascode Bridge Circuit for Input Voltages up to 2\u003ci\u003eV\u003c\/i\u003emax 129\u003c\/p\u003e \u003cp\u003e7.1.2 Cascode Bridge Circuit for Input Voltages up to 3\u003ci\u003eV\u003c\/i\u003emax 130\u003c\/p\u003e \u003cp\u003e7.1.3 Cascode Bridge Circuit for Input Voltages up to 4\u003ci\u003eV\u003c\/i\u003emax 132\u003c\/p\u003e \u003cp\u003e7.2 High Input Voltage Monolithic Switching DC–DC Converters 133\u003c\/p\u003e \u003cp\u003e7.2.1 Operation of Cascode DC–DC Converters 133\u003c\/p\u003e \u003cp\u003e7.2.2 Efficiency Characteristics of DC–DC Converters Operating at Input Voltages up to 2\u003ci\u003eV\u003c\/i\u003emax 136\u003c\/p\u003e \u003cp\u003e7.2.3 Efficiency Characteristics of DC–DC Converters Operating at Input Voltages up to 3\u003ci\u003eV\u003c\/i\u003emax 137\u003c\/p\u003e \u003cp\u003e7.3 Summary 138\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 8 Signal Transfer in ICs with Multiple Supply Voltages 139\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 A High-Speed and Low-Power Voltage Interface Circuit 140\u003c\/p\u003e \u003cp\u003e8.2 Voltage Interface Circuit Simulation Results 141\u003c\/p\u003e \u003cp\u003e8.3 Experimental Results 144\u003c\/p\u003e \u003cp\u003e8.4 Summary 146\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 9 Domino Logic with Variable Threshold Voltage Keeper 147\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Standard Domino (SD) Logic Circuits 148\u003c\/p\u003e \u003cp\u003e9.1.1 Operation of Standard Domino Logic Circuits 148\u003c\/p\u003e \u003cp\u003e9.1.2 Noise Immunity, Delay, and Energy Tradeoffs 150\u003c\/p\u003e \u003cp\u003e9.2 Domino Logic with Variable Threshold Voltage Keeper (DVTVK) 153\u003c\/p\u003e \u003cp\u003e9.2.1 Variable Threshold Voltage Keeper 153\u003c\/p\u003e \u003cp\u003e9.2.2 Dynamic Body Bias Generator 155\u003c\/p\u003e \u003cp\u003e9.3 Simulation Results 156\u003c\/p\u003e \u003cp\u003e9.3.1 Multiple-Output Domino Carry Generator with Variable Threshold Voltage Keeper 156\u003c\/p\u003e \u003cp\u003e9.3.1.1 Improved Delay and Power Characteristics with Comparable Noise Immunity 158\u003c\/p\u003e \u003cp\u003e9.3.1.2 Improved Noise Immunity with Comparable Delay or Power Characteristics 160\u003c\/p\u003e \u003cp\u003e9.3.2 Clock-Delayed Domino Logic with Variable Threshold Voltage Keeper 161\u003c\/p\u003e \u003cp\u003e9.3.3 Energy Overhead of the Dynamic Body Bias Generator 163\u003c\/p\u003e \u003cp\u003e9.4 Domino Logic with Forward and Reverse Body Biased Keeper 164\u003c\/p\u003e \u003cp\u003e9.4.1 Clock-Delayed Domino Logic with Forward and Reverse Body Biased Keeper 165\u003c\/p\u003e \u003cp\u003e9.4.2 Technology Scaling Characteristics of the Reverse and Forward Body Bias Techniques Applied to a Keeper Transistor 168\u003c\/p\u003e \u003cp\u003e9.5 Summary 169\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 10 Subthreshold Leakage Current Characteristics of Dynamic Circuits 171\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 State-Dependent Subthreshold Leakage Current Characteristics 172\u003c\/p\u003e \u003cp\u003e10.2 Noise Immunity 177\u003c\/p\u003e \u003cp\u003e10.3 Power and Delay Characteristics in the Active Mode 180\u003c\/p\u003e \u003cp\u003e10.4 Dual Threshold Voltage CMOS Technology 182\u003c\/p\u003e \u003cp\u003e10.5 Summary 186\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 11 Sleep Switch Dual Threshold Voltage Domino Logic 187\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Existing Sleep Mode Circuit Techniques 188\u003c\/p\u003e \u003cp\u003e11.2 Dual Threshold Voltage Domino Logic Employing Sleep Switches 190\u003c\/p\u003e \u003cp\u003e11.3 Simulation Results 191\u003c\/p\u003e \u003cp\u003e11.3.1 Subthreshold Leakage Energy Reduction 193\u003c\/p\u003e \u003cp\u003e11.3.2 Stack Effect in Domino Logic Circuits 194\u003c\/p\u003e \u003cp\u003e11.3.3 Delay and Power Reduction in the Active Mode 197\u003c\/p\u003e \u003cp\u003e11.3.4 Sleep\/Wake-Up Delay and Energy Overhead 197\u003c\/p\u003e \u003cp\u003e11.4 Noise Immunity Compensation 200\u003c\/p\u003e \u003cp\u003e11.5 Summary 204\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 12 Conclusions 205\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eBibliography 211\u003c\/p\u003e \u003cp\u003eIndex 221\u003c\/p\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default Title","offer_id":49402250363223,"sku":"9780470010235","price":98.06,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9780470010235.jpg?v=1730479836","url":"https:\/\/bookcurl.com\/products\/multivoltage-cmos-circuit-design-9780470010235","provider":"Book Curl","version":"1.0","type":"link"}