{"product_id":"mosfet-models-including-bsim3v3-and-bsim4-wiley-ieee-9780471396970","title":"MOSFET Models Including BSIM3v3 and BSIM4 Wiley","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eAn expert guide to understanding and making optimum use of BSIM Used by more chip designers worldwide than any other comparable model, the Berkeley Short-Channel IGFET Model (BSIM) has, over the past few years, established itself as the de facto standard MOSFET SPICE model for circuit simulation and CMOS technology development.\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cb\u003ePreface.\u003c\/b\u003e  \u003cp\u003e\u003cb\u003e1 Modeling Jargons.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 SPICE Simulator and SPICE Model.\u003c\/p\u003e \u003cp\u003e1.2 Numerical Iteration and Convergence.\u003c\/p\u003e \u003cp\u003e1.3 Digital vs. Analog Models.\u003c\/p\u003e \u003cp\u003e1.4 Smoothing Function and Single Equation.\u003c\/p\u003e \u003cp\u003e1.5 Chain Rule.\u003c\/p\u003e \u003cp\u003e1.6 Quasi-Static Approximation.\u003c\/p\u003e \u003cp\u003e1.7 Terminal Charges and Charge Partition.\u003c\/p\u003e \u003cp\u003e1.8 Charge Conservation.\u003c\/p\u003e \u003cp\u003e1.9 Non-Quasi-Static and Quasi-Static \u003ci\u003ey\u003c\/i\u003e-Parameters.\u003c\/p\u003e \u003cp\u003e1.10 Source-Referencing and Inverse Modeling.\u003c\/p\u003e \u003cp\u003e1.11 Physical Model and Table-Lookup Model.\u003c\/p\u003e \u003cp\u003e1.12 Scalable Model and Device Binning.\u003c\/p\u003e \u003cp\u003eReferences and Notes.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Basic Facts About BSIM3.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 What Is and What's Not Implemented in BSIM3.\u003c\/p\u003e \u003cp\u003e2.2 DC Equivalent Circuit Model.\u003c\/p\u003e \u003cp\u003e2.3 BSIM3's ^-Parameters.\u003c\/p\u003e \u003cp\u003e2.4 Large-Signal Equivalent Circuit.\u003c\/p\u003e \u003cp\u003e2.5 Small-Signal Model.\u003c\/p\u003e \u003cp\u003e2.6 Noise Equivalent Circuit.\u003c\/p\u003e \u003cp\u003e2.7 Special Operating Conditions: \u003ci\u003eVDS \u0026lt;\u003c\/i\u003e0, \u003ci\u003eVBS \u0026gt;\u003c\/i\u003e 0, \u003ci\u003eVGS \u0026lt;\u003c\/i\u003e0, or \u003ci\u003eVBD\u003c\/i\u003e \u0026gt; 0\u0026gt;.\u003c\/p\u003e \u003cp\u003eReferences and Notes.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 BSIM3 Parameters.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 List of Parameters According to Function.\u003c\/p\u003e \u003cp\u003e3.2 Alphabetical Glossary of BSIM3 Parameters.\u003c\/p\u003e \u003cp\u003e3.3 Flow Diagram of SPICE Simulation.\u003c\/p\u003e \u003cp\u003eReferences and Notes.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Improvable Areas of BSIM3.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Lack of Robust Non-Quasi-Static Models: Transient Analysis.\u003c\/p\u003e \u003cp\u003e4.2 Problem with the 40\/60 Partition: The \"Killer NOR Gate\".\u003c\/p\u003e \u003cp\u003e4.3 Lack of Channel Resistance (NQS Effect; Small-Signal Analysis).\u003c\/p\u003e \u003cp\u003e4.4 Incorrect Transconductance Dependency on Frequency.\u003c\/p\u003e \u003cp\u003e4.5 Lack of Gate Resistance (and Associated Noise).\u003c\/p\u003e \u003cp\u003e4.6 Lack of Substrate Distributed Resistance (and Associated Noise).\u003c\/p\u003e \u003cp\u003e4.7 Incorrect Source\/Drain Asymmetry at \u003ci\u003eVDS\u003c\/i\u003e = 0.\u003c\/p\u003e \u003cp\u003e4.8 Incorrect \u003ci\u003eCgb\u003c\/i\u003e Behaviors.\u003c\/p\u003e \u003cp\u003e4.9 Capacitances with Wrong Signs.\u003c\/p\u003e \u003cp\u003e4.10 \u003ci\u003eCgg\u003c\/i\u003e Fit and Other Capacitance Issues.\u003c\/p\u003e \u003cp\u003e4.11 Insufficient Noise Modeling (No Excess Short-Channel Thermal Noise).\u003c\/p\u003e \u003cp\u003e4.12 Insufficient Noise Modeling (No Channel-Induced Gate Noise).\u003c\/p\u003e \u003cp\u003e4.13 Incorrect Noise Figure Behavior.\u003c\/p\u003e \u003cp\u003e4.14 Inconsistent Input-Referred Noise Behavior.\u003c\/p\u003e \u003cp\u003e4.15 Possible Negative Transconductances.\u003c\/p\u003e \u003cp\u003e4.16 Lack of GIDL (Gate-Induced Drain Leakage) Current.\u003c\/p\u003e \u003cp\u003e4.17 Incorrect Subthreshold Behaviors.\u003c\/p\u003e \u003cp\u003e4.18 Threshold Voltage Rollup.\u003c\/p\u003e \u003cp\u003e4.19 Problems Associated with a Nonzero RDSW.\u003c\/p\u003e \u003cp\u003e4.20 Other Nuisances.\u003c\/p\u003e \u003cp\u003eReferences and Notes.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5. Improvements in BSIM4.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Introduction.\u003c\/p\u003e \u003cp\u003e5.2 Physical and Electrical Oxide Thicknesses.\u003c\/p\u003e \u003cp\u003e5.3 Strong Inversion Potential for Vertical Nonuniform Doping Profile.\u003c\/p\u003e \u003cp\u003e5.4 Threshold Voltage Modifications.\u003c\/p\u003e \u003cp\u003e5.5 \u003ci\u003eVGST^\u003c\/i\u003e in Moderate Inversion.\u003c\/p\u003e \u003cp\u003e5.6 Drain Conductance Model.\u003c\/p\u003e \u003cp\u003e5.7 Mobility Model.\u003c\/p\u003e \u003cp\u003e5.8 Diode Capacitance.\u003c\/p\u003e \u003cp\u003e5.9 Diode Breakdown.\u003c\/p\u003e \u003cp\u003e5.10 GIDL (Gate-Induced Drain Leakage) Current.\u003c\/p\u003e \u003cp\u003e5.11 Bias-Dependent Drain-Source Resistance.\u003c\/p\u003e \u003cp\u003e5.12 Gate Resistance.\u003c\/p\u003e \u003cp\u003e5.13 Substrate Resistance.\u003c\/p\u003e \u003cp\u003e5.14 Overlap Capacitance.\u003c\/p\u003e \u003cp\u003e5.15 Thermal Noise Models.\u003c\/p\u003e \u003cp\u003e5.16 Flicker Noise Model.\u003c\/p\u003e \u003cp\u003e5.17 Non-Quasi-Static AC Model.\u003c\/p\u003e \u003cp\u003e5.18 Gate Tunneling Currents.\u003c\/p\u003e \u003cp\u003e5.19 Layout-Dependent Parasitics.\u003c\/p\u003e \u003cp\u003eReferences and Notes.\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendixes.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA BSIM3 Equations.\u003c\/p\u003e \u003cp\u003eB Capacitances and Charges for All Bias Conditions.\u003c\/p\u003e \u003cp\u003eC Non-Quasi-Static ^-Parameters.\u003c\/p\u003e \u003cp\u003eD Fringing Capacitance.\u003c\/p\u003e \u003cp\u003eE BSIM3 Non-Quasi-Static Modeling.\u003c\/p\u003e \u003cp\u003eF Noise Figure.\u003c\/p\u003e \u003cp\u003eG BSIM4 Equations.\u003c\/p\u003e \u003cp\u003e\u003cb\u003eIndex.\u003c\/b\u003e\u003c\/p\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default Title","offer_id":49402586169687,"sku":"9780471396970","price":170.06,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9780471396970.jpg?v=1730480861","url":"https:\/\/bookcurl.com\/products\/mosfet-models-including-bsim3v3-and-bsim4-wiley-ieee-9780471396970","provider":"Book Curl","version":"1.0","type":"link"}