{"product_id":"mos-devices-for-lowvoltage-and-lowenergy-applications-9781119107354","title":"MOS Devices for LowVoltage and LowEnergy","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003e\u003cb\u003eHelps readers understand the physics behind MOS devices for low-voltage and low-energy applications\u003c\/b\u003e\u003c\/p\u003e \u003cul\u003e \u003cli\u003eBased on timely published and unpublished work written by expert authors\u003c\/li\u003e \u003cli\u003eDiscusses various promising MOS devices applicable to low-energy environmental and biomedical uses\u003c\/li\u003e \u003cli\u003eDescribes the physical effects (quantum, tunneling) of MOS devices\u003c\/li\u003e \u003cli\u003eDemonstrates the performance of devices, helping readers to choose right devices applicable to an industrial or consumer environment\u003c\/li\u003e \u003cli\u003eAddresses some Ge-based devices and other compound-material-based devices for high-frequency applications and future development of high performance devices.\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003eSeemingly innocuous everyday devices such as smartphones, tablets and services such as on-line gaming or internet keyword searches consume vast amounts of energy. Even when in standby mode, all these devices consume energy. The upcoming ''Internet of Things'' (IoT) is expected to deploy 60 billio\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp\u003ePreface xv\u003c\/p\u003e \u003cp\u003eAcknowledgments xvi\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart I INTRODUCTION TO LOW‐VOLTAGE AND LOW‐ENERGY DEVICES 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Why Are Low‐Voltage and Low‐Energy Devices Desired? 3\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eReferences 4\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 History of Low‐Voltage and Low‐Power Devices 5\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Scaling Scheme and Low‐Voltage Requests 5\u003c\/p\u003e \u003cp\u003e2.2 Silicon‐on‐Insulator Devices and Real History 8\u003c\/p\u003e \u003cp\u003eReferences 10\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 Performance Prospects of Subthreshold Logic Circuits 12\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Introduction 12\u003c\/p\u003e \u003cp\u003e3.2 Subthreshold Logic and its Issues 12\u003c\/p\u003e \u003cp\u003e3.3 Is Subthreshold Logic the Best Solution? 13\u003c\/p\u003e \u003cp\u003eReferences 13\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart II SUMMARY OF PHYSICS OF MODERN SEMICONDUCTOR DEVICES 15\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Overview 17\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eReferences 18\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 Bulk MOSFET 19\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Theoretical Basis of Bulk MOSFET Operation 19\u003c\/p\u003e \u003cp\u003e5.2 Subthreshold Characteristics: “OFF State” 19\u003c\/p\u003e \u003cp\u003e5.2.1 Fundamental Theory 19\u003c\/p\u003e \u003cp\u003e5.2.2 Influence of BTBT Current 23\u003c\/p\u003e \u003cp\u003e5.2.3 Points to Be Remarked 24\u003c\/p\u003e \u003cp\u003e5.3 Post‐Threshold Characteristics: “ON State” 24\u003c\/p\u003e \u003cp\u003e5.3.1 Fundamental Theory 24\u003c\/p\u003e \u003cp\u003e5.3.2 Self‐Heating Effects 26\u003c\/p\u003e \u003cp\u003e5.3.3 Parasitic Bipolar Effects 27\u003c\/p\u003e \u003cp\u003e5.4 Comprehensive Summary of Short‐Channel Effects 27\u003c\/p\u003e \u003cp\u003eReferences 28\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 SOI MOSFET 29\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Partially Depleted Silicon‐on‐Insulator Metal Oxide Semiconductor Field‐Effect Transistors 29\u003c\/p\u003e \u003cp\u003e6.2 Fully Depleted (FD) SOI MOSFET 30\u003c\/p\u003e \u003cp\u003e6.2.1 Subthreshold Characteristics 30\u003c\/p\u003e \u003cp\u003e6.2.2 Post‐Threshold Characteristics 36\u003c\/p\u003e \u003cp\u003e6.2.3 Comprehensive Summary of Short‐Channel Effects 41\u003c\/p\u003e \u003cp\u003e6.3 Accumulation‐Mode (AM) SOI MOSFET 41\u003c\/p\u003e \u003cp\u003e6.3.1 Aspects of Device Structure 41\u003c\/p\u003e \u003cp\u003e6.3.2 Subthreshold Characteristics 42\u003c\/p\u003e \u003cp\u003e6.3.3 Drain Current Component (I) – Body Current (ID,body) 43\u003c\/p\u003e \u003cp\u003e6.3.4 Drain Current Component (II) – Surface Accumulation\u003c\/p\u003e \u003cp\u003eLayer Current (ID,acc) 45\u003c\/p\u003e \u003cp\u003e6.3.5 Optional Discussions on the Accumulation Mode SOI MOSFET 45\u003c\/p\u003e \u003cp\u003e6.4 FinFET and Triple‐Gate FET 46\u003c\/p\u003e \u003cp\u003e6.4.1 Introduction 46\u003c\/p\u003e \u003cp\u003e6.4.2 Device Structures and Simulations 46\u003c\/p\u003e \u003cp\u003e6.4.3 Results and Discussion 47\u003c\/p\u003e \u003cp\u003e6.4.4 Summary 49\u003c\/p\u003e \u003cp\u003e6.5 Gate‐all‐Around MOSFET 50\u003c\/p\u003e \u003cp\u003eReferences 51\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Tunnel Field‐Effect Transistors (TFETs) 53\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Overview 53\u003c\/p\u003e \u003cp\u003e7.2 Model of Double‐Gate Lateral Tunnel FET and Device Performance Perspective 53\u003c\/p\u003e \u003cp\u003e7.2.1 Introduction 53\u003c\/p\u003e \u003cp\u003e7.2.2 Device Modeling 54\u003c\/p\u003e \u003cp\u003e7.2.3 Numerical Calculation Results and Discussion 61\u003c\/p\u003e \u003cp\u003e7.2.4 Summary 65\u003c\/p\u003e \u003cp\u003e7.3 Model of Vertical Tunnel FET and Aspects of its Characteristics 65\u003c\/p\u003e \u003cp\u003e7.3.1 Introduction 65\u003c\/p\u003e \u003cp\u003e7.3.2 Device Structure and Model Concept 65\u003c\/p\u003e \u003cp\u003e7.3.3 Comparing Model Results with TCAD Results 69\u003c\/p\u003e \u003cp\u003e7.3.4 Consideration of the Impact of Tunnel Dimensionality on Drivability 72\u003c\/p\u003e \u003cp\u003e7.3.5 Summary 75\u003c\/p\u003e \u003cp\u003e7.4 Appendix Integration of Eqs. (7.14)–(7.16) 76\u003c\/p\u003e \u003cp\u003eReferences 78\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart III POTENTIAL OF CONVENTIONAL BULK MOSFETs 81\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 Performance Evaluation of Analog Circuits with Deep Submicrometer MOSFETs in the Subthreshold Regime of Operation 83\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Introduction 83\u003c\/p\u003e \u003cp\u003e8.2 Subthreshold Operation and Device Simulation 84\u003c\/p\u003e \u003cp\u003e8.3 Model Description 85\u003c\/p\u003e \u003cp\u003e8.4 Results 86\u003c\/p\u003e \u003cp\u003e8.5 Summary 90\u003c\/p\u003e \u003cp\u003eReferences 90\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 Impact of Halo Doping on the Subthreshold Performance of Deep‐Submicrometer CMOS Devices and Circuits for Ultralow Power Analog\/Mixed‐Signal Applications 91\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Introduction 91\u003c\/p\u003e \u003cp\u003e9.2 Device Structures and Simulation 92\u003c\/p\u003e \u003cp\u003e9.3 Subthreshold Operation 93\u003c\/p\u003e \u003cp\u003e9.4 Device Optimization for Subthreshold Analog Operation 95\u003c\/p\u003e \u003cp\u003e9.5 Subthreshold Analog Circuit Performance 98\u003c\/p\u003e \u003cp\u003e9.6 CMOS Amplifiers with Large Geometry Devices 105\u003c\/p\u003e \u003cp\u003e9.7 Summary 106\u003c\/p\u003e \u003cp\u003eReferences 107\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 Study of the Subthreshold Performance and the Effect of Channel Engineering on Deep Submicron Single‐Stage CMOS Amplifiers 108\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Introduction 108\u003c\/p\u003e \u003cp\u003e10.2 Circuit Description 108\u003c\/p\u003e \u003cp\u003e10.3 Device Structure and Simulation 110\u003c\/p\u003e \u003cp\u003e10.4 Results and Discussion 110\u003c\/p\u003e \u003cp\u003e10.5 PTAT as a Temperature Sensor 116\u003c\/p\u003e \u003cp\u003e10.6 Summary 116\u003c\/p\u003e \u003cp\u003eReferences 116\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 Subthreshold Performance of Dual‐Material Gate CMOS Devices and Circuits for Ultralow Power Analog\/Mixed‐Signal Applications 117\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Introduction 117\u003c\/p\u003e \u003cp\u003e11.2 Device Structure and Simulation 118\u003c\/p\u003e \u003cp\u003e11.3 Results and Discussion 120\u003c\/p\u003e \u003cp\u003e11.4 Summary 126\u003c\/p\u003e \u003cp\u003eReferences 127\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12 Performance Prospect of Low‐Power Bulk MOSFETs 128\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eReference 129\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart IV POTENTIAL OF FULLY‐DEPLETED SOI MOSFETs 131\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e13 Demand for High‐Performance SOI Devices 133\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e14 Demonstration of 100 nm Gate SOI CMOS with a Thin Buried Oxide Layer and its Impact on Device Technology 134\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e14.1 Introduction 134\u003c\/p\u003e \u003cp\u003e14.2 Device Design Concept for 100 nm Gate SOI CMOS 134\u003c\/p\u003e \u003cp\u003e14.3 Device Fabrication 136\u003c\/p\u003e \u003cp\u003e14.4 Performance of 100‐nm‐ and 85‐nm Gate Devices 137\u003c\/p\u003e \u003cp\u003e14.4.1 Threshold and Subthreshold Characteristics 137\u003c\/p\u003e \u003cp\u003e14.4.2 Drain Current (ID)‐Drain Voltage (VD) and ID‐Gate Voltage (VG) Characteristics of 100‐nm‐Gate MOSFET\/SIMOX 138\u003c\/p\u003e \u003cp\u003e14.4.3 ID–VD and ID–VG Characteristics of 85‐nm‐Gate MOSFET\/SIMOX 142\u003c\/p\u003e \u003cp\u003e14.4.4 Switching Performance 142\u003c\/p\u003e \u003cp\u003e14.5 Discussion 142\u003c\/p\u003e \u003cp\u003e14.5.1 Threshold Voltage Balance in Ultrathin CMOS\/SOI Devices 142\u003c\/p\u003e \u003cp\u003e14.6 Summary 144\u003c\/p\u003e \u003cp\u003eReferences 145\u003c\/p\u003e \u003cp\u003e\u003cb\u003e15 Discussion on Design Feasibility and Prospect of High‐Performance Sub‐50 nm Channel Single‐Gate SOI MOSFET Based on the ITRS Roadmap 147\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e15.1 Introduction 147\u003c\/p\u003e \u003cp\u003e15.2 Device Structure and Simulations 148\u003c\/p\u003e \u003cp\u003e15.3 Proposed Model for Minimum Channel Length 149\u003c\/p\u003e \u003cp\u003e15.3.1 Minimum Channel Length Model Constructed using Extract A 149\u003c\/p\u003e \u003cp\u003e15.3.2 Minimum Channel Length Model Constructed using Extract B 150\u003c\/p\u003e \u003cp\u003e15.4 Performance Prospects of Scaled SOI MOSFETs 152\u003c\/p\u003e \u003cp\u003e15.4.1 Dynamic Operation Characteristics of Scaled SG SOI MOSFETs 152\u003c\/p\u003e \u003cp\u003e15.4.2 Tradeoff and Optimization of Standby Power Consumption and Dynamic Operation 157\u003c\/p\u003e \u003cp\u003e15.5 Summary 162\u003c\/p\u003e \u003cp\u003eReferences 162\u003c\/p\u003e \u003cp\u003e\u003cb\u003e16 Performance Prospects of Fully Depleted SOI MOSFET‐Based Diodes Applied to Schenkel Circuits for RF‐ID Chips 164\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e16.1 Introduction 164\u003c\/p\u003e \u003cp\u003e16.2 Remaining Issues with Conventional Schenkel Circuits and an Advanced Proposal 165\u003c\/p\u003e \u003cp\u003e16.3 Simulation‐Based Consideration of RF Performance of SOI‐QD 172\u003c\/p\u003e \u003cp\u003e16.4 Summary 176\u003c\/p\u003e \u003cp\u003e16.5 Appendix: A Simulation Model for Minority Carrier Lifetime 177\u003c\/p\u003e \u003cp\u003e16.6 Appendix: Design Guideline for SOI‐QDs 177\u003c\/p\u003e \u003cp\u003eReferences 178\u003c\/p\u003e \u003cp\u003e\u003cb\u003e17 The Potential and the Drawbacks of Underlap Single‐Gate Ultrathin SOI MOSFET 180\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e17.1 Introduction 180\u003c\/p\u003e \u003cp\u003e17.2 Simulations 181\u003c\/p\u003e \u003cp\u003e17.3 Results and Discussion 183\u003c\/p\u003e \u003cp\u003e17.3.1 DC Characteristics and Switching Performance: Device A 183\u003c\/p\u003e \u003cp\u003e17.3.2 RF Analog Characteristics: Device A 184\u003c\/p\u003e \u003cp\u003e17.3.3 Impact of High‐κ Gate Dielectric on Performance of USU SOI MOSFET Devices: Devices B and C 185\u003c\/p\u003e \u003cp\u003e17.3.4 Impact of Simulation Model on Simulation Results 189\u003c\/p\u003e \u003cp\u003e17.4 Summary 192\u003c\/p\u003e \u003cp\u003eReferences 192\u003c\/p\u003e \u003cp\u003e\u003cb\u003e18 Practical Source\/Drain Diffusion and Body Doping Layouts for High‐Performance and Low‐Energy Triple‐Gate SOI MOSFETs 194\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e18.1 Introduction 194\u003c\/p\u003e \u003cp\u003e18.2 Device Structures and Simulation Model 195\u003c\/p\u003e \u003cp\u003e18.3 Results and Discussion 196\u003c\/p\u003e \u003cp\u003e18.3.1 Impact of S\/D‐Underlying Layer on ION, IOFF, and Subthreshold Swing 196\u003c\/p\u003e \u003cp\u003e18.3.2 Tradeoff of Short‐Channel Effects and Drivability 196\u003c\/p\u003e \u003cp\u003e18.4 Summary 201\u003c\/p\u003e \u003cp\u003eReferences 201\u003c\/p\u003e \u003cp\u003e\u003cb\u003e19 Gate Field Engineering and Source\/Drain Diffusion Engineering for High‐Performance Si Wire Gate‐All‐Around MOSFET and Low‐Power Strategy in a Sub‐30 nm‐Channel Regime 203\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e19.1 Introduction 203\u003c\/p\u003e \u003cp\u003e19.2 Device Structures Assumed and Physical Parameters 204\u003c\/p\u003e \u003cp\u003e19.3 Simulation Results and Discussion 206\u003c\/p\u003e \u003cp\u003e19.3.1 Performance of Sub‐30 nm‐Channel Devices and Aspects of Device Characteristics 206\u003c\/p\u003e \u003cp\u003e19.3.2 Impact of Cross‐Section of Si Wire on Short‐Channel Effects and Drivability 212\u003c\/p\u003e \u003cp\u003e19.3.3 Minimizing Standby Power Consumption of GAA SOI MOSFET 216\u003c\/p\u003e \u003cp\u003e19.3.4 Prospective Switching Speed Performance of GAA SOI MOSFET 217\u003c\/p\u003e \u003cp\u003e19.3.5 Parasitic Resistance Issues of GAA Wire MOSFETs 218\u003c\/p\u003e \u003cp\u003e19.3.6 Proposal for Possible GAA Wire MOSFET Structure 220\u003c\/p\u003e \u003cp\u003e19.4 Summary 221\u003c\/p\u003e \u003cp\u003e19.5 Appendix: Brief Description of Physical Models in Simulations 221\u003c\/p\u003e \u003cp\u003eReferences 225\u003c\/p\u003e \u003cp\u003e\u003cb\u003e20 Impact of Local High‐κ Insulator on Drivability and Standby Power of Gate‐All‐Around SOI MOSFET 228\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e20.1 Introduction 228\u003c\/p\u003e \u003cp\u003e20.2 Device Structure and Simulations 229\u003c\/p\u003e \u003cp\u003e20.3 Results and Discussion 230\u003c\/p\u003e \u003cp\u003e20.3.1 Device Characteristics of GAA Devices with Graded‐Profile Junctions 230\u003c\/p\u003e \u003cp\u003e20.3.2 Device Characteristics of GAA Devices with Abrupt Junctions 235\u003c\/p\u003e \u003cp\u003e20.3.3 Behaviors of Drivability and Off‐Current 237\u003c\/p\u003e \u003cp\u003e20.3.4 Dynamic Performance of Devices with Graded‐Profile Junctions 239\u003c\/p\u003e \u003cp\u003e20.4 Summary 239\u003c\/p\u003e \u003cp\u003eReferences 240\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart V POTENTIAL OF PARTIALLY DEPLETED SOI MOSFETs 241\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e21 Proposal for Cross‐Current Tetrode (XCT) SOI MOSFETs: A 60 dB Single‐Stage CMOS Amplifier Using High‐Gain Cross‐Current Tetrode MOSFET\/SIMOX 243\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e21.1 Introduction 243\u003c\/p\u003e \u003cp\u003e21.2 Device Fabrication 244\u003c\/p\u003e \u003cp\u003e21.3 Device Characteristics 245\u003c\/p\u003e \u003cp\u003e21.4 Performance of CMOS Amplifier 247\u003c\/p\u003e \u003cp\u003e21.5 Summary 249\u003c\/p\u003e \u003cp\u003eReferences 249\u003c\/p\u003e \u003cp\u003e\u003cb\u003e22 Device Model of the XCT‐SOI MOSFET and Scaling Scheme 250\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e22.1 Introduction 250\u003c\/p\u003e \u003cp\u003e22.2 Device Structure and Assumptions for Modeling 251\u003c\/p\u003e \u003cp\u003e22.2.1 Device Structure and Features of XCT Device 251\u003c\/p\u003e \u003cp\u003e22.2.2 Basic Assumptions for Device Modeling 253\u003c\/p\u003e \u003cp\u003e22.2.3 Derivation of Model Equations 254\u003c\/p\u003e \u003cp\u003e22.3 Results and Discussion 258\u003c\/p\u003e \u003cp\u003e22.3.1 Measured Characteristics of XCT Devices 258\u003c\/p\u003e \u003cp\u003e22.4 Design Guidelines 261\u003c\/p\u003e \u003cp\u003e22.4.1 Drivability Control 261\u003c\/p\u003e \u003cp\u003e22.4.2 Scaling Issues 262\u003c\/p\u003e \u003cp\u003e22.4.3 Potentiality of Low‐Energy Operation of XCT CMOS Devices 265\u003c\/p\u003e \u003cp\u003e22.5 Summary 267\u003c\/p\u003e \u003cp\u003e22.6 Appendix: Calculation of MOSFET Channel Current 267\u003c\/p\u003e \u003cp\u003e22.7 Appendix: Basic Condition for Drivability Control 271\u003c\/p\u003e \u003cp\u003eReferences 271\u003c\/p\u003e \u003cp\u003e\u003cb\u003e23 Low‐Power Multivoltage Reference Circuit Using XCT‐SOI MOSFET 274\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e23.1 Introduction 274\u003c\/p\u003e \u003cp\u003e23.2 Device Structure and Assumptions for Simulations 274\u003c\/p\u003e \u003cp\u003e23.2.1 Device Structure and Features 274\u003c\/p\u003e \u003cp\u003e23.2.2 Assumptions for Simulations 277\u003c\/p\u003e \u003cp\u003e23.3 Proposal for Voltage Reference Circuits and Simulation Results 278\u003c\/p\u003e \u003cp\u003e23.3.1 Two‐Reference Voltage Circuit 278\u003c\/p\u003e \u003cp\u003e23.3.2 Three‐Reference Voltage Circuit 283\u003c\/p\u003e \u003cp\u003e23.4 Summary 283\u003c\/p\u003e \u003cp\u003eReferences 284\u003c\/p\u003e \u003cp\u003e\u003cb\u003e24 Low‐Energy Operation Mechanisms for XCT‐SOI CMOS Devices: Prospects for a Sub‐20 nm Regime 285\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e24.1 Introduction 285\u003c\/p\u003e \u003cp\u003e24.2 Device Structure and Assumptions for Modeling 286\u003c\/p\u003e \u003cp\u003e24.3 Circuit Simulation Results of SOI CMOS and XCT‐SOI CMOS 288\u003c\/p\u003e \u003cp\u003e24.4 Further Scaling Potential of XCT‐SOI MOSFET 291\u003c\/p\u003e \u003cp\u003e24.5 Performance Expected from the Scaled XCT‐SOI MOSFET 292\u003c\/p\u003e \u003cp\u003e24.6 Summary 296\u003c\/p\u003e \u003cp\u003eReferences 296\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart VI QUANTUM EFFECTS AND APPLICATIONS – 1 297\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e25 Overview 299\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eReferences 299\u003c\/p\u003e \u003cp\u003e\u003cb\u003e26 Si Resonant Tunneling MOS Transistor 301\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e26.1 Introduction 301\u003c\/p\u003e \u003cp\u003e26.2 Configuration of SRTMOST 302\u003c\/p\u003e \u003cp\u003e26.2.1 Structure and Electrostatic Potential 302\u003c\/p\u003e \u003cp\u003e26.2.2 Operation Principle and Subthreshold Characteristics 304\u003c\/p\u003e \u003cp\u003e26.3 Device Performance of SRTMOST 307\u003c\/p\u003e \u003cp\u003e26.3.1 Transistor Characteristics of SRTMOST 307\u003c\/p\u003e \u003cp\u003e26.3.2 Logic Circuit Using SRTMOST 310\u003c\/p\u003e \u003cp\u003e26.4 Summary 312\u003c\/p\u003e \u003cp\u003eReferences 312\u003c\/p\u003e \u003cp\u003e\u003cb\u003e27 Tunneling Dielectric Thin‐Film Transistor 314\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e27.1 Introduction 314\u003c\/p\u003e \u003cp\u003e27.2 Fundamental Device Structure 315\u003c\/p\u003e \u003cp\u003e27.3 Experiment 315\u003c\/p\u003e \u003cp\u003e27.3.1 Experimental Method 315\u003c\/p\u003e \u003cp\u003e27.3.2 Calculation Method 317\u003c\/p\u003e \u003cp\u003e27.4 Results and Discussion 320\u003c\/p\u003e \u003cp\u003e27.4.1 Evaluation of SiNx Film 320\u003c\/p\u003e \u003cp\u003e27.4.2 Characteristics of the TDTFT 320\u003c\/p\u003e \u003cp\u003e27.4.3 TFT Performance at Low Temperatures 324\u003c\/p\u003e \u003cp\u003e27.4.4 TFT Performance at High Temperatures 324\u003c\/p\u003e \u003cp\u003e27.4.5 Suppression of the Hump Effect by the TDTFT 330\u003c\/p\u003e \u003cp\u003e27.5 Summary 336\u003c\/p\u003e \u003cp\u003eReferences 336\u003c\/p\u003e \u003cp\u003e\u003cb\u003e28 Proposal for a Tunnel‐Barrier Junction (TBJ) MOSFET 339\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e28.1 Introduction 339\u003c\/p\u003e \u003cp\u003e28.2 Device Structure and Model 339\u003c\/p\u003e \u003cp\u003e28.3 Calculation Results 340\u003c\/p\u003e \u003cp\u003e28.4 Summary 343\u003c\/p\u003e \u003cp\u003eReferences 343\u003c\/p\u003e \u003cp\u003e\u003cb\u003e29 Performance Prediction of SOI Tunneling‐Barrier‐Junction MOSFET 344\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e29.1 Introduction 344\u003c\/p\u003e \u003cp\u003e29.2 Simulation Model 345\u003c\/p\u003e \u003cp\u003e29.3 Simulation Results and Discussion 349\u003c\/p\u003e \u003cp\u003e29.3.1 Fundamental Properties of TBJ MOSFET 349\u003c\/p\u003e \u003cp\u003e29.3.2 Optimization of Device Parameters and Materials 349\u003c\/p\u003e \u003cp\u003e29.4 Summary 357\u003c\/p\u003e \u003cp\u003eReferences 357\u003c\/p\u003e \u003cp\u003e\u003cb\u003e30 Physics‐Based Model for TBJ‐MOSFETs and High‐Frequency Performance Prospects 358\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e30.1 Introduction 358\u003c\/p\u003e \u003cp\u003e30.2 Device Structure and Device Model for Simulations 359\u003c\/p\u003e \u003cp\u003e30.3 Simulation Results and Discussion 360\u003c\/p\u003e \u003cp\u003e30.3.1 Current Drivability 361\u003c\/p\u003e \u003cp\u003e30.3.2 Threshold Voltage Issue 362\u003c\/p\u003e \u003cp\u003e30.3.3 Subthreshold Characteristics 363\u003c\/p\u003e \u003cp\u003e30.3.4 Radio‐Frequency Characteristics 363\u003c\/p\u003e \u003cp\u003e30.4 Summary 365\u003c\/p\u003e \u003cp\u003eReferences 365\u003c\/p\u003e \u003cp\u003e\u003cb\u003e31 Low‐Power High‐Temperature‐Operation‐Tolerant (HTOT) SOI MOSFET 367\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e31.1 Introduction 367\u003c\/p\u003e \u003cp\u003e31.2 Device Structure and Simulations 368\u003c\/p\u003e \u003cp\u003e31.3 Results and Discussion 371\u003c\/p\u003e \u003cp\u003e31.3.1 Room‐Temperature Characteristics 371\u003c\/p\u003e \u003cp\u003e31.3.2 High‐Temperature Characteristics 373\u003c\/p\u003e \u003cp\u003e31.4 Summary 377\u003c\/p\u003e \u003cp\u003eReferences 379\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart VII QUANTUM EFFECTS AND APPLICATIONS – 2 381\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e32 Overview of Tunnel Field‐Effect Transistor 383\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eReferences 385\u003c\/p\u003e \u003cp\u003e\u003cb\u003e33 Impact of a Spacer Dielectric and a Gate Overlap\/Underlap on the Device Performance of a Tunnel Field‐Effect Transistor 386\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e33.1 Introduction 386\u003c\/p\u003e \u003cp\u003e33.2 Device Structure and Simulation 387\u003c\/p\u003e \u003cp\u003e33.3 Results and Discussion 387\u003c\/p\u003e \u003cp\u003e33.3.1 Effects of Variation in the Spacer Dielectric Constant 387\u003c\/p\u003e \u003cp\u003e33.3.2 Effects of Variation in the Spacer Width 391\u003c\/p\u003e \u003cp\u003e33.3.3 Effects of Variation in the Source Doping Concentration 392\u003c\/p\u003e \u003cp\u003e33.3.4 Effects of a Gate‐Source Overlap 394\u003c\/p\u003e \u003cp\u003e33.3.5 Effects of a Gate‐Channel Underlap 394\u003c\/p\u003e \u003cp\u003e33.4 Summary 397\u003c\/p\u003e \u003cp\u003eReferences 397\u003c\/p\u003e \u003cp\u003e\u003cb\u003e34 The Impact of a Fringing Field on the Device Performance of a P‐Channel Tunnel Field‐Effect Transistor with a High‐κ Gate Dielectric 399\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e34.1 Introduction 399\u003c\/p\u003e \u003cp\u003e34.2 Device Structure and Simulation 399\u003c\/p\u003e \u003cp\u003e34.3 Results and Discussion 400\u003c\/p\u003e \u003cp\u003e34.3.1 Effects of Variation in the Gate Dielectric Constant 400\u003c\/p\u003e \u003cp\u003e34.3.2 Effects of Variation in the Spacer Dielectric Constant 408\u003c\/p\u003e \u003cp\u003e34.4 Summary 410\u003c\/p\u003e \u003cp\u003eReferences 410\u003c\/p\u003e \u003cp\u003e\u003cb\u003e35 Impact of a Spacer‐Drain Overlap on the Characteristics of a Silicon Tunnel Field‐Effect Transistor Based on Vertical Tunneling 412\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e35.1 Introduction 412\u003c\/p\u003e \u003cp\u003e35.2 Device Structure and Process Steps 413\u003c\/p\u003e \u003cp\u003e35.3 Simulation Setup 414\u003c\/p\u003e \u003cp\u003e35.4 Results and Discussion 416\u003c\/p\u003e \u003cp\u003e35.4.1 Impact of Variation in the Spacer‐Drain Overlap 416\u003c\/p\u003e \u003cp\u003e35.4.2 Influence of Drain on the Device Characteristics 424\u003c\/p\u003e \u003cp\u003e35.4.3 Impact of Scaling 426\u003c\/p\u003e \u003cp\u003e35.5 Summary 429\u003c\/p\u003e \u003cp\u003eReferences 430\u003c\/p\u003e \u003cp\u003e\u003cb\u003e36 Gate‐on‐Germanium Source Tunnel Field‐Effect Transistor Enabling Sub‐0.5‐V Operation 431\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e36.1 Introduction 431\u003c\/p\u003e \u003cp\u003e36.2 Proposed Device Structure 431\u003c\/p\u003e \u003cp\u003e36.3 Simulation Setup 432\u003c\/p\u003e \u003cp\u003e36.4 Results and Discussion 434\u003c\/p\u003e \u003cp\u003e36.4.1 Device Characteristics 434\u003c\/p\u003e \u003cp\u003e36.4.2 Effects of Different Structural Parameters 435\u003c\/p\u003e \u003cp\u003e36.4.3 Optimization of Different Structural Parameters 436\u003c\/p\u003e \u003cp\u003e36.5 Summary 445\u003c\/p\u003e \u003cp\u003eReferences 445\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart VIII PROSPECTS OF LOW‐ENERGY DEVICE TECHNOLOLGY AND APPLICATIONS 447\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e37 Performance Comparison of Modern Devices 449\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eReferences 450\u003c\/p\u003e \u003cp\u003e\u003cb\u003e38 Emerging Device Technology and the Future of MOSFET 452\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e38.1 Studies to Realize High‐Performance MOSFETs based on Unconventional Materials 452\u003c\/p\u003e \u003cp\u003e38.2 Challenging Studies to Realize High‐Performance MOSFETs based on the Nonconventional Doctrine 453\u003c\/p\u003e \u003cp\u003eReferences 454\u003c\/p\u003e \u003cp\u003e\u003cb\u003e39 How Devices Are and Should Be Applied to Circuits 456\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e39.1 Past Approach 456\u003c\/p\u003e \u003cp\u003e39.2 Latest Studies 456\u003c\/p\u003e \u003cp\u003eReferences 457\u003c\/p\u003e \u003cp\u003e\u003cb\u003e40 Prospects for Low‐Energy Device Technology and Applications 458\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eReferences 459\u003c\/p\u003e \u003cp\u003eBibliography 460\u003c\/p\u003e \u003cp\u003eIndex 463\u003c\/p\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default Title","offer_id":49406986813783,"sku":"9781119107354","price":114.9,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9781119107354.jpg?v=1730497796","url":"https:\/\/bookcurl.com\/products\/mos-devices-for-lowvoltage-and-lowenergy-applications-9781119107354","provider":"Book Curl","version":"1.0","type":"link"}