{"product_id":"learning-in-energyefficient-neuromorphic-computing-algorithm-and-architecture-codesign-9781119507383","title":"Learning in EnergyEfficient Neuromorphic","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003e\u003cb\u003eExplains current co-design and co-optimization methodologies for building hardware neural networks and algorithms for machine learning applications\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eThis book focuses on how to build energy-efficient hardware for neural networks with learning capabilitiesand provides co-design and co-optimization methodologies for building hardware neural networks that can learn. Presenting a complete picture from high-level algorithm to low-level implementation details, \u003ci\u003eLearning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design\u003c\/i\u003e also covers many fundamentals and essentials in neural networks (e.g., deep learning), as well as hardware implementation of neural networks.\u003c\/p\u003e \u003cp\u003eThe book begins with an overview of neural networks. It then discusses algorithms for utilizing and training rate-based artificial neural networks. Next comes an introduction to various options for executing neural networks, ranging from general-purpose processors to specialized\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp\u003ePreface xi\u003c\/p\u003e \u003cp\u003eAcknowledgment xix\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Overview 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 History of Neural Networks 1\u003c\/p\u003e \u003cp\u003e1.2 Neural Networks in Software 2\u003c\/p\u003e \u003cp\u003e1.2.1 Artificial Neural Network 2\u003c\/p\u003e \u003cp\u003e1.2.2 Spiking Neural Network 3\u003c\/p\u003e \u003cp\u003e1.3 Need for Neuromorphic Hardware 3\u003c\/p\u003e \u003cp\u003e1.4 Objectives and Outlines of the Book 5\u003c\/p\u003e \u003cp\u003eReferences 8\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Fundamentals and Learning of Artificial Neural Networks 11\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Operational Principles of Artificial Neural Networks 11\u003c\/p\u003e \u003cp\u003e2.1.1 Inference 11\u003c\/p\u003e \u003cp\u003e2.1.2 Learning 13\u003c\/p\u003e \u003cp\u003e2.2 Neural Network Based Machine Learning 16\u003c\/p\u003e \u003cp\u003e2.2.1 Supervised Learning 17\u003c\/p\u003e \u003cp\u003e2.2.2 Reinforcement Learning 20\u003c\/p\u003e \u003cp\u003e2.2.3 Unsupervised Learning 22\u003c\/p\u003e \u003cp\u003e2.2.4 Case Study: Action-Dependent Heuristic Dynamic Programming 23\u003c\/p\u003e \u003cp\u003e2.2.4.1 Actor-Critic Networks 24\u003c\/p\u003e \u003cp\u003e2.2.4.2 On-Line Learning Algorithm 25\u003c\/p\u003e \u003cp\u003e2.2.4.3 Virtual Update Technique 27\u003c\/p\u003e \u003cp\u003e2.3 Network Topologies 31\u003c\/p\u003e \u003cp\u003e2.3.1 Fully Connected Neural Networks 31\u003c\/p\u003e \u003cp\u003e2.3.2 Convolutional Neural Networks 32\u003c\/p\u003e \u003cp\u003e2.3.3 Recurrent Neural Networks 35\u003c\/p\u003e \u003cp\u003e2.4 Dataset and Benchmarks 38\u003c\/p\u003e \u003cp\u003e2.5 Deep Learning 41\u003c\/p\u003e \u003cp\u003e2.5.1 Pre-Deep-Learning Era 41\u003c\/p\u003e \u003cp\u003e2.5.2 The Rise of Deep Learning 41\u003c\/p\u003e \u003cp\u003e2.5.3 Deep Learning Techniques 42\u003c\/p\u003e \u003cp\u003e2.5.3.1 Performance-Improving Techniques 42\u003c\/p\u003e \u003cp\u003e2.5.3.2 Energy-Efficiency-Improving Techniques 46\u003c\/p\u003e \u003cp\u003e2.5.4 Deep Neural Network Examples 50\u003c\/p\u003e \u003cp\u003eReferences 53\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 Artificial Neural Networks in Hardware 61\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Overview 61\u003c\/p\u003e \u003cp\u003e3.2 General-Purpose Processors 62\u003c\/p\u003e \u003cp\u003e3.3 Digital Accelerators 63\u003c\/p\u003e \u003cp\u003e3.3.1 A Digital ASIC Approach 63\u003c\/p\u003e \u003cp\u003e3.3.1.1 Optimization on Data Movement and Memory Access 63\u003c\/p\u003e \u003cp\u003e3.3.1.2 Scaling Precision 71\u003c\/p\u003e \u003cp\u003e3.3.1.3 Leveraging Sparsity 76\u003c\/p\u003e \u003cp\u003e3.3.2 FPGA-Based Accelerators 80\u003c\/p\u003e \u003cp\u003e3.4 Analog\/Mixed-Signal Accelerators 82\u003c\/p\u003e \u003cp\u003e3.4.1 Neural Networks in Conventional Integrated Technology 82\u003c\/p\u003e \u003cp\u003e3.4.1.1 In\/Near-Memory Computing 82\u003c\/p\u003e \u003cp\u003e3.4.1.2 Near-Sensor Computing 85\u003c\/p\u003e \u003cp\u003e3.4.2 Neural Network Based on Emerging Non-volatile Memory 88\u003c\/p\u003e \u003cp\u003e3.4.2.1 Crossbar as a Massively Parallel Engine 89\u003c\/p\u003e \u003cp\u003e3.4.2.2 Learning in a Crossbar 91\u003c\/p\u003e \u003cp\u003e3.4.3 Optical Accelerator 93\u003c\/p\u003e \u003cp\u003e3.5 Case Study: An Energy-Efficient Accelerator for Adaptive Dynamic Programming 94\u003c\/p\u003e \u003cp\u003e3.5.1 Hardware Architecture 95\u003c\/p\u003e \u003cp\u003e3.5.1.1 On-Chip Memory 95\u003c\/p\u003e \u003cp\u003e3.5.1.2 Datapath 97\u003c\/p\u003e \u003cp\u003e3.5.1.3 Controller 99\u003c\/p\u003e \u003cp\u003e3.5.2 Design Examples 101\u003c\/p\u003e \u003cp\u003eReferences 108\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Operational Principles and Learning in Spiking Neural Networks 119\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Spiking Neural Networks 119\u003c\/p\u003e \u003cp\u003e4.1.1 Popular Spiking Neuron Models 120\u003c\/p\u003e \u003cp\u003e4.1.1.1 Hodgkin-Huxley Model 120\u003c\/p\u003e \u003cp\u003e4.1.1.2 Leaky Integrate-and-Fire Model 121\u003c\/p\u003e \u003cp\u003e4.1.1.3 Izhikevich Model 121\u003c\/p\u003e \u003cp\u003e4.1.2 Information Encoding 122\u003c\/p\u003e \u003cp\u003e4.1.3 Spiking Neuron versus Non-Spiking Neuron 123\u003c\/p\u003e \u003cp\u003e4.2 Learning in Shallow SNNs 124\u003c\/p\u003e \u003cp\u003e4.2.1 ReSuMe 124\u003c\/p\u003e \u003cp\u003e4.2.2 Tempotron 125\u003c\/p\u003e \u003cp\u003e4.2.3 Spike-Timing-Dependent Plasticity 127\u003c\/p\u003e \u003cp\u003e4.2.4 Learning Through Modulating Weight-Dependent STDP in Two-Layer Neural Networks 131\u003c\/p\u003e \u003cp\u003e4.2.4.1 Motivations 131\u003c\/p\u003e \u003cp\u003e4.2.4.2 Estimating Gradients with Spike Timings 131\u003c\/p\u003e \u003cp\u003e4.2.4.3 Reinforcement Learning Example 135\u003c\/p\u003e \u003cp\u003e4.3 Learning in Deep SNNs 146\u003c\/p\u003e \u003cp\u003e4.3.1 SpikeProp 146\u003c\/p\u003e \u003cp\u003e4.3.2 Stack of Shallow Networks 147\u003c\/p\u003e \u003cp\u003e4.3.3 Conversion from ANNs 148\u003c\/p\u003e \u003cp\u003e4.3.4 Recent Advances in Backpropagation for Deep SNNs 150\u003c\/p\u003e \u003cp\u003e4.3.5 Learning Through Modulating Weight-Dependent STDP in Multilayer Neural Networks 151\u003c\/p\u003e \u003cp\u003e4.3.5.1 Motivations 151\u003c\/p\u003e \u003cp\u003e4.3.5.2 Learning Through Modulating Weight-Dependent STDP 151\u003c\/p\u003e \u003cp\u003e4.3.5.3 Simulation Results 158\u003c\/p\u003e \u003cp\u003eReferences 167\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 Hardware Implementations of Spiking Neural Networks 173\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 The Need for Specialized Hardware 173\u003c\/p\u003e \u003cp\u003e5.1.1 Address-Event Representation 173\u003c\/p\u003e \u003cp\u003e5.1.2 Event-Driven Computation 174\u003c\/p\u003e \u003cp\u003e5.1.3 Inference with a Progressive Precision 175\u003c\/p\u003e \u003cp\u003e5.1.4 Hardware Considerations for Implementing the Weight-Dependent STDP Learning Rule 181\u003c\/p\u003e \u003cp\u003e5.1.4.1 Centralized Memory Architecture 182\u003c\/p\u003e \u003cp\u003e5.1.4.2 Distributed Memory Architecture 183\u003c\/p\u003e \u003cp\u003e5.2 Digital SNNs 186\u003c\/p\u003e \u003cp\u003e5.2.1 Large-Scale SNN ASICs 186\u003c\/p\u003e \u003cp\u003e5.2.1.1 SpiNNaker 186\u003c\/p\u003e \u003cp\u003e5.2.1.2 TrueNorth 187\u003c\/p\u003e \u003cp\u003e5.2.1.3 Loihi 191\u003c\/p\u003e \u003cp\u003e5.2.2 Small\/Moderate-Scale Digital SNNs 192\u003c\/p\u003e \u003cp\u003e5.2.2.1 Bottom-Up Approach 192\u003c\/p\u003e \u003cp\u003e5.2.2.2 Top-Down Approach 193\u003c\/p\u003e \u003cp\u003e5.2.3 Hardware-Friendly Reinforcement Learning in SNNs 194\u003c\/p\u003e \u003cp\u003e5.2.4 Hardware-Friendly Supervised Learning in Multilayer SNNs 199\u003c\/p\u003e \u003cp\u003e5.2.4.1 Hardware Architecture 199\u003c\/p\u003e \u003cp\u003e5.2.4.2 CMOS Implementation Results 205\u003c\/p\u003e \u003cp\u003e5.3 Analog\/Mixed-Signal SNNs 210\u003c\/p\u003e \u003cp\u003e5.3.1 Basic Building Blocks 210\u003c\/p\u003e \u003cp\u003e5.3.2 Large-Scale Analog\/Mixed-Signal CMOS SNNs 211\u003c\/p\u003e \u003cp\u003e5.3.2.1 CAVIAR 211\u003c\/p\u003e \u003cp\u003e5.3.2.2 BrainScaleS 214\u003c\/p\u003e \u003cp\u003e5.3.2.3 Neurogrid 215\u003c\/p\u003e \u003cp\u003e5.3.3 Other Analog\/Mixed-Signal CMOS SNN ASICs 216\u003c\/p\u003e \u003cp\u003e5.3.4 SNNs Based on Emerging Nanotechnologies 216\u003c\/p\u003e \u003cp\u003e5.3.4.1 Energy-Efficient Solutions 217\u003c\/p\u003e \u003cp\u003e5.3.4.2 Synaptic Plasticity 218\u003c\/p\u003e \u003cp\u003e5.3.5 Case Study: Memristor Crossbar Based Learning in SNNs 220\u003c\/p\u003e \u003cp\u003e5.3.5.1 Motivations 220\u003c\/p\u003e \u003cp\u003e5.3.5.2 Algorithm Adaptations 222\u003c\/p\u003e \u003cp\u003e5.3.5.3 Non-idealities 231\u003c\/p\u003e \u003cp\u003e5.3.5.4 Benchmarks 238\u003c\/p\u003e \u003cp\u003eReferences 238\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Conclusions 247\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Outlooks 247\u003c\/p\u003e \u003cp\u003e6.1.1 Brain-Inspired Computing 247\u003c\/p\u003e \u003cp\u003e6.1.2 Emerging Nanotechnologies 249\u003c\/p\u003e \u003cp\u003e6.1.3 Reliable Computing with Neuromorphic Systems 250\u003c\/p\u003e \u003cp\u003e6.1.4 Blending of ANNs and SNNs 251\u003c\/p\u003e \u003cp\u003e6.2 Conclusions 252\u003c\/p\u003e \u003cp\u003eReferences 253\u003c\/p\u003e \u003cp\u003e\u003cb\u003eA Appendix 257\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA.1 Hopfield Network 257\u003c\/p\u003e \u003cp\u003eA.2 Memory Self-Repair with Hopfield Network 258\u003c\/p\u003e \u003cp\u003eReferences 266\u003c\/p\u003e \u003cp\u003eIndex 269\u003c\/p\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default Title","offer_id":49407067881815,"sku":"9781119507383","price":90.86,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9781119507383.jpg?v=1730498062","url":"https:\/\/bookcurl.com\/products\/learning-in-energyefficient-neuromorphic-computing-algorithm-and-architecture-codesign-9781119507383","provider":"Book Curl","version":"1.0","type":"link"}