{"product_id":"fsmbased-digital-design-using-verilog-hdl-9780470060704","title":"FSMbased Digital Design using Verilog HDL","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eFSM based Digital Design with Verilog HDL  covers the design and use of finite state machines (FSMs) in digital systems, including stand-alone applications, as well as systems that use microprocessors, micro-controllers, memory controlled directly from the FSM, as well as other common situations found in practical digital systems.\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cb\u003eCHAPTER 1 - THE BASICS\u003c\/b\u003e  \u003cp\u003eIntroduction\u003c\/p\u003e \u003cp\u003eWhat is a Finite State Machine\u003c\/p\u003e \u003cp\u003eNumber of States\u003c\/p\u003e \u003cp\u003eNumber required for State Diagram - Frame 1.3\u003c\/p\u003e \u003cp\u003eMealy FSM\u003c\/p\u003e \u003cp\u003eMoore FSM\u003c\/p\u003e \u003cp\u003eClass C FSM\u003c\/p\u003e \u003cp\u003eIntroduction to the State Diagram – States, Transitions \u0026amp; Inputs\u003c\/p\u003e \u003cp\u003eInput Signals - Frames 1.8 to 1.9,\u003c\/p\u003e \u003cp\u003eOutput Signals - Frame 1.9\u003c\/p\u003e \u003cp\u003eInputs and Outputs of FSM\u003c\/p\u003e \u003cp\u003eInverted Inputs - Frame 1.11\u003c\/p\u003e \u003cp\u003eActive High Signals - Frames 1.11\u003c\/p\u003e \u003cp\u003eAssignment - Frame 1.11\u003c\/p\u003e \u003cp\u003eNon-Unit Distance Coding - Frame 1.11\u003c\/p\u003e \u003cp\u003eSecondary State Variables\u003c\/p\u003e \u003cp\u003eUnit Distance Coding - Frame 1.12 to Frame 1.14.\u003c\/p\u003e \u003cp\u003eActive Low Signals - Frame 1.14\u003c\/p\u003e \u003cp\u003eMealy Outputs - Frame 1.16, 1.19, 1.20, 1.21, from\u003c\/p\u003e \u003cp\u003eEffect of clock on Mealy output signals\u003c\/p\u003e \u003cp\u003eSummary - Frame 1.22\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 2 - CONTROLLING OUTSIDE WORLD DEVICES\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eIntroduction\u003c\/p\u003e \u003cp\u003eUsing Timer to Introduce Wait States - Frame 2.1 to 2.3\u003c\/p\u003e \u003cp\u003eAnalogue to Digital Converters - Frame 2.4\u003c\/p\u003e \u003cp\u003eData Acquisition System - Frame 2.4, Frame 2.9 \u0026amp; Frame 2.10 from\u003c\/p\u003e \u003cp\u003eMemory:\u003c\/p\u003e \u003cp\u003eHow to Control in FSM’s - Frame 2.5 to 2.10\u003c\/p\u003e \u003cp\u003eChip Select \u0026amp; Read and Write Sequences\u003c\/p\u003e \u003cp\u003eFrames 2.5 to 2.7 - (See also Chapter 4, Section 4.4,\u003c\/p\u003e \u003cp\u003eChapter 5, Sections 5.2, 5.3, 5.4, 5.6, 5.8.)\u003c\/p\u003e \u003cp\u003eMonitoring Inputs for Changes - Frame 2.11 to 2.14\u003c\/p\u003e \u003cp\u003eDealing with Incorrect Input States - Frame 2.14\u003c\/p\u003e \u003cp\u003eSummary\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 3 - SYNTHESISING FSMS\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eIntroduction\u003c\/p\u003e \u003cp\u003eSynthesising using T Type Flip Flops - Frame 3.1 to 3.7\u003c\/p\u003e \u003cp\u003eT Type Flip Flop\u003c\/p\u003e \u003cp\u003eT Flip Flop Example in a State Diagram\u003c\/p\u003e \u003cp\u003eDeveloping T Flip Flop Equations from the State Diagram\u003c\/p\u003e \u003cp\u003eExamples of Developing T Equations from a Number of State Diagrams\u003c\/p\u003e \u003cp\u003eSolutions to the Examples\u003c\/p\u003e \u003cp\u003eD Type Flip Flops\u003c\/p\u003e \u003cp\u003eDeveloping D Flip Flop Equations from a State Diagram\u003c\/p\u003e \u003cp\u003eRule 1: Dealing with 1 to 0 with Input Terms\u003c\/p\u003e \u003cp\u003eRule 2: Dealing with 1 to 1 Transitions\u003c\/p\u003e \u003cp\u003eRule 3: Dealing with two-way Branches\u003c\/p\u003e \u003cp\u003eUsing the Two-way Branch Rule\u003c\/p\u003e \u003cp\u003eExamples of Obtaining D Flip Flop Equations from a State Diagram\u003c\/p\u003e \u003cp\u003eState Diagram with Two-way Branch States: Obtaining D Type Equations\u003c\/p\u003e \u003cp\u003eResetting the Flip Flop\u003c\/p\u003e \u003cp\u003eExamples of Developing D Equations from a Number of State Diagrams\u003c\/p\u003e \u003cp\u003eSolutions to the Examples\u003c\/p\u003e \u003cp\u003eAsynchronous and Synchronous Resetting of Flip Flops\u003c\/p\u003e \u003cp\u003eComplete Design of Circuit for a Particular Design\u003c\/p\u003e \u003cp\u003eDealing with Multi-way Branch States using D Type Flip Flops\u003c\/p\u003e \u003cp\u003eDealing with Active Low Output Signals in an FSM\u003c\/p\u003e \u003cp\u003eDealing with Active Low Mealy Output Signals in an FSM\u003c\/p\u003e \u003cp\u003eSummary\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 4 - SYNCHRONOUS FSM DESIGNS\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Traditional FSM Design Method Verses Method used in this Book\u003c\/p\u003e \u003cp\u003e4.2 Dealing with Unused States\u003c\/p\u003e \u003cp\u003e4.3 High\/Low Alarm Indicator System\u003c\/p\u003e \u003cp\u003e4.4 Simple Waveform Generator\u003c\/p\u003e \u003cp\u003e4.5 Dice Game\u003c\/p\u003e \u003cp\u003e4.6 Binary Data Serial Transmitter\u003c\/p\u003e \u003cp\u003e4.7 Development of a Serial Asynchronous Receiver\u003c\/p\u003e \u003cp\u003e4.8 Adding Parity Detection to the Serial Receiver System\u003c\/p\u003e \u003cp\u003e4.9 Asynchronous Serial Transmitter System\u003c\/p\u003e \u003cp\u003e4.10 Clocked Watchdog Timer\u003c\/p\u003e \u003cp\u003e4.11 Summary\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 5 -ONE HOT DESIGNS\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 One Hot Technique of FSM Design\u003c\/p\u003e \u003cp\u003e5.2 Data Acquisition System (DAS)\u003c\/p\u003e \u003cp\u003e5.3 A Shared Memory System\u003c\/p\u003e \u003cp\u003e5.4 Fast Waveform Synthesiser\u003c\/p\u003e \u003cp\u003e5.5 Controlling the FSM from a Microprocessor\u003c\/p\u003e \u003cp\u003e5.6 Memory Chip Tester\u003c\/p\u003e \u003cp\u003e5.7 Comparing One Hot Solution with more Conventional Design\u003c\/p\u003e \u003cp\u003eMethod of Chapter 4\u003c\/p\u003e \u003cp\u003e5.8 Dynamic Memory Access (DMA) Controller\u003c\/p\u003e \u003cp\u003e5.9 How to Control the DMA Controller from a Microprocessor\u003c\/p\u003e \u003cp\u003e5.10 Detecting Binary Sequences using an FSM\u003c\/p\u003e \u003cp\u003e5.11 Summary\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 6 - INTRODUCTION TO VERILOG-HDL\u003c\/b\u003e\u003c\/p\u003e \u003col\u003e\n\u003cli\u003eA Brief Background to HDLs\u003c\/li\u003e\n\u003cli\u003eHardware Modelling with Verilog-HDL - the Module\u003c\/li\u003e\n\u003cli\u003eModules within Modules : Creating Hierarchy\u003c\/li\u003e\n\u003cli\u003eVerilog-HDL Simulation : A Complete Example\u003c\/li\u003e\n\u003cli\u003eReferences and Further Reading\u003c\/li\u003e\n\u003c\/ol\u003e \u003cp\u003e\u003cb\u003eCHAPTER 7 - ELEMENTS OF VERILOG-HDL\u003c\/b\u003e\u003c\/p\u003e \u003col\u003e\n\u003cli\u003eBuilt-in Primitives and Types\u003cbr\u003e 7.1.1 Verilog Types\u003cbr\u003e 7.1.2 Verilog Logic and Numeric Values\u003cbr\u003e 7.1.3 Specifying Values\u003cbr\u003e 7.1.4 Verilog-HDL Primitive Gates\u003c\/li\u003e\n\u003cli\u003eOperators and Expressions\u003c\/li\u003e\n\u003cli\u003eExample Illustrating the use of Verilog-HDL Operators -\u003cbr\u003e Hamming Code Encoder\u003c\/li\u003e\n\u003cli\u003eReferences and Further Reading\u003c\/li\u003e\n\u003c\/ol\u003e \u003cp\u003e\u003cb\u003eCHAPTER 8 - DESCRIBING COMBINATIONAL AND SEQUENTIAL LOGIC USING VERILOG=HDL\u003c\/b\u003e\u003c\/p\u003e \u003col\u003e\n\u003cli\u003eThe Data Flow Style of Description - Review of the\u003cbr\u003e Continuous Assignment\u003c\/li\u003e\n\u003cli\u003eThe Behavioural Style of Description - The Sequential Block\u003c\/li\u003e\n\u003cli\u003eAssignments within Sequential Blocks : Blocking and\u003cbr\u003e Non-Blocking\u003c\/li\u003e\n\u003cli\u003eDescribing Combinational Logic using a Sequential Block\u003c\/li\u003e\n\u003cli\u003eDescribing Sequential Logic using a Sequential Block\u003c\/li\u003e\n\u003cli\u003eDescribing Memories\u003c\/li\u003e\n\u003cli\u003eDescribing Finite State Machines:\u003cbr\u003e Example 1 Chess Clock Controller FSM\u003cbr\u003e Example 2 Combinational Lock FSM with Automatic\u003cbr\u003e Lock Feature\u003c\/li\u003e\n\u003cli\u003eReferences and Further Reading\u003c\/li\u003e\n\u003c\/ol\u003e \u003cp\u003e\u003cb\u003eCHAPTER 9 - ASYNCHRONOUS FSM DESIGN\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Introduction\u003c\/p\u003e \u003cp\u003e9.2 Development of Event Driven Logic\u003c\/p\u003e \u003cp\u003e9.3 Using the Sequential Equations to Synthesise an Event FSM\u003c\/p\u003e \u003cp\u003e9.3.1 Short Cut Rule\u003c\/p\u003e \u003cp\u003e9.4 Implementing the Design using Sum of Product as PLD\u003c\/p\u003e \u003cp\u003e9.5 Development of an Event Version of the Single Pulse Generator\u003c\/p\u003e \u003cp\u003ewith Memory FSM\u003c\/p\u003e \u003cp\u003e9.6 Another event FSM design through to simulation\u003c\/p\u003e \u003cp\u003e9.7 The Hover Mower FSM\u003c\/p\u003e \u003cp\u003e9.8 An Example with a Transition Without any Input\u003c\/p\u003e \u003cp\u003e9.9 Unusual Example responding to a Microprocessor\u003c\/p\u003e \u003cp\u003eAddress Location\u003c\/p\u003e \u003cp\u003e9.10 Example that uses a Mealy Output\u003c\/p\u003e \u003cp\u003e9.11 Example using a Relay Circuit\u003c\/p\u003e \u003cp\u003e9.12 Race Conditions in Event FSMs\u003c\/p\u003e \u003cp\u003e9.13 Wait State Generator for a Microprocessor System\u003c\/p\u003e \u003cp\u003e9.14 Development of an Asynchronous FSM to Control a Clothes\u003c\/p\u003e \u003cp\u003eSpin System\u003c\/p\u003e \u003cp\u003e9.15 Summary\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 10 - PETRI-NETS\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Introduction to Simple Petri-Nets\u003c\/p\u003e \u003cp\u003e10.2 Sequential Petri-Net Example, the Pump Spin Motor Problem\u003c\/p\u003e \u003cp\u003e10.3 Parallel Petri-Nets\u003c\/p\u003e \u003cp\u003e10.4 Synchronising Flow in a Parallel Petri-Net\u003c\/p\u003e \u003cp\u003e10.5 Using Enabling\/Disabling Arcs to Synchronise Flow between\u003c\/p\u003e \u003cp\u003eTwo Petri-Nets\u003c\/p\u003e \u003cp\u003e10.6 Example - Control of Shared Resource\u003c\/p\u003e \u003cp\u003e10.7 A Serial Receiver of Binary Data using a Petri-Net Controller\u003c\/p\u003e \u003cp\u003e10.8 Summary\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAPPENDIX INDEX\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAPPENDIX A1 - LOGIC GATES AND BOOLEAN ALGEBRA IN THE BOOK\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eIntroduction\u003c\/p\u003e \u003cp\u003eA1.1 Basic Gate Symbols used in the Book\u003c\/p\u003e \u003cp\u003eA1.2 Exclusive OR and Exclusive NOR Symbols\u003c\/p\u003e \u003cp\u003eA1.3 Laws of Boolean Algebra:\u003c\/p\u003e \u003cp\u003eA1.3.1 Basic OR Rules\u003c\/p\u003e \u003cp\u003eA1.3.2 Basic AND Rules\u003c\/p\u003e \u003cp\u003eA1.3.3 Associative Laws and Commutative Laws\u003c\/p\u003e \u003cp\u003eA1.3.4 Distributive Laws\u003c\/p\u003e \u003cp\u003eA1.3.5 Auxiliary Law - For Static 1 Hazard Removal\u003c\/p\u003e \u003cp\u003eA1.3.5.1 Proof of the Auxiliary Law\u003c\/p\u003e \u003cp\u003eA1.3.6 The Consensus Theorem\u003c\/p\u003e \u003cp\u003eA1.3.7 Effect of Signal Delay on Logic Gates\u003c\/p\u003e \u003cp\u003eA1.3.8 De-Morgans Theorem\u003c\/p\u003e \u003cp\u003eA1.4 Examples of Applying the Laws of Boolean Algebra\u003c\/p\u003e \u003cp\u003eA1.4.1 Converting AND-OR to NAND\u003c\/p\u003e \u003cp\u003eA1.4.2 Converting AND-OR to NOR\u003c\/p\u003e \u003cp\u003eA1.4.3 Logical Adjacency Rule\u003c\/p\u003e \u003cp\u003eA1.5 Summary\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAPPENDIX A2 - COUNTING \u0026amp; SHIFTING CIRCUIT TECHNIQUES\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eIntroduction\u003c\/p\u003e \u003cp\u003eA2.1 Basic Up Down Synchronous Binary Counter Development\u003c\/p\u003e \u003cp\u003eA2.2 Example of a Four Bit Synchronous up Counter using T Flip Flops\u003c\/p\u003e \u003cp\u003eA2.3 Parallel Loading Counters\u003c\/p\u003e \u003cp\u003eA2.4 Using D Flip Flops to Build Parallel Loading Counters\u003c\/p\u003e \u003cp\u003eA2.5 Simple Binary Up Counter\u003c\/p\u003e \u003cp\u003eA2.6 Clock Circuit to Drive the Counter (and FSMs)\u003c\/p\u003e \u003cp\u003eA2.7 Counter Design using Don’t Cares\u003c\/p\u003e \u003cp\u003eA2.8 Shift Registers\u003c\/p\u003e \u003cp\u003eA2.9 Asynchronous Receiver Details for Section 4.7 Chapter 4\u003c\/p\u003e \u003cp\u003eA2.9.1 Eleven Bit Shift Register for the Asynchronous\u003c\/p\u003e \u003cp\u003eReceiver Module\u003c\/p\u003e \u003cp\u003eA2.9.2 Divide by Eleven Counter\u003c\/p\u003e \u003cp\u003eA2.9.3 Complete Simulation of the Asynchronous\u003c\/p\u003e \u003cp\u003eReceiver System\u003c\/p\u003e \u003cp\u003eA2.10 Summary\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAPPENDIX A3 - TUTORIAL ON THE USE OF VERILOG HDL\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eTO SIMULATE AN FSM DESIGN\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA3.1 Introduction\u003c\/p\u003e \u003cp\u003eA3.2 Single Pulse with Memory Synchronous FSM Design\u003c\/p\u003e \u003cp\u003eA3.2.1 Specification\u003c\/p\u003e \u003cp\u003eA3.2.2 Block Diagram\u003c\/p\u003e \u003cp\u003eA3.2.3 State Diagram\u003c\/p\u003e \u003cp\u003eA3.2.4 Equations from the State Diagram\u003c\/p\u003e \u003cp\u003eA3.2.5 Translation into a Verilog Description\u003c\/p\u003e \u003cp\u003eA3.3 Test Bench Module and its Purpose\u003c\/p\u003e \u003cp\u003eA3.4 Using the Verilogger Simulator\u003c\/p\u003e \u003cp\u003eA3.4.1 Output from the Simulator\u003c\/p\u003e \u003cp\u003eA3.5 Summary\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAPPENDIX A4 - IMPLEMENTING STATE MACHINES USING VERILOG BEHAVIOURAL MODE\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA4.1 Introduction\u003c\/p\u003e \u003cp\u003eA4.2 Example 1- The Single Pulse with Memory FSM Revisited\u003c\/p\u003e \u003cp\u003eA4.3 The Memory Tester in Chapter 5, Section 5.6 Revisited\u003c\/p\u003e \u003cp\u003eA4.4 Summary\u003c\/p\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default Title","offer_id":49402276872535,"sku":"9780470060704","price":108.86,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9780470060704.jpg?v=1730479921","url":"https:\/\/bookcurl.com\/products\/fsmbased-digital-design-using-verilog-hdl-9780470060704","provider":"Book Curl","version":"1.0","type":"link"}