{"product_id":"fpga-prototyping-by-vhdl-examples-9780470185315","title":"FPGA Prototyping by VHDL Examples","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eAn introductory text, this book introduces the HDL (hardware description languages) and FPGA development process to designers through a series of hands-on experiments. The main focus of the book is on the effective derivation of hardware.\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTrade Review\u003c\/b\u003e\u003cbr\u003e\"The book is well organized and contains many useful synthesizable VHDL examples. Moreover, design concepts are clearly explained … This book is indeed an excellent text for people who wish to learn PFGA and VHDL from practical examples and exercises.\" (\u003ci\u003eComputing Reviews\u003c\/i\u003e, February 18, 2009)  \u003cp\u003e\"Brimming with code examples, flowcharts and other illustrations, the book serves as a good starting point for a development project.  It's recommended to anyone looking to get started with FPGA prototyping using VHDL.\" (\u003ci\u003eElectronic Design\u003c\/i\u003e, February 4, 2008)\u003c\/p\u003e \u003cp\u003e\"It's recommended to anyone looking to get started with FGPA prototyping using VHDL.\" (\u003ci\u003eElectronic Design Online\u003c\/i\u003e, February 4, 2008)\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003ePreface.  \u003cp\u003eAcknowledgments.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART I: BASIC DIGITAL CIRCUITS.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1. Gate-level combinational circuit.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Introduction.\u003c\/p\u003e \u003cp\u003e1.2 General description.\u003c\/p\u003e \u003cp\u003e1.2.1 Basic lexical rules.\u003c\/p\u003e \u003cp\u003e1.2.2 Library and package.\u003c\/p\u003e \u003cp\u003e1.2.3 Entity declaration.\u003c\/p\u003e \u003cp\u003e1.2.4 Data type and operators.\u003c\/p\u003e \u003cp\u003e1.2.5 Architecture body.\u003c\/p\u003e \u003cp\u003e1.2.6 Code of a 2-bit comparator.\u003c\/p\u003e \u003cp\u003e1.3 Structural description.\u003c\/p\u003e \u003cp\u003e1.4 Testbench.\u003c\/p\u003e \u003cp\u003e1.5 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e1.6 Suggested experiments.\u003c\/p\u003e \u003cp\u003e1.6.1 Code for gate-level greater-than circuit.\u003c\/p\u003e \u003cp\u003e1.6.2 Code for gate-level binary decoder.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2. Overview of FPGA and EDA software.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Introduction.\u003c\/p\u003e \u003cp\u003e2.2 FPGA.\u003c\/p\u003e \u003cp\u003e2.2.1 Overview of general FPGA device.\u003c\/p\u003e \u003cp\u003e2.2.2 Overview of Xilinx Spartan-3 device.\u003c\/p\u003e \u003cp\u003e2.3 Overview of Digilent S3 board.\u003c\/p\u003e \u003cp\u003e2.4 Design flow.\u003c\/p\u003e \u003cp\u003e2.5 Overview of Xilinx ISE project navigator.\u003c\/p\u003e \u003cp\u003e2.6 Short tutorial of ISE project navigator.\u003c\/p\u003e \u003cp\u003e2.6.1 Create the design project and HDL codes.\u003c\/p\u003e \u003cp\u003e2.6.2 Create a testbench and perform RTL simulation.\u003c\/p\u003e \u003cp\u003e2.6.3 Add a constraint file and synthesize and implement the code.\u003c\/p\u003e \u003cp\u003e2.6.4 Generate and download the configuration file to FPGA devices.\u003c\/p\u003e \u003cp\u003e2.7 Short tutorial of ModelSim HDL simulator.\u003c\/p\u003e \u003cp\u003e2.8 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e2.9 Suggested experiments.\u003c\/p\u003e \u003cp\u003e2.9.1 Gate-level greater-than circuit.\u003c\/p\u003e \u003cp\u003e2.9.2 Gate-level binary decoder.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3. RT-level combinational circuit.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Introduction.\u003c\/p\u003e \u003cp\u003e3.2 RT-level components.\u003c\/p\u003e \u003cp\u003e3.2.1 Relational operators.\u003c\/p\u003e \u003cp\u003e3.2.2 Arithmetic operators.\u003c\/p\u003e \u003cp\u003e3.2.3 Other synthesis related VHDL constructs.\u003c\/p\u003e \u003cp\u003e3.2.4 Summary.\u003c\/p\u003e \u003cp\u003e3.3 Routing circuit with concurrent assignment statements.\u003c\/p\u003e \u003cp\u003e3.3.1 Conditional signal assignment statement.\u003c\/p\u003e \u003cp\u003e3.3.2 Selected signal assignment statement.\u003c\/p\u003e \u003cp\u003e3.4 Modeling with process.\u003c\/p\u003e \u003cp\u003e3.4.1 Process.\u003c\/p\u003e \u003cp\u003e3.4.2 Sequential signal assignment statement.\u003c\/p\u003e \u003cp\u003e3.5 Routing circuit with if and case statements.\u003c\/p\u003e \u003cp\u003e3.5.1 If statement.\u003c\/p\u003e \u003cp\u003e3.5.2 Case statement.\u003c\/p\u003e \u003cp\u003e3.5.3 Comparison to concurrent statements.\u003c\/p\u003e \u003cp\u003e3.5.4 Unintended memory.\u003c\/p\u003e \u003cp\u003e3.6 Constant and generic.\u003c\/p\u003e \u003cp\u003e3.6.1 Constant.\u003c\/p\u003e \u003cp\u003e3.6.2 Generic.\u003c\/p\u003e \u003cp\u003e3.7 Design examples.\u003c\/p\u003e \u003cp\u003e3.7.1 Hexadecimal digit to seven-segment LED decoder.\u003c\/p\u003e \u003cp\u003e3.7.2 Sign-magnitude adder.\u003c\/p\u003e \u003cp\u003e3.7.3 Barrel shifter.\u003c\/p\u003e \u003cp\u003e3.7.4 A simplified floating-point adder.\u003c\/p\u003e \u003cp\u003e3.8 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e3.9 Suggested experiments.\u003c\/p\u003e \u003cp\u003e3.9.1 Multi-function barrel shifter.\u003c\/p\u003e \u003cp\u003e3.9.2 Dual priority encoder.\u003c\/p\u003e \u003cp\u003e3.9.3 BCD incrementor.\u003c\/p\u003e \u003cp\u003e3.9.4 Floating-point greater-than circuit.\u003c\/p\u003e \u003cp\u003e3.9.5 Floating-point and signed integer conversion circuit.\u003c\/p\u003e \u003cp\u003e3.9.6 Enhanced floating-point adder.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4. Regular Sequential Circuit.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Overview.\u003c\/p\u003e \u003cp\u003e4.1.1 D FF and register.\u003c\/p\u003e \u003cp\u003e4.1.2 Synchronous system.\u003c\/p\u003e \u003cp\u003e4.1.3 Code development.\u003c\/p\u003e \u003cp\u003e4.2 HDL code of FF and register.\u003c\/p\u003e \u003cp\u003e4.2.1 D FF.\u003c\/p\u003e \u003cp\u003e4.2.2 Register.\u003c\/p\u003e \u003cp\u003e4.2.3 Register File.\u003c\/p\u003e \u003cp\u003e4.2.4 Storage components in Spartan-3 deviceXilinx specific.\u003c\/p\u003e \u003cp\u003e4.3 Simple design examples.\u003c\/p\u003e \u003cp\u003e4.3.1 Shift register.\u003c\/p\u003e \u003cp\u003e4.3.2 Binary counter and variant.\u003c\/p\u003e \u003cp\u003e4.4 Testbench for sequential circuits.\u003c\/p\u003e \u003cp\u003e4.5 Case study.\u003c\/p\u003e \u003cp\u003e4.5.1 LED time multiplexing circuit.\u003c\/p\u003e \u003cp\u003e4.5.2 Stopwatch.\u003c\/p\u003e \u003cp\u003e4.5.3 FIFO buffer.\u003c\/p\u003e \u003cp\u003e4.6 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e4.7 Suggested experiments.\u003c\/p\u003e \u003cp\u003e4.7.1 Programmable square wave generator.\u003c\/p\u003e \u003cp\u003e4.7.2 PWM and LED dimmer.\u003c\/p\u003e \u003cp\u003e4.7.3 Rotating square circuit.\u003c\/p\u003e \u003cp\u003e4.7.4 Heartbeat circuit.\u003c\/p\u003e \u003cp\u003e4.7.5 Rotating LED banner circuit.\u003c\/p\u003e \u003cp\u003e4.7.6 Enhanced stopwatch.\u003c\/p\u003e \u003cp\u003e4.7.7 Stack.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5. FSM.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Overview.\u003c\/p\u003e \u003cp\u003e5.1.1 Mealy and Moore outputs.\u003c\/p\u003e \u003cp\u003e5.1.2 FSM representation.\u003c\/p\u003e \u003cp\u003e5.2 FSM code development.\u003c\/p\u003e \u003cp\u003e5.3 Design examples.\u003c\/p\u003e \u003cp\u003e5.3.1 Rising edge detector.\u003c\/p\u003e \u003cp\u003e5.3.2 Debouncing circuit.\u003c\/p\u003e \u003cp\u003e5.3.3 Testing circuit.\u003c\/p\u003e \u003cp\u003e5.4 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e5.5 Suggested experiments.\u003c\/p\u003e \u003cp\u003e5.5.1 Dual-edge detector.\u003c\/p\u003e \u003cp\u003e5.5.2 Alternative debouncing circuit.\u003c\/p\u003e \u003cp\u003e5.5.3 Parking lot occupancy counter.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6. FSMD.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Overview.\u003c\/p\u003e \u003cp\u003e6.1.1 Single RT operation.\u003c\/p\u003e \u003cp\u003e6.1.2 ASMD chart.\u003c\/p\u003e \u003cp\u003e6.1.3 Decision box with register.\u003c\/p\u003e \u003cp\u003e6.2 Code development of FSMD.\u003c\/p\u003e \u003cp\u003e6.2.1 Debouncing circuit based on RT methodology.\u003c\/p\u003e \u003cp\u003e6.2.2 Code with explicit data path components.\u003c\/p\u003e \u003cp\u003e6.2.3 Code with implicit data path components.\u003c\/p\u003e \u003cp\u003e6.2.4 Comparison.\u003c\/p\u003e \u003cp\u003e6.2.5 Testing circuit.\u003c\/p\u003e \u003cp\u003e6.3 Design examples.\u003c\/p\u003e \u003cp\u003e6.3.1 Fibonacci number circuit.\u003c\/p\u003e \u003cp\u003e6.3.2 Division circuit.\u003c\/p\u003e \u003cp\u003e6.3.3 Binary-to-BCD conversion circuit.\u003c\/p\u003e \u003cp\u003e6.3.4 Period counter.\u003c\/p\u003e \u003cp\u003e6.3.5 Accurate low-frequency counter.\u003c\/p\u003e \u003cp\u003e6.4 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e6.5 Suggested experiments.\u003c\/p\u003e \u003cp\u003e6.5.1 Alternative debouncing circuit.\u003c\/p\u003e \u003cp\u003e6.5.2 BCD-to-binary conversion circuit.\u003c\/p\u003e \u003cp\u003e6.5.3 Fibonacci circuit with BCD I\/O: design approach 1.\u003c\/p\u003e \u003cp\u003e6.5.4 Fibonacci circuit with BCD I\/O: design approach 2.\u003c\/p\u003e \u003cp\u003e6.5.5 Auto-scaled low-frequency counter.\u003c\/p\u003e \u003cp\u003e6.5.6 Reaction timer.\u003c\/p\u003e \u003cp\u003e6.5.7 Babbage difference engine emulation circuit.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART II: I\/O MODULES.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7. UART.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Overview.\u003c\/p\u003e \u003cp\u003e7.2 UART receiving subsystem.\u003c\/p\u003e \u003cp\u003e7.2.1 Oversampling procedure.\u003c\/p\u003e \u003cp\u003e7.2.2 Baud rate generator.\u003c\/p\u003e \u003cp\u003e7.2.3 UART receiver.\u003c\/p\u003e \u003cp\u003e7.2.4 Interface circuit.\u003c\/p\u003e \u003cp\u003e7.3 UART transmitting subsystem.\u003c\/p\u003e \u003cp\u003e7.4 Overall UART system.\u003c\/p\u003e \u003cp\u003e7.4.1 Complete UART core.\u003c\/p\u003e \u003cp\u003e7.4.2 UART verification configuration.\u003c\/p\u003e \u003cp\u003e7.5 Customizing the UART.\u003c\/p\u003e \u003cp\u003e7.6 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e7.7 Suggested experiments.\u003c\/p\u003e \u003cp\u003e7.7.1 Full-featured UART.\u003c\/p\u003e \u003cp\u003e7.7.2 A UART with an automatic baud rate detection circuit.\u003c\/p\u003e \u003cp\u003e7.7.3 A UART with an automatic baud rate and parity detection circuit.\u003c\/p\u003e \u003cp\u003e7.7.4 UART controlled stopwatch.\u003c\/p\u003e \u003cp\u003e7.7.5 UART controlled rotating LED banner.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8. PS2 Keyboard.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Overview.\u003c\/p\u003e \u003cp\u003e8.2 PS2 receiving subsystem.\u003c\/p\u003e \u003cp\u003e8.2.1 Physical interface of PS2 port.\u003c\/p\u003e \u003cp\u003e8.2.2 Device-to-host communication protocol.\u003c\/p\u003e \u003cp\u003e8.2.3 Design and code.\u003c\/p\u003e \u003cp\u003e8.3 PS2 keyboard scan code.\u003c\/p\u003e \u003cp\u003e8.3.1 Overview of scan code.\u003c\/p\u003e \u003cp\u003e8.3.2 Scan code monitor circuit.\u003c\/p\u003e \u003cp\u003e8.4 PS2 keyboard interface circuit.\u003c\/p\u003e \u003cp\u003e8.4.1 Basic design and HDL code.\u003c\/p\u003e \u003cp\u003e8.4.2 Verification circuit.\u003c\/p\u003e \u003cp\u003e8.5 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e8.6 Suggested experiments.\u003c\/p\u003e \u003cp\u003e8.6.1 Alternative keyboard interface I.\u003c\/p\u003e \u003cp\u003e8.6.2 Alternative keyboard interface II.\u003c\/p\u003e \u003cp\u003e8.6.3 PS2 receiving subsystem with watchdog timer.\u003c\/p\u003e \u003cp\u003e8.6.4 Keyboard controlled stopwatch.\u003c\/p\u003e \u003cp\u003e8.6.5 Keyboard controlled rotating LED banner.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9. PS2 Mouse.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Overview.\u003c\/p\u003e \u003cp\u003e9.2 PS2 mouse protocol.\u003c\/p\u003e \u003cp\u003e9.2.1 Basic operation.\u003c\/p\u003e \u003cp\u003e9.2.2 Basic initialization procedure.\u003c\/p\u003e \u003cp\u003e9.3 PS2 transmitting subsystem.\u003c\/p\u003e \u003cp\u003e9.3.1 Host-to-PS2-device communication protocol.\u003c\/p\u003e \u003cp\u003e9.3.2 Design and code.\u003c\/p\u003e \u003cp\u003e9.4 Bidirectional PS2 interface.\u003c\/p\u003e \u003cp\u003e9.4.1 Basic design and code.\u003c\/p\u003e \u003cp\u003e9.4.2 Verification circuit.\u003c\/p\u003e \u003cp\u003e9.5 PS2 mouse interface.\u003c\/p\u003e \u003cp\u003e9.5.1 Basic design.\u003c\/p\u003e \u003cp\u003e9.5.2 Testing circuit.\u003c\/p\u003e \u003cp\u003e9.6 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e9.7 Suggested experiments.\u003c\/p\u003e \u003cp\u003e9.7.1 Keyboard control circuit.\u003c\/p\u003e \u003cp\u003e9.7.2 Enhanced mouse interface.\u003c\/p\u003e \u003cp\u003e9.7.3 Mouse controlled seven-segment LED display.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10. External SRAM.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Introduction.\u003c\/p\u003e \u003cp\u003e10.2 Specification of the IS61LV25616AL SRAM.\u003c\/p\u003e \u003cp\u003e10.2.1 Block diagram and I\/O signals.\u003c\/p\u003e \u003cp\u003e10.2.2 Timing parameters.\u003c\/p\u003e \u003cp\u003e10.3 Basic memory controller.\u003c\/p\u003e \u003cp\u003e10.3.1 Block diagram.\u003c\/p\u003e \u003cp\u003e10.3.2 Timing requirement.\u003c\/p\u003e \u003cp\u003e10.3.3 Register file versus SRAM.\u003c\/p\u003e \u003cp\u003e10.4 A safe design.\u003c\/p\u003e \u003cp\u003e10.4.1 ASMD chart.\u003c\/p\u003e \u003cp\u003e10.4.2 Timing analysis.\u003c\/p\u003e \u003cp\u003e10.4.3 HDL implementation.\u003c\/p\u003e \u003cp\u003e10.4.4 Basic testing circuit.\u003c\/p\u003e \u003cp\u003e10.4.5 Comprehensive SRAM testing circuit.\u003c\/p\u003e \u003cp\u003e10.5 More aggressive design.\u003c\/p\u003e \u003cp\u003e10.5.1 Timing issues.\u003c\/p\u003e \u003cp\u003e10.5.2 Alternative design I.\u003c\/p\u003e \u003cp\u003e10.5.3 Alternative design II.\u003c\/p\u003e \u003cp\u003e10.5.4 Alternative design III.\u003c\/p\u003e \u003cp\u003e10.5.5 Advanced FPGA featuresXilinx specific.\u003c\/p\u003e \u003cp\u003e10.6 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e10.7 Suggested experiments.\u003c\/p\u003e \u003cp\u003e10.7.1 Memory with 512K-by-16 configuration.\u003c\/p\u003e \u003cp\u003e10.7.2 Memory with 1M-by-8 configuration.\u003c\/p\u003e \u003cp\u003e10.7.3 Memory with 8M-by-1 configuration.\u003c\/p\u003e \u003cp\u003e10.7.4 Expanded memory testing circuit.\u003c\/p\u003e \u003cp\u003e10.7.5 Memory controller and testing circuit for alternative design I.\u003c\/p\u003e \u003cp\u003e10.7.6 Memory controller and testing circuit for alternative design II.\u003c\/p\u003e \u003cp\u003e10.7.7 Memory controller and testing circuit for alternative design III.\u003c\/p\u003e \u003cp\u003e10.7.8 Memory controller with DCM.\u003c\/p\u003e \u003cp\u003e10.7.9 High-performance memory controller.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11. Xilinx Spartan-3 Specific Memory.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Introduction.\u003c\/p\u003e \u003cp\u003e11.2 Embedded memory of Spartan-3 device.\u003c\/p\u003e \u003cp\u003e11.2.1 Overview.\u003c\/p\u003e \u003cp\u003e11.2.2 Comparison.\u003c\/p\u003e \u003cp\u003e11.3 Method to incorporate memory modules.\u003c\/p\u003e \u003cp\u003e11.3.1 Memory module via HDL component instantiation.\u003c\/p\u003e \u003cp\u003e11.3.2 Memory module via Core Generator.\u003c\/p\u003e \u003cp\u003e11.3.3 Memory module via HDL inference.\u003c\/p\u003e \u003cp\u003e11.4 HDL templates for memory inference.\u003c\/p\u003e \u003cp\u003e11.4.1 Single-port RAM.\u003c\/p\u003e \u003cp\u003e11.4.2 Dual-port RAM.\u003c\/p\u003e \u003cp\u003e11.4.3 ROM.\u003c\/p\u003e \u003cp\u003e11.5 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e11.6 Suggested experiments.\u003c\/p\u003e \u003cp\u003e11.6.1 Block RAM based FIFO.\u003c\/p\u003e \u003cp\u003e11.6.2 Block RAM based stack.\u003c\/p\u003e \u003cp\u003e11.6.3 ROM based sign-magnitude adder.\u003c\/p\u003e \u003cp\u003e11.6.4 ROM based sin(x) function.\u003c\/p\u003e \u003cp\u003e11.6.5 ROM based sin(x) and cos(x) functions.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12. VGA controller I: graphic.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e12.1 Introduction.\u003c\/p\u003e \u003cp\u003e12.1.1 Basic operation of a CRT.\u003c\/p\u003e \u003cp\u003e12.1.2 VGA port of S3 board.\u003c\/p\u003e \u003cp\u003e12.1.3 Video controller.\u003c\/p\u003e \u003cp\u003e12.2 VGA synchronization.\u003c\/p\u003e \u003cp\u003e12.2.1 Horizontal synchronization.\u003c\/p\u003e \u003cp\u003e12.2.2 Vertical synchronization.\u003c\/p\u003e \u003cp\u003e12.2.3 Timing calculation of VGA synchronization signals.\u003c\/p\u003e \u003cp\u003e12.2.4 HDL implementation.\u003c\/p\u003e \u003cp\u003e12.2.5 Testing circuit.\u003c\/p\u003e \u003cp\u003e12.3 Overview of pixel generation circuit.\u003c\/p\u003e \u003cp\u003e12.4 Graphic generation with object-mapped scheme.\u003c\/p\u003e \u003cp\u003e12.4.1 Rectangular objects.\u003c\/p\u003e \u003cp\u003e12.4.2 Non-rectangular object.\u003c\/p\u003e \u003cp\u003e12.4.3 Animated object.\u003c\/p\u003e \u003cp\u003e12.5 Graphic generation with bit-mapped scheme.\u003c\/p\u003e \u003cp\u003e12.5.1 Dual-port RAM implementation.\u003c\/p\u003e \u003cp\u003e12.5.2 Single-port RAM implementation.\u003c\/p\u003e \u003cp\u003e12.6 Suggest experiments.\u003c\/p\u003e \u003cp\u003e12.6.1 VGA test pattern generator.\u003c\/p\u003e \u003cp\u003e12.6.2 SVGA mode synchronization circuit.\u003c\/p\u003e \u003cp\u003e12.6.3 Visible screen adjustment circuit.\u003c\/p\u003e \u003cp\u003e12.6.4 Ball-in-a-box circuit.\u003c\/p\u003e \u003cp\u003e12.6.5 Two-balls-in-a-box circuit.\u003c\/p\u003e \u003cp\u003e12.6.6 Two-player pong game.\u003c\/p\u003e \u003cp\u003e12.6.7 Breakout game.\u003c\/p\u003e \u003cp\u003e12.6.8 Full-screen dot trace.\u003c\/p\u003e \u003cp\u003e12.6.9 Mouse pointer circuit.\u003c\/p\u003e \u003cp\u003e12.6.10 Small-screen mouse scribble circuit.\u003c\/p\u003e \u003cp\u003e12.6.11 Full-screen mouse scribble circuit.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e13. VGA controller II: text.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e13.1 Introduction.\u003c\/p\u003e \u003cp\u003e13.2 Text generation.\u003c\/p\u003e \u003cp\u003e13.2.1 Character as tile.\u003c\/p\u003e \u003cp\u003e13.2.2 Font ROM.\u003c\/p\u003e \u003cp\u003e13.2.3 Basic text generation circuit.\u003c\/p\u003e \u003cp\u003e13.2.4 Font display circuit.\u003c\/p\u003e \u003cp\u003e13.2.5 Font scaling.\u003c\/p\u003e \u003cp\u003e13.3 Full-screen text display.\u003c\/p\u003e \u003cp\u003e13.4 The complete pong game.\u003c\/p\u003e \u003cp\u003e13.4.1 Text subsystem.\u003c\/p\u003e \u003cp\u003e13.4.2 Modified graphic subsystem.\u003c\/p\u003e \u003cp\u003e13.4.3 Auxiliary counters.\u003c\/p\u003e \u003cp\u003e13.4.4 Top-level system.\u003c\/p\u003e \u003cp\u003e13.5 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e13.6 Suggested experiments.\u003c\/p\u003e \u003cp\u003e13.6.1 Rotating banner.\u003c\/p\u003e \u003cp\u003e13.6.2 Underline for cursor.\u003c\/p\u003e \u003cp\u003e13.6.3 Dual-mode text display.\u003c\/p\u003e \u003cp\u003e13.6.4 Keyboard text entry.\u003c\/p\u003e \u003cp\u003e13.6.5 UART terminal.\u003c\/p\u003e \u003cp\u003e13.6.6 Square wave display.\u003c\/p\u003e \u003cp\u003e13.6.7 Simple four-trace logic analyzer.\u003c\/p\u003e \u003cp\u003e13.6.8 Complete two-player pong game.\u003c\/p\u003e \u003cp\u003e13.6.9 Complete breakout game.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART III: PICOBLAZE MICROCONTROLLERXILINX SPECIFIC.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e14. PicoBlaze Overview.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e14.1 Introduction.\u003c\/p\u003e \u003cp\u003e14.2 Customized hardware and customized software.\u003c\/p\u003e \u003cp\u003e14.2.1 From special-purpose FSMD to general-purpose microcontroller.\u003c\/p\u003e \u003cp\u003e14.2.2 Application of microcontroller.\u003c\/p\u003e \u003cp\u003e14.3 Overview of PicoBlaze.\u003c\/p\u003e \u003cp\u003e14.3.1 Basic organization.\u003c\/p\u003e \u003cp\u003e14.3.2 Top-level HDL modules.\u003c\/p\u003e \u003cp\u003e14.4 Development flow.\u003c\/p\u003e \u003cp\u003e14.5 Instruction set.\u003c\/p\u003e \u003cp\u003e14.5.1 Programming model.\u003c\/p\u003e \u003cp\u003e14.5.2 Instruction format.\u003c\/p\u003e \u003cp\u003e14.5.3 Logical instructions.\u003c\/p\u003e \u003cp\u003e14.5.4 Arithmetic instructions.\u003c\/p\u003e \u003cp\u003e14.5.5 Compare and test instructions.\u003c\/p\u003e \u003cp\u003e14.5.6 Shift and rotate instructions.\u003c\/p\u003e \u003cp\u003e14.5.7 Data movement instructions.\u003c\/p\u003e \u003cp\u003e14.5.8 Program flow control instructions.\u003c\/p\u003e \u003cp\u003e14.5.9 Interrupt related instructions.\u003c\/p\u003e \u003cp\u003e14.6 Assembler directives.\u003c\/p\u003e \u003cp\u003e14.6.1 The KCPSM3 directives.\u003c\/p\u003e \u003cp\u003e14.6.2 The PBlazeIDE directives.\u003c\/p\u003e \u003cp\u003e14.7 Bibliographic notes 343.\u003c\/p\u003e \u003cp\u003e14.8 Suggested experiments 343.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e15. PicoBlaze Assembly Code Development.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e15.1 Introduction.\u003c\/p\u003e \u003cp\u003e15.2 Useful code segments.\u003c\/p\u003e \u003cp\u003e15.2.1 KCPSM3 conventions.\u003c\/p\u003e \u003cp\u003e15.2.2 Bit manipulation.\u003c\/p\u003e \u003cp\u003e15.2.3 Multiple-byte manipulation.\u003c\/p\u003e \u003cp\u003e15.2.4 Control structure.\u003c\/p\u003e \u003cp\u003e15.3 Subroutine development.\u003c\/p\u003e \u003cp\u003e15.4 Program development.\u003c\/p\u003e \u003cp\u003e15.4.1 Demonstration example.\u003c\/p\u003e \u003cp\u003e15.4.2 Program documentation.\u003c\/p\u003e \u003cp\u003e15.5 Processing of assembly code.\u003c\/p\u003e \u003cp\u003e15.5.1 Compiling with KCSPM3.\u003c\/p\u003e \u003cp\u003e15.5.2 Simulation by PBlazeIDE.\u003c\/p\u003e \u003cp\u003e15.5.3 Reload code via JTAG port.\u003c\/p\u003e \u003cp\u003e15.5.4 Compiling by PBlazeIDE.\u003c\/p\u003e \u003cp\u003e15.6 Syntheses with PicoBlaze.\u003c\/p\u003e \u003cp\u003e15.7 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e15.8 Suggested experiments.\u003c\/p\u003e \u003cp\u003e15.8.1 Signed multiplication.\u003c\/p\u003e \u003cp\u003e15.8.2 Multi-bytes multiplication.\u003c\/p\u003e \u003cp\u003e15.8.3 Barrel shift function.\u003c\/p\u003e \u003cp\u003e15.8.4 Reverse function.\u003c\/p\u003e \u003cp\u003e15.8.5 Binary-to-BCD conversion.\u003c\/p\u003e \u003cp\u003e15.8.6 BCD-to-binary conversion.\u003c\/p\u003e \u003cp\u003e15.8.7 Heartbeat circuit.\u003c\/p\u003e \u003cp\u003e15.8.8 Rotating LED circuit.\u003c\/p\u003e \u003cp\u003e15.8.9 Discrete LED dimmer.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e16. PicoBlaze I\/O Interface.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e16.1 Overview.\u003c\/p\u003e \u003cp\u003e16.2 Output port.\u003c\/p\u003e \u003cp\u003e16.2.1 Output instruction and timing.\u003c\/p\u003e \u003cp\u003e16.2.2 Output interface.\u003c\/p\u003e \u003cp\u003e16.3 Input port.\u003c\/p\u003e \u003cp\u003e16.3.1 Input instruction and timing.\u003c\/p\u003e \u003cp\u003e16.3.2 Input interface.\u003c\/p\u003e \u003cp\u003e16.4 Square program with switch and seven-segment LED display interface.\u003c\/p\u003e \u003cp\u003e16.4.1 Output interface.\u003c\/p\u003e \u003cp\u003e16.4.2 Input interface.\u003c\/p\u003e \u003cp\u003e16.4.3 Assembly code development.\u003c\/p\u003e \u003cp\u003e16.4.4 VHDL code development.\u003c\/p\u003e \u003cp\u003e16.5 Square program with combinational multiplier and UART console.\u003c\/p\u003e \u003cp\u003e16.5.1 Multiplier interface.\u003c\/p\u003e \u003cp\u003e16.5.2 UART interface.\u003c\/p\u003e \u003cp\u003e16.5.3 Assembly code development.\u003c\/p\u003e \u003cp\u003e16.5.4 VHDL code development.\u003c\/p\u003e \u003cp\u003e16.6 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e16.7 Suggested experiments.\u003c\/p\u003e \u003cp\u003e16.7.1 Low-frequency counter I.\u003c\/p\u003e \u003cp\u003e16.7.2 Low frequency counter II.\u003c\/p\u003e \u003cp\u003e16.7.3 Auto-scaled low-frequency counter.\u003c\/p\u003e \u003cp\u003e16.7.4 Basic reaction timer with software timer.\u003c\/p\u003e \u003cp\u003e16.7.5 Basic reaction timer with hardware timer.\u003c\/p\u003e \u003cp\u003e16.7.6 Enhanced reaction timer.\u003c\/p\u003e \u003cp\u003e16.7.7 Small-screen mouse scribble circuit.\u003c\/p\u003e \u003cp\u003e16.7.8 Full-screen mouse scribble circuit.\u003c\/p\u003e \u003cp\u003e16.7.9 Enhanced rotating banner.\u003c\/p\u003e \u003cp\u003e16.7.10 Pong game.\u003c\/p\u003e \u003cp\u003e16.7.11 Text editor.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e17. PicoBlaze Interrupt Interface.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e17.1 Overview.\u003c\/p\u003e \u003cp\u003e17.2 Interrupt handling in PicoBlaze.\u003c\/p\u003e \u003cp\u003e17.2.1 Software processing.\u003c\/p\u003e \u003cp\u003e17.2.2 Timing.\u003c\/p\u003e \u003cp\u003e17.3 External interface.\u003c\/p\u003e \u003cp\u003e17.3.1 Single interrupt request.\u003c\/p\u003e \u003cp\u003e17.3.2 Multiple interrupt requests.\u003c\/p\u003e \u003cp\u003e17.4 Software development considerations.\u003c\/p\u003e \u003cp\u003e17.4.1 Interrupt as alternative scheduling scheme.\u003c\/p\u003e \u003cp\u003e17.4.2 Development of interrupt service routine.\u003c\/p\u003e \u003cp\u003e17.5 Design example.\u003c\/p\u003e \u003cp\u003e17.5.1 interrupt interface.\u003c\/p\u003e \u003cp\u003e17.5.2 Interrupt service routine development.\u003c\/p\u003e \u003cp\u003e17.5.3 Assembly code development.\u003c\/p\u003e \u003cp\u003e17.5.4 VHDL code development.\u003c\/p\u003e \u003cp\u003e17.6 Bibliographic notes.\u003c\/p\u003e \u003cp\u003e17.7 Suggested experiments.\u003c\/p\u003e \u003cp\u003e17.7.1 Alternative timer interrupt service routine.\u003c\/p\u003e \u003cp\u003e17.7.2 Programmable timer.\u003c\/p\u003e \u003cp\u003e17.7.3 Set-button interrupt service routine.\u003c\/p\u003e \u003cp\u003e17.7.4 Interrupt interface with two requests.\u003c\/p\u003e \u003cp\u003e17.7.5 Four-request interrupt controller.\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix A: Sample VHDL templates.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA.1 General VHDL constructs.\u003c\/p\u003e \u003cp\u003eA.1.1 Overall code structure.\u003c\/p\u003e \u003cp\u003eA.1.2 Component instantiation.\u003c\/p\u003e \u003cp\u003eA.2 Combinational circuits.\u003c\/p\u003e \u003cp\u003eA.2.1 Arithmetic operations.\u003c\/p\u003e \u003cp\u003eA.2.2 Fixed-amount shift operations.\u003c\/p\u003e \u003cp\u003eA.2.3 Routing with concurrent statements.\u003c\/p\u003e \u003cp\u003eA.2.4 Routing with case and if statements.\u003c\/p\u003e \u003cp\u003eA.2.5 Combinational circuit using process.\u003c\/p\u003e \u003cp\u003eA.3 Memory Components.\u003c\/p\u003e \u003cp\u003eA.3.1 Register template.\u003c\/p\u003e \u003cp\u003eA.3.2 Register file.\u003c\/p\u003e \u003cp\u003eA.4 Regular sequential circuits.\u003c\/p\u003e \u003cp\u003eA.5 FSM.\u003c\/p\u003e \u003cp\u003eA.6 FSMD.\u003c\/p\u003e \u003cp\u003eA.7 S3 board constraint file (s3.ucf).\u003c\/p\u003e \u003cp\u003eReferences.\u003c\/p\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default Title","offer_id":49402301940055,"sku":"9780470185315","price":92.66,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9780470185315.jpg?v=1730479997","url":"https:\/\/bookcurl.com\/products\/fpga-prototyping-by-vhdl-examples-9780470185315","provider":"Book Curl","version":"1.0","type":"link"}