{"product_id":"esd-9781118954461","title":"ESD","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003ci\u003eESD: Circuits and Devices 2nd Edition\u003c\/i\u003e provides a clear picture of layout and design of digital, analog, radio frequency (RF) and power applications for protection from electrostatic discharge (ESD), electrical overstress (EOS), and latchup phenomena from a generalist perspective and design synthesis practices providing optimum solutions in advanced technologies. \u003cp\u003eNew features in the 2nd edition:\u003c\/p\u003e \u003cul\u003e \u003cli\u003eExpanded treatment of ESD and analog design of passive devices of resistors, capacitors, inductors, and active devices of diodes, bipolar junction transistors, MOSFETs, and FINFETs.\u003c\/li\u003e \u003cli\u003eIncreased focus on ESD power clamps for power rails for CMOS, Bipolar, and BiCMOS.\u003c\/li\u003e \u003cli\u003eCo-synthesizing of semiconductor chip architecture and floor planning with ESD design practices for analog, and mixed signal applications\u003c\/li\u003e \u003cli\u003eIllustrates the influence of analog design practices on ESD design circuitry, from integration, synthesis and layout, to symmetry, matching, inter-di\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eAbout the Author xix\u003c\/p\u003e \u003cp\u003ePreface xxi\u003c\/p\u003e \u003cp\u003eAcknowledgments xxv\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Electrostatic Discharge 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Electricity and Electrostatic Discharge 1\u003c\/p\u003e \u003cp\u003e1.1.1 Electricity and Electrostatics 1\u003c\/p\u003e \u003cp\u003e1.1.2 Electrostatic Discharge 2\u003c\/p\u003e \u003cp\u003e1.1.3 Key ESD Patents, Inventions, and Innovations 4\u003c\/p\u003e \u003cp\u003e1.1.4 Table of ESD Defect Mechanisms 8\u003c\/p\u003e \u003cp\u003e1.2 Fundamental Concepts of ESD Design 11\u003c\/p\u003e \u003cp\u003e1.2.1 Concepts of ESD Design 12\u003c\/p\u003e \u003cp\u003e1.2.2 Device Response to External Events 13\u003c\/p\u003e \u003cp\u003e1.2.3 Alternate Current Loops 14\u003c\/p\u003e \u003cp\u003e1.2.4 Switches 14\u003c\/p\u003e \u003cp\u003e1.2.5 Decoupling of Current Paths 15\u003c\/p\u003e \u003cp\u003e1.2.6 Decoupling of Feedback Loops 15\u003c\/p\u003e \u003cp\u003e1.2.7 Decoupling of Power Rails 15\u003c\/p\u003e \u003cp\u003e1.2.8 Local and Global Distribution 15\u003c\/p\u003e \u003cp\u003e1.2.9 Usage of Parasitic Elements 16\u003c\/p\u003e \u003cp\u003e1.2.10 Buffering 16\u003c\/p\u003e \u003cp\u003e1.2.11 Ballasting 16\u003c\/p\u003e \u003cp\u003e1.2.12 Unused Section of a Semiconductor Device, Circuit, or Chip Function 17\u003c\/p\u003e \u003cp\u003e1.2.13 Impedance Matching between Floating and Nonfloating Networks 17\u003c\/p\u003e \u003cp\u003e1.2.14 Unconnected Structures 17\u003c\/p\u003e \u003cp\u003e1.2.15 Utilization of Dummy Structures and Dummy Circuits 17\u003c\/p\u003e \u003cp\u003e1.2.16 Nonscalable Source Events 17\u003c\/p\u003e \u003cp\u003e1.2.17 Area Efficiency 18\u003c\/p\u003e \u003cp\u003e1.3 ESD, EOS, EMI, Electromagnetic Compatibility, and Latchup 18\u003c\/p\u003e \u003cp\u003e1.3.1 Esd 18\u003c\/p\u003e \u003cp\u003e1.3.2 Electrical Overstress 19\u003c\/p\u003e \u003cp\u003e1.3.3 Electromagnetic Interference 19\u003c\/p\u003e \u003cp\u003e1.3.4 Electromagnetic Compatibility 19\u003c\/p\u003e \u003cp\u003e1.3.5 Latchup 19\u003c\/p\u003e \u003cp\u003e1.4 ESD Models 19\u003c\/p\u003e \u003cp\u003e1.4.1 Human Body Model 20\u003c\/p\u003e \u003cp\u003e1.4.2 Machine Model 21\u003c\/p\u003e \u003cp\u003e1.4.3 Cassette Model (Small Charge Model) 24\u003c\/p\u003e \u003cp\u003e1.4.4 Charged Device Model 24\u003c\/p\u003e \u003cp\u003e1.4.5 Transmission Line Pulse 25\u003c\/p\u003e \u003cp\u003e1.4.6 Very Fast Transmission Line Pulse 26\u003c\/p\u003e \u003cp\u003e1.5 ESD and System-Level Test Models 28\u003c\/p\u003e \u003cp\u003e1.5.1 IEC 61000-4-2 29\u003c\/p\u003e \u003cp\u003e1.5.2 Human Metal Model 29\u003c\/p\u003e \u003cp\u003e1.5.3 IEC 61000-4-5 30\u003c\/p\u003e \u003cp\u003e1.5.4 Charged Board Model 31\u003c\/p\u003e \u003cp\u003e1.5.5 Cable Discharge Event 32\u003c\/p\u003e \u003cp\u003e1.5.5.1 CDE and Scaling 36\u003c\/p\u003e \u003cp\u003e1.5.5.2 CDE—Cable Measurement Equipment 37\u003c\/p\u003e \u003cp\u003e1.5.5.3 Cable Configuration—Test Configuration 38\u003c\/p\u003e \u003cp\u003e1.5.5.4 Cable Configuration—Floating Cable 38\u003c\/p\u003e \u003cp\u003e1.5.5.5 Cable Configuration—Held Cable 38\u003c\/p\u003e \u003cp\u003e1.5.5.6 CDE—Peak Current versus Charged Voltage 39\u003c\/p\u003e \u003cp\u003e1.5.5.7 CDE—Plateau Current versus Charged Voltage 39\u003c\/p\u003e \u003cp\u003e1.6 Time Constants 39\u003c\/p\u003e \u003cp\u003e1.6.1 Characteristic Times 39\u003c\/p\u003e \u003cp\u003e1.6.2 Electrostatic and Magnetostatic Time Constants 39\u003c\/p\u003e \u003cp\u003e1.6.2.1 Charge Relaxation Time 39\u003c\/p\u003e \u003cp\u003e1.6.2.2 Magnetic Diffusion Time 40\u003c\/p\u003e \u003cp\u003e1.6.2.3 Electromagnetic Wave Transit Time 40\u003c\/p\u003e \u003cp\u003e1.6.3 Thermal Time Constants 42\u003c\/p\u003e \u003cp\u003e1.6.3.1 Heat Capacity 42\u003c\/p\u003e \u003cp\u003e1.6.3.2 Thermal Diffusion 42\u003c\/p\u003e \u003cp\u003e1.6.3.3 Heat Transport Equation 42\u003c\/p\u003e \u003cp\u003e1.6.4 Thermal Physics Time Constants 43\u003c\/p\u003e \u003cp\u003e1.6.4.1 Adiabatic, Thermal Diffusion Timescale, and Steady State 44\u003c\/p\u003e \u003cp\u003e1.6.5 Semiconductor Device Time Constants 45\u003c\/p\u003e \u003cp\u003e1.6.5.1 Depletion Region Transit Time 45\u003c\/p\u003e \u003cp\u003e1.6.5.2 Silicon Diode Storage Delay Time 45\u003c\/p\u003e \u003cp\u003e1.6.5.3 Bipolar Base Transit Time 46\u003c\/p\u003e \u003cp\u003e1.6.5.4 Bipolar Turn-on Transient Time 46\u003c\/p\u003e \u003cp\u003e1.6.5.5 Bipolar Turn-off Transient Time 46\u003c\/p\u003e \u003cp\u003e1.6.5.6 Bipolar Emitter Transition Capacitance Charging Time 46\u003c\/p\u003e \u003cp\u003e1.6.5.7 Bipolar Collector Capacitance Charging Time 47\u003c\/p\u003e \u003cp\u003e1.6.5.8 SCR Time Response 47\u003c\/p\u003e \u003cp\u003e1.6.5.9 MOSFET Transit Time 47\u003c\/p\u003e \u003cp\u003e1.6.5.10 MOSFET Drain Charging Time 48\u003c\/p\u003e \u003cp\u003e1.6.5.11 MOSFET Gate Charging Time 48\u003c\/p\u003e \u003cp\u003e1.6.5.12 MOSFET Parasitic Bipolar Response Time 48\u003c\/p\u003e \u003cp\u003e1.6.6 Circuit Time Constants 49\u003c\/p\u003e \u003cp\u003e1.6.6.1 Pad Capacitance 49\u003c\/p\u003e \u003cp\u003e1.6.6.2 Half-Pass TGs 49\u003c\/p\u003e \u003cp\u003e1.6.6.3 N-Channel Half-Pass Transistor Charging Time Constant 49\u003c\/p\u003e \u003cp\u003e1.6.6.4 Half-pass Transistor TG Discharge Time Constant 49\u003c\/p\u003e \u003cp\u003e1.6.6.5 P-Channel Half-Pass Transistor Charging Time Constant 49\u003c\/p\u003e \u003cp\u003e1.6.6.6 Inverter Propagation Delay Time Constants 50\u003c\/p\u003e \u003cp\u003e1.6.6.7 High-to-Low and Low-to-High Transition Time 50\u003c\/p\u003e \u003cp\u003e1.6.6.8 Inverter Propagation Delay Time 51\u003c\/p\u003e \u003cp\u003e1.6.6.9 Series N-channel MOSFETs Discharge Delay Time 51\u003c\/p\u003e \u003cp\u003e1.6.6.10 Series P-channel MOSFETs Charge Delay Time 51\u003c\/p\u003e \u003cp\u003e1.6.7 Chip-Level Time Constants 52\u003c\/p\u003e \u003cp\u003e1.6.7.1 Peripheral I\/O Power Bus Time Constant 52\u003c\/p\u003e \u003cp\u003e1.6.7.2 Core Chip Time Constant 53\u003c\/p\u003e \u003cp\u003e1.6.7.3 Substrate Time Constants 53\u003c\/p\u003e \u003cp\u003e1.6.7.4 Package Time Constants 54\u003c\/p\u003e \u003cp\u003e1.6.8 ESD Time Constants 54\u003c\/p\u003e \u003cp\u003e1.6.8.1 ESD Events 55\u003c\/p\u003e \u003cp\u003e1.6.8.2 HBM Characteristic Time 55\u003c\/p\u003e \u003cp\u003e1.6.8.3 mm Characteristic Time 56\u003c\/p\u003e \u003cp\u003e1.6.8.4 CDM Characteristic Time 57\u003c\/p\u003e \u003cp\u003e1.6.8.5 Charged Cable Model Characteristic Time 57\u003c\/p\u003e \u003cp\u003e1.6.8.6 CDE Model 57\u003c\/p\u003e \u003cp\u003e1.6.8.7 CCM Characteristic Time 58\u003c\/p\u003e \u003cp\u003e1.6.8.8 TLP Model Characteristic Time 58\u003c\/p\u003e \u003cp\u003e1.6.8.9 VF-TLP Model Characteristic Time 59\u003c\/p\u003e \u003cp\u003e1.7 Capacitance, Resistance, and Inductance and ESD 59\u003c\/p\u003e \u003cp\u003e1.7.1 The Role of Capacitance 59\u003c\/p\u003e \u003cp\u003e1.7.2 The Role of Resistance 60\u003c\/p\u003e \u003cp\u003e1.7.3 The Role of Inductance 61\u003c\/p\u003e \u003cp\u003e1.8 Rules of Thumb and ESD 62\u003c\/p\u003e \u003cp\u003e1.8.1 ESD Design: An “ESD Ohm’s Law”—A Simple ESD Rule-of-Thumb Design Approach 62\u003c\/p\u003e \u003cp\u003e1.9 ESD Scaling 63\u003c\/p\u003e \u003cp\u003e1.10 Lumped versus Distributed Analysis and ESD 65\u003c\/p\u003e \u003cp\u003e1.10.1 Current and Voltage Distributions 65\u003c\/p\u003e \u003cp\u003e1.10.2 Lumped versus Distributed Systems 66\u003c\/p\u003e \u003cp\u003e1.10.3 Distributed Systems—Ladder Network Analysis 67\u003c\/p\u003e \u003cp\u003e1.10.4 RLC Distributed Systems 69\u003c\/p\u003e \u003cp\u003e1.10.5 Resistor–Capacitor (RC) Distributed Systems 74\u003c\/p\u003e \u003cp\u003e1.10.6 RG Distributed Systems 77\u003c\/p\u003e \u003cp\u003e1.11 ESD Metrics: Chip-Level ESD Metrics and Figures of Merit 79\u003c\/p\u003e \u003cp\u003e1.11.1 Chip Mean Pin Power-to-Failure 80\u003c\/p\u003e \u003cp\u003e1.11.2 Chip Pin Standard Deviation Power-to-Failure 80\u003c\/p\u003e \u003cp\u003e1.11.3 Chip Mean Pin Power-to-Failure to ESD Specification Margin 80\u003c\/p\u003e \u003cp\u003e1.11.4 Worst-Case Pin Power-to-Failure to Specification ESD Margin 81\u003c\/p\u003e \u003cp\u003e1.11.5 Total ESD Area to Total Chip Area Ratio 81\u003c\/p\u003e \u003cp\u003e1.11.6 ESD Area to I\/O Area Ratio 81\u003c\/p\u003e \u003cp\u003e1.11.7 Circuit ESD Metrics 82\u003c\/p\u003e \u003cp\u003e1.11.7.1 Circuit ESD Protection Level to ESD Loading Effect 82\u003c\/p\u003e \u003cp\u003e1.11.7.2 Circuit Performance to ESD Loading Effect 82\u003c\/p\u003e \u003cp\u003e1.11.7.3 ESD Area to Total Circuit Area Ratio 83\u003c\/p\u003e \u003cp\u003e1.11.7.4 Circuit ESD Level to Specification Margin 83\u003c\/p\u003e \u003cp\u003e1.11.7.5 Device ESD Metric 83\u003c\/p\u003e \u003cp\u003e1.12 ESD Quality and Reliability Business Metrics 84\u003c\/p\u003e \u003cp\u003e1.13 Twelve Steps to Building an ESD Strategy 85\u003c\/p\u003e \u003cp\u003e1.14 Summary and Closing Comments 86\u003c\/p\u003e \u003cp\u003eProblems 87\u003c\/p\u003e \u003cp\u003eReferences 87\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Design Synthesis 94\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Synthesis and Architecture of a Semiconductor Chip for ESD Protection 94\u003c\/p\u003e \u003cp\u003e2.2 Electrical and Spatial Connectivity 95\u003c\/p\u003e \u003cp\u003e2.2.1 Electrical Connectivity 95\u003c\/p\u003e \u003cp\u003e2.2.2 Thermal Connectivity 95\u003c\/p\u003e \u003cp\u003e2.2.3 Spatial Connectivity 96\u003c\/p\u003e \u003cp\u003e2.3 ESD, Latchup, and Noise 96\u003c\/p\u003e \u003cp\u003e2.3.1 Noise 97\u003c\/p\u003e \u003cp\u003e2.3.2 Latchup 98\u003c\/p\u003e \u003cp\u003e2.4 Interface Circuits and ESD Elements 98\u003c\/p\u003e \u003cp\u003e2.5 ESD Power Clamp Networks 101\u003c\/p\u003e \u003cp\u003e2.5.1 Placement of ESD Power Clamps 104\u003c\/p\u003e \u003cp\u003e2.6 ESD Rail-to-Rail Networks 105\u003c\/p\u003e \u003cp\u003e2.6.1 Placement of ESD Rail-to-Rail Networks 107\u003c\/p\u003e \u003cp\u003e2.6.2 Peripheral and Array I\/O 107\u003c\/p\u003e \u003cp\u003e2.7 Guard Rings 109\u003c\/p\u003e \u003cp\u003e2.8 Pads, Floating Pads, and No-connect Pads 111\u003c\/p\u003e \u003cp\u003e2.9 Structures under Bond Pads 112\u003c\/p\u003e \u003cp\u003e2.10 Mixed Signal Architecture: CMOS 112\u003c\/p\u003e \u003cp\u003e2.10.1 Digital and Analog CMOS Architecture 114\u003c\/p\u003e \u003cp\u003e2.10.2 Digital and Analog Floor Plan: Placement of Analog Circuits 114\u003c\/p\u003e \u003cp\u003e2.11 MS Architecture: Digital, Analog, and RF Architecture 116\u003c\/p\u003e \u003cp\u003e2.12 Digital-to-Analog Interdomain Signal Line Failures 118\u003c\/p\u003e \u003cp\u003e2.12.1 Digital-to-Analog Core Spatial Isolation 120\u003c\/p\u003e \u003cp\u003e2.12.2 Digital-to-Analog Core Ground Coupling 120\u003c\/p\u003e \u003cp\u003e2.12.3 Digital-to-Analog Core Resistive Ground Coupling 120\u003c\/p\u003e \u003cp\u003e2.12.4 Digital-to-Analog Core Diode Ground Coupling 120\u003c\/p\u003e \u003cp\u003e2.12.5 Domain-to-Domain Signal Line ESD Networks 122\u003c\/p\u003e \u003cp\u003e2.12.6 Domain-to-Domain Third-Party Coupling Networks 122\u003c\/p\u003e \u003cp\u003e2.12.7 Domain-to-Domain Cross-Domain ESD Power Clamp 123\u003c\/p\u003e \u003cp\u003e2.13 Summary and Closing Comments 124\u003c\/p\u003e \u003cp\u003eProblems 124\u003c\/p\u003e \u003cp\u003eReferences 125\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 MOSFET ESD Design 129\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Basic ESD Design Concepts 129\u003c\/p\u003e \u003cp\u003e3.2 ESD MOSFET Design: Channel Length 136\u003c\/p\u003e \u003cp\u003e3.2.1 Channel Length and Linewidth Control 136\u003c\/p\u003e \u003cp\u003e3.2.2 ACLV Control 138\u003c\/p\u003e \u003cp\u003e3.2.3 MOSFET ESD Design Practices 142\u003c\/p\u003e \u003cp\u003e3.3 N-Channel MOSFET Design: Channel Width 143\u003c\/p\u003e \u003cp\u003e3.4 ESD MOSFET Design: Contacts 144\u003c\/p\u003e \u003cp\u003e3.4.1 Gate-to-Contact Spacing 144\u003c\/p\u003e \u003cp\u003e3.4.1.1 Off-Axis Current Distribution 148\u003c\/p\u003e \u003cp\u003e3.4.1.2 Self-Heating Equienergy Contours 148\u003c\/p\u003e \u003cp\u003e3.4.2 Contact-to-Contact Space 149\u003c\/p\u003e \u003cp\u003e3.4.3 ESD Design: End Contact 152\u003c\/p\u003e \u003cp\u003e3.4.4 ESD MOSFET Design: Contacts to Isolation Edge 153\u003c\/p\u003e \u003cp\u003e3.5 ESD MOSFET Design: Metal Distribution 153\u003c\/p\u003e \u003cp\u003e3.5.1 MOSFET Metal Bus Design and Current Distribution 153\u003c\/p\u003e \u003cp\u003e3.5.2 MOSFET Ladder Network Model 154\u003c\/p\u003e \u003cp\u003e3.5.3 MOSFET Wiring: Parallel Current Distribution 158\u003c\/p\u003e \u003cp\u003e3.5.4 MOSFET Wiring: Antiparallel Current Distribution 162\u003c\/p\u003e \u003cp\u003e3.6 ESD MOSFET Design: Silicide Masking 165\u003c\/p\u003e \u003cp\u003e3.6.1 ESD MOSFET Design: Silicide Mask Design 165\u003c\/p\u003e \u003cp\u003e3.6.2 ESD MOSFET Design: Silicide Mask Design over Source and Drain 166\u003c\/p\u003e \u003cp\u003e3.6.3 ESD MOSFET Design: Silicide Mask Design over Gate 167\u003c\/p\u003e \u003cp\u003e3.7 ESD MOSFET Design: Series Cascode Configurations 170\u003c\/p\u003e \u003cp\u003e3.7.1 MOSFET ESD Design: Series Cascode MOSFET 170\u003c\/p\u003e \u003cp\u003e3.7.2 Integrated Cascoded MOSFETs 171\u003c\/p\u003e \u003cp\u003e3.8 ESD MOSFET Design: Multifinger MOSFET Design—Integration of Coupling and Ballasting Techniques 174\u003c\/p\u003e \u003cp\u003e3.8.1 Grounded-Gate Resistor-Ballasted MOSFET 174\u003c\/p\u003e \u003cp\u003e3.8.2 Soft Substrate Grounded-Gate Resistor-Ballasted MOSFET 176\u003c\/p\u003e \u003cp\u003e3.8.3 Gate-Coupled Domino Resistor-Ballasted MOSFET 177\u003c\/p\u003e \u003cp\u003e3.8.4 MOSFET Source-Initiated Gate-Bootstrapped Resistor-Ballasted Multifinger MOSFET with MOSFET 179\u003c\/p\u003e \u003cp\u003e3.8.5 MOSFET Source-Initiated Gate-Bootstrapped Resistor-Ballasted Multifinger MOSFET with Diode 180\u003c\/p\u003e \u003cp\u003e3.9 ESD MOSFET Design: Enclosed Drain Design Practice 181\u003c\/p\u003e \u003cp\u003e3.10 ESD MOSFET Interconnect Ballasting Design 182\u003c\/p\u003e \u003cp\u003e3.11 ESD MOSFET Design: Source and Drain Segmentation 184\u003c\/p\u003e \u003cp\u003e3.12 MOSFET Design for Analog Applications 185\u003c\/p\u003e \u003cp\u003e3.13 Summary and Closing Comments 187\u003c\/p\u003e \u003cp\u003eProblems 187\u003c\/p\u003e \u003cp\u003eReferences 188\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 ESD Design: Diode Design 191\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 ESD Diode Design: ESD Basics 191\u003c\/p\u003e \u003cp\u003e4.1.1 Basic ESD Design Concepts 191\u003c\/p\u003e \u003cp\u003e4.1.2 ESD Diode Design: ESD Diode Operation 193\u003c\/p\u003e \u003cp\u003e4.2 ESD Diode Anode Design 194\u003c\/p\u003e \u003cp\u003e4.2.1 P+ Diffusion Anode Width Effect 195\u003c\/p\u003e \u003cp\u003e4.2.2 P+ Anode Contacts 195\u003c\/p\u003e \u003cp\u003e4.2.3 P+ Anode Silicide to Edge Design 195\u003c\/p\u003e \u003cp\u003e4.2.4 P+ Anode to N+ Cathode Isolation Spacing 198\u003c\/p\u003e \u003cp\u003e4.2.5 P+ Anode Diode End Effects 198\u003c\/p\u003e \u003cp\u003e4.2.6 Circular and Octagonal ESD Diode Design 200\u003c\/p\u003e \u003cp\u003e4.3 ESD Diode Design: Interconnect Wiring 202\u003c\/p\u003e \u003cp\u003e4.3.1 Parallel Wiring Design 203\u003c\/p\u003e \u003cp\u003e4.3.2 Antiparallel Wiring Design 203\u003c\/p\u003e \u003cp\u003e4.3.3 Quantized Tapered Parallel and Antiparallel Wiring 203\u003c\/p\u003e \u003cp\u003e4.3.4 Continuous Tapered Antiparallel and Parallel Wiring 203\u003c\/p\u003e \u003cp\u003e4.3.5 Perpendicular (and Broadside) Wiring with Center-Fed Design 205\u003c\/p\u003e \u003cp\u003e4.3.6 Perpendicular (and Broadside) with Uniform Metal Width 206\u003c\/p\u003e \u003cp\u003e4.3.7 Perpendicular (and Broadside) Wiring with T-Shaped Extensions 207\u003c\/p\u003e \u003cp\u003e4.3.8 Metal Design for Structures under Bond Pads 208\u003c\/p\u003e \u003cp\u003e4.4 ESD Design: Polysilicon-Bound Diode Designs 210\u003c\/p\u003e \u003cp\u003e4.4.1 ESD Design Issues with Polysilicon-Bound Diode Structures 212\u003c\/p\u003e \u003cp\u003e4.5 N-Well Diode Design 213\u003c\/p\u003e \u003cp\u003e4.5.1 N-Well Diode Wiring Design 213\u003c\/p\u003e \u003cp\u003e4.5.2 N-Well Contact Density 214\u003c\/p\u003e \u003cp\u003e4.5.3 N-Well ESD Design, Guard Rings, and Adjacent Structures 214\u003c\/p\u003e \u003cp\u003e4.6 N+\/P Substrate Diode Design 216\u003c\/p\u003e \u003cp\u003e4.7 ESD Design: Diode String Design 217\u003c\/p\u003e \u003cp\u003e4.7.1 ESD Design: Diode String Design—Architecture 223\u003c\/p\u003e \u003cp\u003e4.7.2 Diode String Elements in Multiple I\/O Environments 223\u003c\/p\u003e \u003cp\u003e4.7.3 Integration of Signal Pads 224\u003c\/p\u003e \u003cp\u003e4.7.4 ESD Design: Diode String Design—Darlington Amplification 227\u003c\/p\u003e \u003cp\u003e4.7.5 ESD Design: Diode String Design—Area Scaling 229\u003c\/p\u003e \u003cp\u003e4.8 Triple-Well ESD Diode Design 231\u003c\/p\u003e \u003cp\u003e4.9 Summary and Closing Comments 234\u003c\/p\u003e \u003cp\u003eProblems 234\u003c\/p\u003e \u003cp\u003eReferences 236\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 ESD Design: Passive Resistors 239\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 N-Well Resistors 239\u003c\/p\u003e \u003cp\u003e5.1.1 N-Well ESD Design Issues 239\u003c\/p\u003e \u003cp\u003e5.1.2 N-Well Resistors ESD Design Issues: Integration with MOSFETs 243\u003c\/p\u003e \u003cp\u003e5.1.3 N-Well Resistor Ballasting Design 245\u003c\/p\u003e \u003cp\u003e5.2 N-Diffusion Resistor Design 248\u003c\/p\u003e \u003cp\u003e5.2.1 N-Diffusion Resistors for ESD Protection 248\u003c\/p\u003e \u003cp\u003e5.2.2 N-Diffusion Resistors Ballasting Design 249\u003c\/p\u003e \u003cp\u003e5.3 P-Diffusion Resistor Design 252\u003c\/p\u003e \u003cp\u003e5.3.1 P-Diffusion Resistors for ESD Protection 253\u003c\/p\u003e \u003cp\u003e5.4 Br 254\u003c\/p\u003e \u003cp\u003e5.4.1 BR Design 254\u003c\/p\u003e \u003cp\u003e5.4.2 BR as an ESD Diode Element 256\u003c\/p\u003e \u003cp\u003e5.4.3 BR as an ESD HBM and CDM Element 257\u003c\/p\u003e \u003cp\u003e5.4.4 BR Ballasting 260\u003c\/p\u003e \u003cp\u003e5.4.5 BR Design Integration and ESD 261\u003c\/p\u003e \u003cp\u003e5.4.6 BR: Current Robbing and Balancing ESD and Resistor Parasitics 263\u003c\/p\u003e \u003cp\u003e5.4.7 BR-to-BR ESD Failure Mechanisms 266\u003c\/p\u003e \u003cp\u003e5.4.8 BR Gate Connection and Failure Mechanisms 267\u003c\/p\u003e \u003cp\u003e5.5 Summary and Closing Comments 268\u003c\/p\u003e \u003cp\u003eProblems 268\u003c\/p\u003e \u003cp\u003eReferences 270\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Passives for Digital, Analog, and RF Applications 271\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Analog Design Layout Revisited 271\u003c\/p\u003e \u003cp\u003e6.1.1 Analog Design: Local Matching 272\u003c\/p\u003e \u003cp\u003e6.1.2 Analog Design: Global Matching 272\u003c\/p\u003e \u003cp\u003e6.1.3 Symmetry 273\u003c\/p\u003e \u003cp\u003e6.1.4 Layout Design Symmetry 273\u003c\/p\u003e \u003cp\u003e6.1.5 Thermal Symmetry 273\u003c\/p\u003e \u003cp\u003e6.2 Common Centroid Design 274\u003c\/p\u003e \u003cp\u003e6.2.1 Common Centroid Arrays 274\u003c\/p\u003e \u003cp\u003e6.2.2 One-Axis Common Centroid Design 275\u003c\/p\u003e \u003cp\u003e6.2.3 Two-Axis Common Centroid Design 275\u003c\/p\u003e \u003cp\u003e6.3 Interdigitation Design 275\u003c\/p\u003e \u003cp\u003e6.4 Common Centroid and Interdigitation Design 276\u003c\/p\u003e \u003cp\u003e6.5 Passive Element Design 277\u003c\/p\u003e \u003cp\u003e6.6 Resistor Element Design 277\u003c\/p\u003e \u003cp\u003e6.6.1 Resistor Element Design: Dogbone Layout 277\u003c\/p\u003e \u003cp\u003e6.6.2 Resistor Design: Analog Interdigitated Layout 278\u003c\/p\u003e \u003cp\u003e6.6.3 Dummy Resistor Layout 278\u003c\/p\u003e \u003cp\u003e6.6.4 Thermoelectric Cancellation Layout 279\u003c\/p\u003e \u003cp\u003e6.6.5 Electrostatic Shield 280\u003c\/p\u003e \u003cp\u003e6.6.6 Interdigitated Resistors and ESD Parasitics 281\u003c\/p\u003e \u003cp\u003e6.7 Capacitor Element Design 283\u003c\/p\u003e \u003cp\u003e6.8 Inductor Element Design 283\u003c\/p\u003e \u003cp\u003e6.9 Summary and Closing Comments 286\u003c\/p\u003e \u003cp\u003eProblems 286\u003c\/p\u003e \u003cp\u003eReferences 286\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Off-Chip Drivers and ESD 288\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Off-chip Drivers 288\u003c\/p\u003e \u003cp\u003e7.1.1 OCD I\/O Standards and ESD 289\u003c\/p\u003e \u003cp\u003e7.1.2 OCD ESD Design Basics 290\u003c\/p\u003e \u003cp\u003e7.1.3 OCD: CMOS Asymmetric Pull-Up\/Pull-Down 291\u003c\/p\u003e \u003cp\u003e7.1.4 OCD: CMOS Symmetric Pull-Up\/Pull-Down 292\u003c\/p\u003e \u003cp\u003e7.1.5 OCD: Gunning Transceiver Logic 294\u003c\/p\u003e \u003cp\u003e7.1.6 OCD: High-Speed Transceiver Logic 295\u003c\/p\u003e \u003cp\u003e7.1.7 OCD: Stub Series-Terminated Logic 296\u003c\/p\u003e \u003cp\u003e7.2 OCDs: mvi 297\u003c\/p\u003e \u003cp\u003e7.3 OCDs: Self-Bias Well OCD Networks 297\u003c\/p\u003e \u003cp\u003e7.3.1 Self-Bias Well OCD Networks 297\u003c\/p\u003e \u003cp\u003e7.3.2 ESD Protection Networks for Self-Bias Well OCD Networks 300\u003c\/p\u003e \u003cp\u003e7.4 Programmable Impedance OCD Network 302\u003c\/p\u003e \u003cp\u003e7.4.1 OCD: PIMP OCD Networks 302\u003c\/p\u003e \u003cp\u003e7.4.2 ESD Input Protection Networks for PIMP OCDs 305\u003c\/p\u003e \u003cp\u003e7.5 OCDs: Universal OCDs 305\u003c\/p\u003e \u003cp\u003e7.6 OCDs: Gate-Array OCD Design 306\u003c\/p\u003e \u003cp\u003e7.6.1 Gate-Array OCD ESD Design Practices 306\u003c\/p\u003e \u003cp\u003e7.6.2 Gate-Array OCD Design—Usage of Unused Elements 306\u003c\/p\u003e \u003cp\u003e7.6.3 Gate-Array OCD Design—Impedance Matching of Unused Elements 307\u003c\/p\u003e \u003cp\u003e7.6.4 OCD ESD Design—Power Rails Over Multifinger MOSFETs 308\u003c\/p\u003e \u003cp\u003e7.7 OCDs: Gate-Modulated Networks 309\u003c\/p\u003e \u003cp\u003e7.7.1 OCD: Gate-Modulated MOSFET ESD Network 309\u003c\/p\u003e \u003cp\u003e7.7.2 OCD Simplified Gate-Modulated Network 310\u003c\/p\u003e \u003cp\u003e7.8 OCDs ESD Design: Integration of Coupling and Ballasting Techniques 311\u003c\/p\u003e \u003cp\u003e7.8.1 Ballasting and Coupling 311\u003c\/p\u003e \u003cp\u003e7.8.2 MOSFET Source-Initiated Gate-Bootstrapped Resistor-Ballasted Multifinger MOSFET with Diode 311\u003c\/p\u003e \u003cp\u003e7.8.3 MOSFET Source-Initiated Gate-Bootstrapped Resistor-Ballasted Multifinger MOSFET with an MOSFET 312\u003c\/p\u003e \u003cp\u003e7.8.4 Gate-Coupled Domino Resistor-Ballasted MOSFET 314\u003c\/p\u003e \u003cp\u003e7.9 Substrate-Modulated Resistor-Ballasted MOSFET 315\u003c\/p\u003e \u003cp\u003e7.10 Summary and Closing Comments 317\u003c\/p\u003e \u003cp\u003eProblems 318\u003c\/p\u003e \u003cp\u003eReferences 319\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 Receiver Circuits 322\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Receivers and ESD 322\u003c\/p\u003e \u003cp\u003e8.1.1 Receivers and Receiver Delay Time 323\u003c\/p\u003e \u003cp\u003e8.1.2 ESD Loading Effect on Receiver Performance 323\u003c\/p\u003e \u003cp\u003e8.2 Receivers and ESD 324\u003c\/p\u003e \u003cp\u003e8.2.1 Receivers and HBM 324\u003c\/p\u003e \u003cp\u003e8.2.2 Receivers and CDM 325\u003c\/p\u003e \u003cp\u003e8.3 Receivers and Receiver Evolution 327\u003c\/p\u003e \u003cp\u003e8.3.1 Receiver Circuits with Half-Pass TG 327\u003c\/p\u003e \u003cp\u003e8.3.2 Receiver with Full-Pass TG 330\u003c\/p\u003e \u003cp\u003e8.3.3 Receiver, Half-Pass TG, and Keeper Network 332\u003c\/p\u003e \u003cp\u003e8.3.4 Receiver, Half-Pass TG, and the Modified Keeper Network 335\u003c\/p\u003e \u003cp\u003e8.4 Receiver Circuits with Pseudozero V T Half-Pass TG 337\u003c\/p\u003e \u003cp\u003e8.5 Receiver with ZVT TG 339\u003c\/p\u003e \u003cp\u003e8.6 Receiver Circuits with Bleed Transistors 342\u003c\/p\u003e \u003cp\u003e8.7 Receiver Circuits with Test Functions 343\u003c\/p\u003e \u003cp\u003e8.8 Receiver with Schmitt Trigger Feedback Network 344\u003c\/p\u003e \u003cp\u003e8.9 Bipolar Transistor Receivers 347\u003c\/p\u003e \u003cp\u003e8.9.1 Bipolar Single-Ended Receiver Circuits 347\u003c\/p\u003e \u003cp\u003e8.10 Differential Receivers 349\u003c\/p\u003e \u003cp\u003e8.10.1 Signal Differential Receiver 350\u003c\/p\u003e \u003cp\u003e8.10.2 Signal CMOS Differential Receivers 350\u003c\/p\u003e \u003cp\u003e8.10.3 Signal Bipolar Differential Receivers 350\u003c\/p\u003e \u003cp\u003e8.11 CMOS Differential Receiver with Analog Layout Concepts 355\u003c\/p\u003e \u003cp\u003e8.11.1 CMOS Differential Receiver Capacitance Loading 355\u003c\/p\u003e \u003cp\u003e8.11.2 CMOS Differential Receiver ESD Mismatch 356\u003c\/p\u003e \u003cp\u003e8.11.3 Analog Differential Pair ESD Signal Pin Matching with Common Well Layout 359\u003c\/p\u003e \u003cp\u003e8.11.4 Analog Differential Pair Common Centroid Design Layout: Signal Pin-to-Signal Pin and Parasitic ESD Elements 359\u003c\/p\u003e \u003cp\u003e8.12 Summary and Closing Comments 363\u003c\/p\u003e \u003cp\u003eProblems 364\u003c\/p\u003e \u003cp\u003eReferences 366\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 Silicon on Insulator (SOI) ESD Design 368\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Silicon on Insulator ESD Design Concepts 368\u003c\/p\u003e \u003cp\u003e9.2 SOI Design MOSFET with Body Contact: T-Shape Layout Style 372\u003c\/p\u003e \u003cp\u003e9.3 SOI Lateral Diode Structure 375\u003c\/p\u003e \u003cp\u003e9.3.1 Transistors: Bulk Versus SOI Technology 375\u003c\/p\u003e \u003cp\u003e9.3.2 SOI Lateral Diode Design 376\u003c\/p\u003e \u003cp\u003e9.3.3 SOI Lateral Diode Perimeter Design 376\u003c\/p\u003e \u003cp\u003e9.3.4 SOI Lateral Diode Channel Length Design 377\u003c\/p\u003e \u003cp\u003e9.3.5 SOI Lateral P+\/N−\/N+ Diode Structure 377\u003c\/p\u003e \u003cp\u003e9.3.6 SOI Lateral P+\/P−\/N+ Diode Structure 377\u003c\/p\u003e \u003cp\u003e9.3.7 SOI Lateral P+\/P−\/N−\/N+ Diode Structure 378\u003c\/p\u003e \u003cp\u003e9.3.8 SOI Lateral Ungated P+\/P−\/N−\/N+ Diode Structure 379\u003c\/p\u003e \u003cp\u003e9.3.9 SOI Lateral Diode Structures and SOI MOSFET Halos 379\u003c\/p\u003e \u003cp\u003e9.4 SOI BR Elements 380\u003c\/p\u003e \u003cp\u003e9.5 Dynamic Threshold SOI MOSFET 381\u003c\/p\u003e \u003cp\u003e9.6 SOI Dual-Gate MOSFET 384\u003c\/p\u003e \u003cp\u003e9.7 SOI ESD Design: Mixed Voltage T-Shape Layout Style 384\u003c\/p\u003e \u003cp\u003e9.8 SOI ESD Design: Mixed Voltage Diode Strings 384\u003c\/p\u003e \u003cp\u003e9.9 SOI ESD Design: Double-Diode Network 385\u003c\/p\u003e \u003cp\u003e9.10 Bulk to SOI ESD Design Remapping 387\u003c\/p\u003e \u003cp\u003e9.11 SOI ESD Design in MVI Environments 391\u003c\/p\u003e \u003cp\u003e9.12 Comparison of Bulk to SOI ESD Results 393\u003c\/p\u003e \u003cp\u003e9.13 SOI ESD Design with Aluminum Interconnects 394\u003c\/p\u003e \u003cp\u003e9.14 SOI ESD Design with Copper Interconnects 395\u003c\/p\u003e \u003cp\u003e9.15 SOI ESD Design with Gate Circuitry 397\u003c\/p\u003e \u003cp\u003e9.16 SOI FinFET Structure 399\u003c\/p\u003e \u003cp\u003e9.17 Summary and Closing Comments 403\u003c\/p\u003e \u003cp\u003eProblems 403\u003c\/p\u003e \u003cp\u003eReferences 405\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 ESD Circuits: BiCMOS 408\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Bipolar ESD Input Circuits 408\u003c\/p\u003e \u003cp\u003e10.2 Diode-Configured Bipolar ESD Input Circuits 412\u003c\/p\u003e \u003cp\u003e10.3 Bipolar ESD Input Circuits: Voltage-Triggered Elements 413\u003c\/p\u003e \u003cp\u003e10.3.1 Voltage Triggered Bipolar ESD Input Circuits Classifications 413\u003c\/p\u003e \u003cp\u003e10.3.2 Bipolar ESD Input: Resistor Grounded-Base ESD Input 414\u003c\/p\u003e \u003cp\u003e10.3.3 Bipolar ESD Input Circuits: Zener Breakdown Voltage Triggered 418\u003c\/p\u003e \u003cp\u003e10.3.4 Bipolar ESD: BV CEO Voltage-Triggered ESD Input 423\u003c\/p\u003e \u003cp\u003e10.3.5 Bipolar ESD Input Circuits: Ultralow-Voltage Forward-Biased Voltage Trigger 430\u003c\/p\u003e \u003cp\u003e10.3.6 ESD Bipolar Input Circuits: Future Networks and Scaling 433\u003c\/p\u003e \u003cp\u003e10.3.7 Bipolar ESD Input Device Scaling 436\u003c\/p\u003e \u003cp\u003e10.4 BiCMOS Mixed Signal Designs 437\u003c\/p\u003e \u003cp\u003e10.5 Summary and Closing Comments 437\u003c\/p\u003e \u003cp\u003eProblems 437\u003c\/p\u003e \u003cp\u003eReferences 438\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 ESD Power Clamps 442\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 ESD Power Clamp Design Practices 442\u003c\/p\u003e \u003cp\u003e11.1.1 Classification of ESD Power Clamps 444\u003c\/p\u003e \u003cp\u003e11.1.2 Design Synthesis of ESD Power Clamp: Key Design Parameters 446\u003c\/p\u003e \u003cp\u003e11.2 Design Synthesis of ESD Power Clamps Trigger Networks 446\u003c\/p\u003e \u003cp\u003e11.2.1 Transient Response Frequency Trigger Element and the ESD Frequency Window 446\u003c\/p\u003e \u003cp\u003e11.2.2 The ESD Power Clamp Frequency Design Window 447\u003c\/p\u003e \u003cp\u003e11.2.3 Design Synthesis of ESD Power Clamp: Voltage-Triggered ESD Trigger Elements 447\u003c\/p\u003e \u003cp\u003e11.3 Design Synthesis of ESD Power Clamp: The ESD Power Clamp Shunting Element 449\u003c\/p\u003e \u003cp\u003e11.3.1 ESD Power Clamp Trigger Condition versus Shunt Failure 450\u003c\/p\u003e \u003cp\u003e11.3.2 ESD Clamp Element: Width Scaling 450\u003c\/p\u003e \u003cp\u003e11.3.3 ESD Clamp Element: On-Resistance 451\u003c\/p\u003e \u003cp\u003e11.3.4 ESD Clamp Element: Safe Operating Area 451\u003c\/p\u003e \u003cp\u003e11.4 ESD Power Clamp Issues 452\u003c\/p\u003e \u003cp\u003e11.4.1 ESD Power Clamp Issues: Power-Up and Power-Down 452\u003c\/p\u003e \u003cp\u003e11.4.2 ESD Power Clamp Issues: False Triggering 452\u003c\/p\u003e \u003cp\u003e11.4.3 ESD Power Clamp Issues: Precharging 452\u003c\/p\u003e \u003cp\u003e11.4.4 ESD Power Clamp Issues: Postcharging 453\u003c\/p\u003e \u003cp\u003e11.5 ESD Power Clamp Design 453\u003c\/p\u003e \u003cp\u003e11.5.1 Native Power Supply RC-Triggered MOSFET ESD Power Clamp 453\u003c\/p\u003e \u003cp\u003e11.5.2 Nonnative Power Supply RC-Triggered MOSFET ESD Power Clamp 454\u003c\/p\u003e \u003cp\u003e11.5.3 ESD Power Clamp Networks with Improved Inverter Stage Feedback 454\u003c\/p\u003e \u003cp\u003e11.5.4 ESD Power Clamp Design Synthesis: Forward-Bias-Triggered ESD Power Clamps 456\u003c\/p\u003e \u003cp\u003e11.5.5 ESD Power Clamp Design Synthesis: IEC 61000-4-2 Responsive ESD Power Clamps 457\u003c\/p\u003e \u003cp\u003e11.5.6 ESD Power Clamp Design Synthesis: Precharging and Postcharging Insensitive ESD Power Clamps 457\u003c\/p\u003e \u003cp\u003e11.6 Master\/Slave ESD Power Clamp Systems 458\u003c\/p\u003e \u003cp\u003e11.7 Series-Stacked RC-Triggered ESD Power Clamps 460\u003c\/p\u003e \u003cp\u003e11.8 ESD Power Clamps: Triple-Well Series Diodes as Core Clamps 460\u003c\/p\u003e \u003cp\u003e11.9 Summary and Closing Comments 464\u003c\/p\u003e \u003cp\u003eProblems 465\u003c\/p\u003e \u003cp\u003eReferences 466\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12 Bipolar ESD Power Clamps 468\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e12.1 Bipolar ESD Power Clamps 468\u003c\/p\u003e \u003cp\u003e12.2 Bipolar Voltage-Triggered ESD Power Clamps 468\u003c\/p\u003e \u003cp\u003e12.2.1 Bipolar ESD Power Clamp: Zener Breakdown Voltage Triggered 469\u003c\/p\u003e \u003cp\u003e12.2.2 Bipolar ESD Power Clamp: BV CEO Voltage-Triggered ESD Power Clamp 470\u003c\/p\u003e \u003cp\u003e12.3 ESD Power Clamp Design Synthesis: Bipolar ESD Power Clamps 473\u003c\/p\u003e \u003cp\u003e12.4 Mixed Voltage Interface Forward-Bias Voltage and BV CEO Breakdown Synthesized Bipolar ESD Power Clamps 476\u003c\/p\u003e \u003cp\u003e12.5 Ultralow-Voltage Forward-Biased Voltage-Trigger BiCMOS ESD Power Clamp 480\u003c\/p\u003e \u003cp\u003e12.6 Bipolar ESD Power Clamps with Frequency Trigger Elements: Capacitance Triggered 485\u003c\/p\u003e \u003cp\u003e12.7 Summary and Closing Comments 485\u003c\/p\u003e \u003cp\u003eProblems 486\u003c\/p\u003e \u003cp\u003eReferences 487\u003c\/p\u003e \u003cp\u003e\u003cb\u003e13 Silicon-Controlled Rectifier Power Clamps 489\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e13.1 ESD Silicon-Controlled Rectifier Circuits 489\u003c\/p\u003e \u003cp\u003e13.1.1 Unidirectional SCR 489\u003c\/p\u003e \u003cp\u003e13.1.2 Bidirectional SCR ESD Power Clamps 489\u003c\/p\u003e \u003cp\u003e13.1.3 Medium-Level SCR ESD Power Clamps 490\u003c\/p\u003e \u003cp\u003e13.1.4 Low Voltage Triggered SCR ESD Power Clamps 490\u003c\/p\u003e \u003cp\u003e13.2 Lateral Diffused MOS Circuits 492\u003c\/p\u003e \u003cp\u003e13.2.1 LOCOS-Defined LDMOS 492\u003c\/p\u003e \u003cp\u003e13.2.2 Shallow Trench Isolation-Defined LDMOS 493\u003c\/p\u003e \u003cp\u003e13.2.3 STI-Defined Isolated LDMOS 494\u003c\/p\u003e \u003cp\u003e13.3 DeMOS Circuits 496\u003c\/p\u003e \u003cp\u003e13.3.1 DeNMOS 497\u003c\/p\u003e \u003cp\u003e13.3.2 DeNMOS-SCR Transistor 497\u003c\/p\u003e \u003cp\u003e13.4 Ultrahigh-Voltage LDMOS (UHV-LDMOS) Circuits 497\u003c\/p\u003e \u003cp\u003e13.4.1 Uhv-ldmos 497\u003c\/p\u003e \u003cp\u003e13.4.2 Uhv-ldmos-scr 497\u003c\/p\u003e \u003cp\u003e13.5 Summary and Closing Comments 501\u003c\/p\u003e \u003cp\u003eProblems 501\u003c\/p\u003e \u003cp\u003eReferences 501\u003c\/p\u003e \u003cp\u003eGlossary of Terms 504\u003c\/p\u003e \u003cp\u003eStandards 509\u003c\/p\u003e \u003cp\u003eIndex 512\u003c\/p\u003e\n\u003c\/li\u003e\n\u003c\/ul\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default Title","offer_id":49406955487575,"sku":"9781118954461","price":84.5,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9781118954461.jpg?v=1730497682","url":"https:\/\/bookcurl.com\/products\/esd-9781118954461","provider":"Book Curl","version":"1.0","type":"link"}