{"product_id":"engineering-the-cmos-library-9781118243046","title":"Engineering the CMOS Library","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eShows readers how to gain the competitive edge in the integrated circuit marketplace\u003c\/p\u003e \u003cp\u003eThis book offers a wholly unique perspective on the digital design kit. It points to hidden value in the safety margins of standard-cell libraries and shows design engineers and managers how to use this knowledge to beat the competition.\u003c\/p\u003e \u003cp\u003e\u003ci\u003eEngineering the CMOS Library\u003c\/i\u003e reveals step by step how the generic, foundry-provided standard-cell library is built, and how to extract value from existing std-cells and EDA tools in order to produce tighter-margined, smaller, faster, less power-hungry, and more yield-producing integrated circuits. It explores all aspects of the digital design kit, including the different views of CMOS std-cell libraries along with coverage of IO libraries, memory compilers, and small analog blocks. Readers will learn:\u003c\/p\u003e \u003cul\u003e \u003cli\u003e \u003cp\u003eHow to work with overdesigned std-cell libraries to improve profitability while maintaining safety\u003c\/p\u003e \u003c\/li\u003e \u003cli\u003e \u003cp\u003eHow function\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003ePREFACE xi  \u003c\/p\u003e\n\u003cp\u003eACKNOWLEDGMENTS xiii\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 INTRODUCTION 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Adding Project-Specific Functions, Drive Strengths, Views, and Corners 4\u003c\/p\u003e \u003cp\u003e1.2 What Is a DDK? 5\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 STDCELL LIBRARIES 9\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Lesson from the Real World: Manager's Perspective and Engineer's Perspective 9\u003c\/p\u003e \u003cp\u003e2.2 What Is a Stdcell? 11\u003c\/p\u003e \u003cp\u003e2.3 Extended Library Offerings 32\u003c\/p\u003e \u003cp\u003e2.4 Boutique Library Offerings 36\u003c\/p\u003e \u003cp\u003e2.5 Concepts for Further Study 37\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 IO LIBRARIES 39\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 39\u003c\/p\u003e \u003cp\u003e3.2 Extension Capable Architectures versus Function Complete Architectures 40\u003c\/p\u003e \u003cp\u003e3.3 Electrostatic Discharge Considerations 43\u003c\/p\u003e \u003cp\u003e3.4 Concepts for Further Study 50\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 MEMORY COMPILERS 52\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 52\u003c\/p\u003e \u003cp\u003e4.2 Single Ports, Dual Ports, and ROM: The Compiler 55\u003c\/p\u003e \u003cp\u003e4.3 Nonvolatile Memories: The Block 58\u003c\/p\u003e \u003cp\u003e4.4 Special-Purpose Memories: The Custom 60\u003c\/p\u003e \u003cp\u003e4.5 Concepts for Further Study 62\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 OTHER FUNCTIONS 63\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 63\u003c\/p\u003e \u003cp\u003e5.2 Phase-Locked Loops, Power-On Resets, and Other Small-Scale Integration Analogs 66\u003c\/p\u003e \u003cp\u003e5.3 Low-Power Support Structures 69\u003c\/p\u003e \u003cp\u003e5.4 Stitching Structures 71\u003c\/p\u003e \u003cp\u003e5.5 Hard, Firm, and Soft Boxes 75\u003c\/p\u003e \u003cp\u003e5.6 Concepts for Further Study 78\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 PHYSICAL VIEWS 80\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 80\u003c\/p\u003e \u003cp\u003e6.2 Picking an Architecture 82\u003c\/p\u003e \u003cp\u003e6.3 Measuring Density 86\u003c\/p\u003e \u003cp\u003e6.4 The Need and the Way to Work with Fabrication Houses 89\u003c\/p\u003e \u003cp\u003e6.5 Concepts for Further Study 92\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 SPICE 95\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 95\u003c\/p\u003e \u003cp\u003e7.2 Why a Tool More Than 40 Years Old Is Still Useful 99\u003c\/p\u003e \u003cp\u003e7.3 Accuracy, Reality, and Why SPICE Results Must be Viewed with a Wary Eye 102\u003c\/p\u003e \u003cp\u003e7.4 Sufficient Parasitics 106\u003c\/p\u003e \u003cp\u003e7.5 Concepts for Further Study 107\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 TIMING VIEWS 109\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 109\u003c\/p\u003e \u003cp\u003e8.2 Performance Limits and Measurement 110\u003c\/p\u003e \u003cp\u003e8.3 Default Versus Conditional Arcs 110\u003c\/p\u003e \u003cp\u003e8.4 Break-Point Optimization 112\u003c\/p\u003e \u003cp\u003e8.5 A Word on Setup and Hold 115\u003c\/p\u003e \u003cp\u003e8.6 Failure Mechanisms and Roll-Off 122\u003c\/p\u003e \u003cp\u003e8.7 Supporting Efficient Synthesis 124\u003c\/p\u003e \u003cp\u003e8.8 Supporting Efficient Timing Closure 131\u003c\/p\u003e \u003cp\u003e8.9 Design Corner Specific Timing Views 134\u003c\/p\u003e \u003cp\u003e8.10 Nonlinear Timing Views are so \"Old Hat\" . . . 140\u003c\/p\u003e \u003cp\u003e8.11 Concepts for Further Study 142\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 POWER VIEWS 145\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 145\u003c\/p\u003e \u003cp\u003e9.2 Timing Arcs Versus Power Arcs 147\u003c\/p\u003e \u003cp\u003e9.3 Static Power 148\u003c\/p\u003e \u003cp\u003e9.4 Real Versus Measured Dynamic Power 150\u003c\/p\u003e \u003cp\u003e9.5 Should Power Be Built as a Monotonic Array? 153\u003c\/p\u003e \u003cp\u003e9.6 Best-Case and Worst-case Power Views Versus Best-Case and Worst-Case Timing Views 155\u003c\/p\u003e \u003cp\u003e9.7 Efficiently Measuring Power 156\u003c\/p\u003e \u003cp\u003e9.8 Concepts for Further Study 158\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 NOISE VIEWS 160\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 160\u003c\/p\u003e \u003cp\u003e10.2 Noise Arcs Versus Timing and Power Arcs 162\u003c\/p\u003e \u003cp\u003e10.3 The Easy Part 165\u003c\/p\u003e \u003cp\u003e10.4 The Not-So-Easy Part 166\u003c\/p\u003e \u003cp\u003e10.5 Concepts for Further Study 168\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 LOGICAL VIEWS 170\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 170\u003c\/p\u003e \u003cp\u003e11.2 Consistency Across Simulators 171\u003c\/p\u003e \u003cp\u003e11.2.1 Efficient Testing 175\u003c\/p\u003e \u003cp\u003e11.3 Consistency with Timing, Power \u0026amp; Noise Views 177\u003c\/p\u003e \u003cp\u003e11.4 Concepts for Further Study 180\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12 TEST VIEWS 181\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e12.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 181\u003c\/p\u003e \u003cp\u003e12.2 Supporting Reachability 184\u003c\/p\u003e \u003cp\u003e12.3 Supporting Observability 189\u003c\/p\u003e \u003cp\u003e12.4 Concepts for Further Study 191\u003c\/p\u003e \u003cp\u003e\u003cb\u003e13 CONSISTENCY 193\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e13.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 193\u003c\/p\u003e \u003cp\u003e13.2 Validating Views across a Library 195\u003c\/p\u003e \u003cp\u003e13.3 Validating Stdcells Across a Technology Node 199\u003c\/p\u003e \u003cp\u003e13.4 Validating Libraries Across Multiple Technology Nodes 204\u003c\/p\u003e \u003cp\u003e13.5 Concepts for Further Study 208\u003c\/p\u003e \u003cp\u003e\u003cb\u003e14 DESIGN FOR MANUFACTURABILITY 209\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e14.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 209\u003c\/p\u003e \u003cp\u003e14.2 What is DFM? 211\u003c\/p\u003e \u003cp\u003e14.3 Concepts for Further Study 224\u003c\/p\u003e \u003cp\u003e\u003cb\u003e15 VALIDATION 226\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e15.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 226\u003c\/p\u003e \u003cp\u003e15.2 Quality Levels 229\u003c\/p\u003e \u003cp\u003e15.3 Concepts for Further Study 236\u003c\/p\u003e \u003cp\u003e\u003cb\u003e16 PLAYING WITH THE PHYSICAL DESIGN KIT: USUALLY \"AT YOUR OWN RISK\" 237\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e16.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 237\u003c\/p\u003e \u003cp\u003e16.2 Manipulating Models 240\u003c\/p\u003e \u003cp\u003e16.3 Added Unsupported Devices 243\u003c\/p\u003e \u003cp\u003e16.4 Concepts for Further Study 245\u003c\/p\u003e \u003cp\u003e\u003cb\u003e17 TAGGING AND REVISIONING 247\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e17.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 247\u003c\/p\u003e \u003cp\u003e17.2 Tagging and Time Stamps 248\u003c\/p\u003e \u003cp\u003e17.3 Metadata, Directory Structures, and Pointers 254\u003c\/p\u003e \u003cp\u003e17.4 Concepts for Further Study 258\u003c\/p\u003e \u003cp\u003e\u003cb\u003e18 RELEASING AND SUPPORTING 260\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e18.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 260\u003c\/p\u003e \u003cp\u003e18.2 When Is Test Silicon Needed for Verification? 263\u003c\/p\u003e \u003cp\u003e18.3 Sending the Baby Out the Door 265\u003c\/p\u003e \u003cp\u003e18.4 Multiple Quality Levels on the Same Design 269\u003c\/p\u003e \u003cp\u003e18.5 Supporting \"Bug Fixes\" 271\u003c\/p\u003e \u003cp\u003e18.6 Concepts for Further Study 274\u003c\/p\u003e \u003cp\u003e\u003cb\u003e19 OTHER TOPICS 276\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e19.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 276\u003c\/p\u003e \u003cp\u003e19.2 Supporting High-Speed Design 279\u003c\/p\u003e \u003cp\u003e19.3 Supporting Low-Power Design 283\u003c\/p\u003e \u003cp\u003e19.4 Supporting Third-Party Libraries 286\u003c\/p\u003e \u003cp\u003e19.5 Supporting Black Box Third-Party IP (Intellectual Property) Design 289\u003c\/p\u003e \u003cp\u003e19.6 Supporting Multiple Library Design 292\u003c\/p\u003e \u003cp\u003e19.7 Concepts for Further Study 293\u003c\/p\u003e \u003cp\u003e\u003cb\u003e20 COMMUNICATIONS 295\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e20.1 Manager's Perspective 295\u003c\/p\u003e \u003cp\u003e20.2 Customer's Perspective 298\u003c\/p\u003e \u003cp\u003e20.3 Vendor's Perspective 300\u003c\/p\u003e \u003cp\u003e20.4 Engineer's Perspective 301\u003c\/p\u003e \u003cp\u003e20.5 Concepts for Further Study 302\u003c\/p\u003e \u003cp\u003e20.6 Conclusions 302\u003c\/p\u003e \u003cp\u003eAPPENDIX I MINIMUM LIBRARY SYNTHESIS VERSUS FULL-LIBRARY SYNTHESIS OF A FOUR-BIT FLASH ADDER 305\u003c\/p\u003e \u003cp\u003eAPPENDIX II PERTINENT CMOS BSIM SPICE PARAMETERS WITH UNITS AND DEFAULT LEVELS 311\u003c\/p\u003e \u003cp\u003eAPPENDIX III DEFINITION OF TERMS 313\u003c\/p\u003e \u003cp\u003eAPPENDIX IV ONE POSSIBLE MEANS OF FORMALIZED\u003c\/p\u003e \u003cp\u003eMONTHLY REPORTING 317\u003c\/p\u003e \u003cp\u003eINDEX 319\u003c\/p\u003e\n\u003c\/li\u003e\n\u003c\/ul\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default Title","offer_id":49406843224407,"sku":"9781118243046","price":95.36,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9781118243046.jpg?v=1730497311","url":"https:\/\/bookcurl.com\/products\/engineering-the-cmos-library-9781118243046","provider":"Book Curl","version":"1.0","type":"link"}