{"product_id":"digital-system-design-using-fsms-9781119782704","title":"Digital System Design using FSMs","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cb\u003eDIGITAL SYSTEM DESIGN USING FSMS\u003c\/b\u003e \u003cp\u003e\u003cb\u003eExplore this concise guide perfect for digital designers and students of electronic engineering who work in or study embedded systems\u003c\/b\u003e\u003c\/p\u003e\u003cp\u003e\u003ci\u003eDigital System Design using FSMs: A Practical Learning Approach\u003c\/i\u003e delivers a thorough update on the author's earlier work, FSM-Based Digital Design using Verilog HDL. The new book retains the foundational content from the first book while including refreshed content to cover the design of Finite State Machines delivered in a linear programmed learning format. The author describes a different form of State Machines based on ToggleFlip Flops and Data Flip Flops.\u003c\/p\u003e\u003cp\u003eThe book includes many figures of which 15 are Verilog HDL simulations that readers can use to test out the design methods described in the book, as well as 19 Logisim simulation files with figures. Additional circuits are also contained within the Wiley web folder. It has tutorials and exercises, including comprehensive coverage of real-wo\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp\u003ePreface viii\u003c\/p\u003e \u003cp\u003eAcknowledgements x\u003c\/p\u003e \u003cp\u003eAbout the Companion Website xi\u003c\/p\u003e \u003cp\u003eGuide to Supplementary Resources xii\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Introduction to Finite State Machines 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Some Notes on Style 1\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Using FSMs to Control External Devices 25\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Introduction 25\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 Introduction to FSM Synthesis 45\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Introduction 45\u003c\/p\u003e \u003cp\u003e3.2 Tutorials Covering Chapters 1, 2, and 3 71\u003c\/p\u003e \u003cp\u003e3.2.1 Binary data serial transmitter FSM 71\u003c\/p\u003e \u003cp\u003e3.2.2 The high low FSM system 76\u003c\/p\u003e \u003cp\u003e3.2.3 The clocked watchdog timer FSM 80\u003c\/p\u003e \u003cp\u003e3.2.3.1 FSM equations 81\u003c\/p\u003e \u003cp\u003e3.2.4 The asynchronous receiver system clocked FSM 84\u003c\/p\u003e \u003cp\u003e3.2.4.1 Brief note on the development of the test bench generator 86\u003c\/p\u003e \u003cp\u003e3.2.4.2 The state diagram 86\u003c\/p\u003e \u003cp\u003e3.2.4.3 The state diagram equations 87\u003c\/p\u003e \u003cp\u003e3.2.4.4 The outputs 87\u003c\/p\u003e \u003cp\u003e3.2.4.5 Verilog HDL simulation of the completed system 95\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Asynchronous FSM Methods 97\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Introduction to Asynchronous FSM 97\u003c\/p\u003e \u003cp\u003e4.2 Summary 144\u003c\/p\u003e \u003cp\u003e4.3 Tutorials 144\u003c\/p\u003e \u003cp\u003e4.3.1 FSM motor with fault detection 144\u003c\/p\u003e \u003cp\u003e4.3.2 The mower in four and two states 148\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 Clocked One Hot Method of FSM Design 153\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Introduction 153\u003c\/p\u003e \u003cp\u003e5.2 Tutorials on the Clocked One Hot FSM Method 168\u003c\/p\u003e \u003cp\u003e5.2.1 Seven-state system clocked one hot method 168\u003c\/p\u003e \u003cp\u003e5.2.2 Memory tester FSM 170\u003c\/p\u003e \u003cp\u003e5.2.3 Eight-bit sequence detector FSM 174\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Further Event-Driven FSM Design 179\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Introduction 179\u003c\/p\u003e \u003cp\u003e6.2 Conclusions 195\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Petri Net FSM Design 197\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Introduction 197\u003c\/p\u003e \u003cp\u003e7.2 Tutorials Using Petri Net FSM 234\u003c\/p\u003e \u003cp\u003e7.2.1 Controlled shared resource Petri nets 234\u003c\/p\u003e \u003cp\u003e7.2.2 Serial clock-driven Petri net FSM 240\u003c\/p\u003e \u003cp\u003e7.2.3 Using asynchronous (event-driven) design with Petri nets 247\u003c\/p\u003e \u003cp\u003e7.3 Conclusions 249\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix A1: Boolean Algebra 251\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA1.1 Basic Gate Symbols 251\u003c\/p\u003e \u003cp\u003eA1.2 The Exclusive OR and Exclusive NOR 252\u003c\/p\u003e \u003cp\u003eA1.3 Laws of Boolean Algebra 252\u003c\/p\u003e \u003cp\u003eA1.3.1 Basic OR rules 252\u003c\/p\u003e \u003cp\u003eA1.3.2 Basic AND rules 253\u003c\/p\u003e \u003cp\u003eA1.3.3 Associative and commutative laws 253\u003c\/p\u003e \u003cp\u003eA1.3.4 Distributive laws 253\u003c\/p\u003e \u003cp\u003eA1.3.5 Auxiliary rule for static 1 hazard removal 254\u003c\/p\u003e \u003cp\u003eA1.3.5.1 Proof of the Auxiliary Rule 254\u003c\/p\u003e \u003cp\u003eA1.3.6 Consensus theorem 254\u003c\/p\u003e \u003cp\u003eA1.3.7 The effect of signal delay in logic gates 255\u003c\/p\u003e \u003cp\u003eA1.3.8 De-Morgan’s theorem 256\u003c\/p\u003e \u003cp\u003eA1.4 Examples of Applying the Laws of Boolean Algebra 257\u003c\/p\u003e \u003cp\u003eA1.4.1 Converting AND–OR to NAND 257\u003c\/p\u003e \u003cp\u003eA1.4.2 Converting AND–OR to NOR 257\u003c\/p\u003e \u003cp\u003eA1.4.3 Logical adjacency rule 258\u003c\/p\u003e \u003cp\u003eA1.5 Summary 258\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix A2: Use of Verilog HDL and Logisim to FSM 261\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA2.1 The Single-Pulse Generator with Memory Clock-Driven FSM 261\u003c\/p\u003e \u003cp\u003eA2.2 Test Bench Module and its Purpose 267\u003c\/p\u003e \u003cp\u003eA2.3 Using Synapticad Software 268\u003c\/p\u003e \u003cp\u003eA2.4 More Direct Method 270\u003c\/p\u003e \u003cp\u003eA2.5 A Very Simple Guide to Using the Logisim Simulator 271\u003c\/p\u003e \u003cp\u003eA2.5.1 The Logisim top level menu items 271\u003c\/p\u003e \u003cp\u003eA2.6 Using Flip-Flops in a Circuit 273\u003c\/p\u003e \u003cp\u003eA2.7 Example Single-Pulse FSM 275\u003c\/p\u003e \u003cp\u003eA2.8 How to Use the Simulator to Simulate the Single-Pulse FSM 278\u003c\/p\u003e \u003cp\u003eA2.8.1 Using Logisim with the truth table approach 278\u003c\/p\u003e \u003cp\u003eA2.9 Using Logisim with the Truth Table Approach 279\u003c\/p\u003e \u003cp\u003eA2.9.1 Useful note 281\u003c\/p\u003e \u003cp\u003eA2.10 Summary 281\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix A3: Counters, Shift Registers, Input, and Output with an FSM 285\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA3.1 Basic Down Synchronous Binary Counter Development 285\u003c\/p\u003e \u003cp\u003eA3.2 Example of a Four-Bit Synchronous Up Counter with T Type Flip-Flops 288\u003c\/p\u003e \u003cp\u003eA3.3 Parallel Loading Counters – Using T Flip-Flops 291\u003c\/p\u003e \u003cp\u003eA3.4 Using D Flip-Flops To Build Parallel Loading Counters 292\u003c\/p\u003e \u003cp\u003eA3.5 Simple Binary Up Counter with Parallel Inputs 293\u003c\/p\u003e \u003cp\u003eA3.6 Clock Circuit to Drive the Counter (and FSM) 294\u003c\/p\u003e \u003cp\u003eA3.7 Counter Design Using Don’t Care States 295\u003c\/p\u003e \u003cp\u003eA3.8 Shift Registers 296\u003c\/p\u003e \u003cp\u003eA3.9 Dealing with Input and Output Signals Using FSM 298\u003c\/p\u003e \u003cp\u003eA3.10 Using Logisim to Work with Larger FSM Systems 301\u003c\/p\u003e \u003cp\u003eA3.10.1 The equations 302\u003c\/p\u003e \u003cp\u003eA3.11 Summary 305\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix A4: Finite State Machines Using Verilog Behavioural Mode 307\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA4.1 Introduction 307\u003c\/p\u003e \u003cp\u003eA4.2 The Single-Pulse\/Multiple-Pulse Generator with Memory FSM 307\u003c\/p\u003e \u003cp\u003eA4.3 The Memory Tester FSM Revisited 313\u003c\/p\u003e \u003cp\u003eA4.4 Summary 315\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix A5: Programming a Finite State Machine 317\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA5.1 Introduction 317\u003c\/p\u003e \u003cp\u003eA5.2 The Parallel Loading Counter 317\u003c\/p\u003e \u003cp\u003eA5.3 The Multiplexer 319\u003c\/p\u003e \u003cp\u003eA5.4 The Micro Instruction 320\u003c\/p\u003e \u003cp\u003eA5.5 The Memory 320\u003c\/p\u003e \u003cp\u003eA5.6 The Instruction Set 321\u003c\/p\u003e \u003cp\u003eA5.7 Simple Example: Single-Pulse FSM 323\u003c\/p\u003e \u003cp\u003eA5.8 The Final Example 325\u003c\/p\u003e \u003cp\u003eA5.9 The Program Code 328\u003c\/p\u003e \u003cp\u003eA5.10 Returning Unused States via Other Transition Paths 328\u003c\/p\u003e \u003cp\u003eA5.11 Summary 328\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix A6: The Rotational Detector Using Logisim Simulator with Sub-Circuits 329\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA6.1 Using the Two-State Diagram Arrangement 333\u003c\/p\u003e \u003cp\u003eBibliography 335\u003c\/p\u003e \u003cp\u003eIndex 337\u003c\/p\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default 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