{"product_id":"digital-design-global-edition-9781292231167","title":"Digital Design Global Edition","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003e\u003cstrong\u003eM. Morris Mano\u003c\/strong\u003e is an Emeritus Professor of Computer Engineering at the California State University, Los Angeles. His notable works include the Mano Machine, i.e. a theoretical computer that contains a central processing unit, random access memory, and an input-output bus. M. Morris Mano has authored numerous books in the area of digital circuits that are known for teaching the basic concepts of digital logic circuits in a clear, accessible manner. His books for the introductory digital design course,\u003cem\u003e Logic and Computer Design Fundamentals\u003c\/em\u003e and \u003cem\u003eDigital Design\u003c\/em\u003e, continue to be two of the most widely used texts around the world.\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eMichael Ciletti \u003c\/strong\u003eis an Emeritus Professor of Electrical and Computer Engineering at the University of Colorado, Colorado Springs. An early advocate of including HDL-based design methodology in the curriculum, he pioneered and developed the offering of several courses using Verilog, VHDL, FPGAs and standard\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp\u003ePreface   \u003c\/p\u003e \u003cp\u003e1  Digital Systems and Binary Numbers   \u003c\/p\u003e \u003cp\u003e1.1   Digital Systems  \u003c\/p\u003e \u003cp\u003e1.2   Binary Numbers  \u003c\/p\u003e \u003cp\u003e1.3   Number-Base Conversions \u003c\/p\u003e \u003cp\u003e1.4   Octal and Hexadecimal Numbers \u003c\/p\u003e \u003cp\u003e1.5   Complements of Numbers \u003c\/p\u003e \u003cp\u003e1.6   Signed Binary Numbers \u003c\/p\u003e \u003cp\u003e1.7   Binary Codes \u003c\/p\u003e \u003cp\u003e1.8   Binary Storage and Registers    \u003c\/p\u003e \u003cp\u003e1.9   Binary Logic \u003c\/p\u003e \u003cp\u003e \u003c\/p\u003e \u003cp\u003e2  Boolean Algebra and Logic Gates    \u003c\/p\u003e \u003cp\u003e2.1   Introduction \u003c\/p\u003e \u003cp\u003e2.2   Basic Definitions \u003c\/p\u003e \u003cp\u003e2.3   Axiomatic Definition of Boolean Algebra \u003c\/p\u003e \u003cp\u003e2.4   Basic Theorems and Properties of Boolean Algebra \u003c\/p\u003e \u003cp\u003e2.5   Boolean Functions \u003c\/p\u003e \u003cp\u003e2.6   Canonical and Standard Forms \u003c\/p\u003e \u003cp\u003e2.7   Other Logic Operations \u003c\/p\u003e \u003cp\u003e2.8   Digital Logic Gates \u003c\/p\u003e \u003cp\u003e2.9   Integrated Circuits  \u003c\/p\u003e \u003cp\u003e \u003c\/p\u003e \u003cp\u003e3  Gate-Level Minimization    \u003c\/p\u003e \u003cp\u003e3.1   Introduction \u003c\/p\u003e \u003cp\u003e3.2   The Map Method \u003c\/p\u003e \u003cp\u003e3.3   Four-Variable K-Map \u003c\/p\u003e \u003cp\u003e3.4   Product-of-Sums Simplification \u003c\/p\u003e \u003cp\u003e3.5   Don’t-Care Conditions \u003c\/p\u003e \u003cp\u003e3.6   NAND and NOR Implementation \u003c\/p\u003e \u003cp\u003e3.7   Other Two-Level Implementations \u003c\/p\u003e \u003cp\u003e3.8   Exclusive-OR Function \u003c\/p\u003e \u003cp\u003e3.9   Hardware Description Languages (HDLs) \u003c\/p\u003e \u003cp\u003e \u003c\/p\u003e \u003cp\u003e4  Combinational Logic    \u003c\/p\u003e \u003cp\u003e4.1   Introduction \u003c\/p\u003e \u003cp\u003e4.2   Combinational Circuits \u003c\/p\u003e \u003cp\u003e4.3   Analysis of Combinational Circuits \u003c\/p\u003e \u003cp\u003e4.4   Design Procedure \u003c\/p\u003e \u003cp\u003e4.5   Binary Adder—Subtractor \u003c\/p\u003e \u003cp\u003e4.6   Decimal Adder \u003c\/p\u003e \u003cp\u003e4.7   Binary Multiplier \u003c\/p\u003e \u003cp\u003e4.8   Magnitude Comparator \u003c\/p\u003e \u003cp\u003e4.9   Decoders \u003c\/p\u003e \u003cp\u003e4.10   Encoders \u003c\/p\u003e \u003cp\u003e4.11   Multiplexers \u003c\/p\u003e \u003cp\u003e4.12   HDL Models of Combinational Circuits    \u003c\/p\u003e \u003cp\u003e   \u003c\/p\u003e \u003cp\u003e5  Synchronous Sequential Logic    \u003c\/p\u003e \u003cp\u003e5.1   Introduction \u003c\/p\u003e \u003cp\u003e5.2   Sequential Circuits \u003c\/p\u003e \u003cp\u003e5.3   Storage Elements: Latches \u003c\/p\u003e \u003cp\u003e5.4   Storage Elements: Flip-Flops \u003c\/p\u003e \u003cp\u003e5.5   Analysis of Clocked Sequential Circuits \u003c\/p\u003e \u003cp\u003e5.6   Synthesizable HDL Models of Sequential Circuits \u003c\/p\u003e \u003cp\u003e5.7   State Reduction and Assignment \u003c\/p\u003e \u003cp\u003e5.8   Design Procedure \u003c\/p\u003e \u003cp\u003e \u003c\/p\u003e \u003cp\u003e6  Registers and Counters    \u003c\/p\u003e \u003cp\u003e6.1   Registers \u003c\/p\u003e \u003cp\u003e6.2   Shift Registers \u003c\/p\u003e \u003cp\u003e6.3   Ripple Counters \u003c\/p\u003e \u003cp\u003e6.4   Synchronous Counters \u003c\/p\u003e \u003cp\u003e6.5   Other Counters \u003c\/p\u003e \u003cp\u003e6.6   HDL Models of Registers and Counters  \u003c\/p\u003e \u003cp\u003e \u003c\/p\u003e \u003cp\u003e7  Memory and Programmable Logic    \u003c\/p\u003e \u003cp\u003e7.1   Introduction \u003c\/p\u003e \u003cp\u003e7.2   Random-Access Memory \u003c\/p\u003e \u003cp\u003e7.3   Memory Decoding \u003c\/p\u003e \u003cp\u003e7.4   Error Detection and Correction \u003c\/p\u003e \u003cp\u003e7.5   Read-Only Memory \u003c\/p\u003e \u003cp\u003e7.6   Programmable Logic Array \u003c\/p\u003e \u003cp\u003e7.7   Programmable Array Logic \u003c\/p\u003e \u003cp\u003e7.8   Sequential Programmable Devices \u003c\/p\u003e \u003cp\u003e \u003c\/p\u003e \u003cp\u003e8   Design at the Register Transfer Level    \u003c\/p\u003e \u003cp\u003e8.1   Introduction \u003c\/p\u003e \u003cp\u003e8.2   Register Transfer Level (RTL) Notation \u003c\/p\u003e \u003cp\u003e8.3   RTL descriptions VERILOG (Edge- and Level-Sensitive Behaviors) \u003c\/p\u003e \u003cp\u003e8.4   Algorithmic State Machines (ASMs) \u003c\/p\u003e \u003cp\u003e8.5   Design Example (ASMD Chart) \u003c\/p\u003e \u003cp\u003e8.6   HDL Description of Design Example \u003c\/p\u003e \u003cp\u003e8.7   Sequential Binary Multiplier \u003c\/p\u003e \u003cp\u003e8.8   Control Logic \u003c\/p\u003e \u003cp\u003e8.9   HDL Description of Binary Multiplier \u003c\/p\u003e \u003cp\u003e8.10   Design with Multiplexers \u003c\/p\u003e \u003cp\u003e8.11   Race-Free Design (Software Race Conditions) \u003c\/p\u003e \u003cp\u003e8.12   Latch-Free Design (Why Waste Silicon?) \u003c\/p\u003e \u003cp\u003e8.13   System Verilog–An Introduction \u003c\/p\u003e \u003cp\u003e \u003c\/p\u003e \u003cp\u003e9   Laboratory Experiments with Standard ICs and FPGAs    \u003c\/p\u003e \u003cp\u003e9.1   Introduction t\u003c\/p\u003e","brand":"Pearson Education","offers":[{"title":"Default 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