{"product_id":"cmos-9781119481515","title":"CMOS","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003ePreface xxxiii\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 1 Introduction to CMOS Design 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 The CMOS IC Design Process 1\u003c\/p\u003e \u003cp\u003e1.1.1 Fabrication 2\u003c\/p\u003e \u003cp\u003e1.2 CMOS Background 5\u003c\/p\u003e \u003cp\u003e1.3 An Introduction to SPICE 8\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 2 The Well 31\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Patterning 32\u003c\/p\u003e \u003cp\u003e2.1.1 Patterning the N-well 35\u003c\/p\u003e \u003cp\u003e2.2 Laying Out the N-well 35\u003c\/p\u003e \u003cp\u003e2.2.1 Design Rules for the N-well 36\u003c\/p\u003e \u003cp\u003e2.3 Resistance Calculation 36\u003c\/p\u003e \u003cp\u003e2.3.1 The N-well Resistor 38\u003c\/p\u003e \u003cp\u003e2.4 The N-well\/Substrate Diode 39\u003c\/p\u003e \u003cp\u003e2.4.1 A Brief Introduction to PN Junction Physics 39\u003c\/p\u003e \u003cp\u003e2.4.2 Depletion Layer Capacitance 42\u003c\/p\u003e \u003cp\u003e2.4.3 Storage or Diffusion Capacitance 45\u003c\/p\u003e \u003cp\u003e2.4.4 SPICE Modeling 46\u003c\/p\u003e \u003cp\u003e2.5 The RC Delay through the N-well 48\u003c\/p\u003e \u003cp\u003e2.6 Twin Well Processes 51\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 3 The Metal Layers 59\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 The Bonding Pad 59\u003c\/p\u003e \u003cp\u003e3.1.1 Laying Out the Pad I 60\u003c\/p\u003e \u003cp\u003e3.2 Design and Layout Using the Metal Layers 63\u003c\/p\u003e \u003cp\u003e3.2.1 Metal1 and Via1 63\u003c\/p\u003e \u003cp\u003e3.2.2 Parasitics Associated with the Metal Layers 63\u003c\/p\u003e \u003cp\u003e3.2.3 Current-Carrying Limitations 67\u003c\/p\u003e \u003cp\u003e3.2.4 Design Rules for the Metal Layers 68\u003c\/p\u003e \u003cp\u003e3.2.5 Contact Resistance 69\u003c\/p\u003e \u003cp\u003e3.3 Crosstalk and Ground Bounce 70\u003c\/p\u003e \u003cp\u003e3.3.1 Crosstalk 71\u003c\/p\u003e \u003cp\u003e3.3.2 Ground Bounce 72\u003c\/p\u003e \u003cp\u003e3.4 Layout Examples 74\u003c\/p\u003e \u003cp\u003e3.4.1 Laying Out the Pad II 74\u003c\/p\u003e \u003cp\u003e3.4.2 Laying Out Metal Test Structures 76\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 4 The Active and Poly Layers 83\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Layout Using the Active and Poly Layers 83\u003c\/p\u003e \u003cp\u003e4.1.1 Process Flow 90\u003c\/p\u003e \u003cp\u003e4.2 Connecting Wires to Poly and Active 93\u003c\/p\u003e \u003cp\u003e4.3 Electrostatic Discharge (ESD) Protection 99\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 5 Resistors, Capacitors, MOSFETs 107\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Resistors 107\u003c\/p\u003e \u003cp\u003e5.2 Capacitors 115\u003c\/p\u003e \u003cp\u003e5.3 MOSFETs 118\u003c\/p\u003e \u003cp\u003e5.4 Layout Examples 125\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 6 MOSFET Operation 135\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 MOSFET Capacitance Overview\/Review 136\u003c\/p\u003e \u003cp\u003e6.2 The Threshold Voltage 139\u003c\/p\u003e \u003cp\u003e6.3 IV Characteristics of MOSFETs 144\u003c\/p\u003e \u003cp\u003e6.3.1 MOSFET Operation in the Triode Region 144\u003c\/p\u003e \u003cp\u003e6.3.2 The Saturation Region 146\u003c\/p\u003e \u003cp\u003e6.4 SPICE Modeling of the MOSFET 149\u003c\/p\u003e \u003cp\u003e6.4.1 Some SPICE Simulation Examples 151\u003c\/p\u003e \u003cp\u003e6.4.2 The Subthreshold Current 152\u003c\/p\u003e \u003cp\u003e6.5 Short-Channel MOSFETs 154\u003c\/p\u003e \u003cp\u003e6.5.1 MOSFET Scaling 155\u003c\/p\u003e \u003cp\u003e6.5.2 Short-Channel Effects 156\u003c\/p\u003e \u003cp\u003e6.5.3 SPICE Models for Our Short-Channel CMOS Process 157\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 7 CMOS Fabrication by Jeff Jessing 165\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 CMOS Unit Processes 165\u003c\/p\u003e \u003cp\u003e7.1.1 Wafer Manufacture 165\u003c\/p\u003e \u003cp\u003e7.1.2 Thermal Oxidation 167\u003c\/p\u003e \u003cp\u003e7.1.3 Doping Processes 168\u003c\/p\u003e \u003cp\u003e7.1.4 Photolithography 170\u003c\/p\u003e \u003cp\u003e7.1.5 Thin Film Removal 173\u003c\/p\u003e \u003cp\u003e7.1.6 Thin Film Deposition 177\u003c\/p\u003e \u003cp\u003e7.2 CMOS Process Integration 180\u003c\/p\u003e \u003cp\u003e7.2.1 Frontend-of-the-Line Integration 182\u003c\/p\u003e \u003cp\u003e7.2.2 Backend-of-the-Line Integration 196\u003c\/p\u003e \u003cp\u003e7.3 Backend Processes 210\u003c\/p\u003e \u003cp\u003e7.4 Advanced CMOS Process Integration 212\u003c\/p\u003e \u003cp\u003e7.4.1 FinFETs 213\u003c\/p\u003e \u003cp\u003e7.4.2 Dual Damascene Low-k\/Cu Interconnects 216\u003c\/p\u003e \u003cp\u003e7.5 Summary 219\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 8 Electrical Noise: An Overview 221\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Signals 221\u003c\/p\u003e \u003cp\u003e8.1.1 Power and Energy 221\u003c\/p\u003e \u003cp\u003e8.1.2 Power Spectral Density 223\u003c\/p\u003e \u003cp\u003e8.2 Circuit Noise 226\u003c\/p\u003e \u003cp\u003e8.2.1 Calculating and Modeling Circuit Noise 227\u003c\/p\u003e \u003cp\u003e8.2.2 Thermal Noise 231\u003c\/p\u003e \u003cp\u003e8.2.3 Signal-to-Noise Ratio 237\u003c\/p\u003e \u003cp\u003e8.2.4 Shot Noise 247\u003c\/p\u003e \u003cp\u003e8.2.5 Flicker Noise 251\u003c\/p\u003e \u003cp\u003e8.2.6 Other Noise Sources 258\u003c\/p\u003e \u003cp\u003e8.3 Discussion 260\u003c\/p\u003e \u003cp\u003e8.3.1 Correlation 260\u003c\/p\u003e \u003cp\u003e8.3.2 Noise and Feedback 264\u003c\/p\u003e \u003cp\u003e8.3.3 Some Final Notes Concerning Notation 267\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 9 Models for Analog Design 277\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Long-Channel MOSFETs 277\u003c\/p\u003e \u003cp\u003e9.1.1 The Square-Law Equations 279\u003c\/p\u003e \u003cp\u003e9.1.2 Small Signal Models 286\u003c\/p\u003e \u003cp\u003e9.1.3 Temperature Effects 300\u003c\/p\u003e \u003cp\u003e9.2 Short-Channel MOSFETs 302\u003c\/p\u003e \u003cp\u003e9.2.1 General Design (A Starting Point) 303\u003c\/p\u003e \u003cp\u003e9.2.2 Specific Design (A Discussion) 306\u003c\/p\u003e \u003cp\u003e9.3 MOSFET Noise Modeling 308\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 10 Models for Digital Design 327\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 The Digital MOSFET Model 328\u003c\/p\u003e \u003cp\u003e10.1.2 Process Characteristic Time Constant 331\u003c\/p\u003e \u003cp\u003e10.1.3 Delay and Transition Times 333\u003c\/p\u003e \u003cp\u003e10.1.4 General Digital Design 326\u003c\/p\u003e \u003cp\u003e10.2 The MOSFET Pass Gate 326\u003c\/p\u003e \u003cp\u003e10.2.1 Delay through a Pass Gate 338\u003c\/p\u003e \u003cp\u003e10.2.2 Delay through Series-Connected PGs 340\u003c\/p\u003e \u003cp\u003e10.3 A Final Comment Concerning Measurements 341\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 11 The Inverter 347\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 DC Characteristics 347\u003c\/p\u003e \u003cp\u003e11.2 Switching Characteristics 352\u003c\/p\u003e \u003cp\u003e11.3 Layout of the Inverter 356\u003c\/p\u003e \u003cp\u003e11.4 Sizing for Large Capacitive Loads 358\u003c\/p\u003e \u003cp\u003e11.5 Other Inverter Configurations 364\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 12 Static Logic Gates 369\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e12.1 DC Characteristics of the NAND and NOR Gates 369\u003c\/p\u003e \u003cp\u003e12.1.1 DC Characteristics of the NAND Gate 369\u003c\/p\u003e \u003cp\u003e12.1.2 DC Characteristics of the NOR Gate 372\u003c\/p\u003e \u003cp\u003e12.2 Layout of the NAND and NOR Gates 373\u003c\/p\u003e \u003cp\u003e12.3 Switching Characteristics 374\u003c\/p\u003e \u003cp\u003e12.3.1 NAND Gate 375\u003c\/p\u003e \u003cp\u003e12.3.2 Number of Inputs 378\u003c\/p\u003e \u003cp\u003e12.4 Complex CMOS Logic Gates 379\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 13 Clocked Circuits 389\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e13.1 The CMOS TG 389\u003c\/p\u003e \u003cp\u003e13.2 Applications of the Transmission Gate 391\u003c\/p\u003e \u003cp\u003e13.3 Latches and Flip-Flops 395\u003c\/p\u003e \u003cp\u003e13.4 Examples 402\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 14 Dynamic Logic Gates 411\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e14.1 Fundamentals of Dynamic Logic 411\u003c\/p\u003e \u003cp\u003e14.1.1 Charge Leakage 411\u003c\/p\u003e \u003cp\u003e14.1.2 Simulating Dynamic Circuits 414\u003c\/p\u003e \u003cp\u003e14.1.3 Nonoverlapping Clock Generation 415\u003c\/p\u003e \u003cp\u003e14.1.4 CMOS TG in Dynamic Circuits 416\u003c\/p\u003e \u003cp\u003e14.2 Clocked CMOS Logic 417\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 15 CMOS Layout Examples 425\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e15.1 Chip Layout 426\u003c\/p\u003e \u003cp\u003e15.2 Layout Steps by Dean Moriarty 434\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 16 Memory Circuits 445\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e16.1 Array Architectures 446\u003c\/p\u003e \u003cp\u003e16.1.1 Sensing Basics 446\u003c\/p\u003e \u003cp\u003e16.1.2 The Folded Array 452\u003c\/p\u003e \u003cp\u003e16.1.3 Chip Organization 458\u003c\/p\u003e \u003cp\u003e16.2 Peripheral Circuits 458\u003c\/p\u003e \u003cp\u003e16.2.1 Sense Amplifier Design 458\u003c\/p\u003e \u003cp\u003e16.2.2 Row\/Column Decoders 467\u003c\/p\u003e \u003cp\u003e16.2.3 Row Drivers 470\u003c\/p\u003e \u003cp\u003e16.3 Memory Cells 471\u003c\/p\u003e \u003cp\u003e16.3.1 The SRAM Cell 473\u003c\/p\u003e \u003cp\u003e16.3.2 Read-Only Memory (ROM) 473\u003c\/p\u003e \u003cp\u003e16.3.3 Floating Gate Memory 473\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 17 Sensing Using Modulation 493\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e17.1 Qualitative Discussion 494\u003c\/p\u003e \u003cp\u003e17.1.1 Examples of DSM 494\u003c\/p\u003e \u003cp\u003e17.1.2 Using DSM for Sensing in Flash Memory 496\u003c\/p\u003e \u003cp\u003e17.2 Sensing Resistive Memory 506\u003c\/p\u003e \u003cp\u003e17.3 Sensing in CMOS Imagers 513\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 18 Special Purpose CMOS Circuits 533\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e18.1 The Schmitt Trigger 533\u003c\/p\u003e \u003cp\u003e18.1.1 Design of the Schmitt Trigger 534\u003c\/p\u003e \u003cp\u003e18.1.2 Applications of the Schmitt Trigger 536\u003c\/p\u003e \u003cp\u003e18.2 Multivibrator Circuits 538\u003c\/p\u003e \u003cp\u003e18.2.1 The Monostable Multivibrator 539\u003c\/p\u003e \u003cp\u003e18.2.2 The Astable Multivibrator 540\u003c\/p\u003e \u003cp\u003e18.3 Input Buffers 541\u003c\/p\u003e \u003cp\u003e18.3.1 Basic Circuits 541\u003c\/p\u003e \u003cp\u003e18.3.2 Differential Circuits 543\u003c\/p\u003e \u003cp\u003e18.3.3 DC Reference 547\u003c\/p\u003e \u003cp\u003e18.3.4 Reducing Buffer Input Resistance 550\u003c\/p\u003e \u003cp\u003e18.4 Charge Pumps (Voltage Generators) 551\u003c\/p\u003e \u003cp\u003e18.4.1 Increasing the Output Voltage 553\u003c\/p\u003e \u003cp\u003e18.4.2 Generating Higher Voltages: The Dickson Charge Pump 553\u003c\/p\u003e \u003cp\u003e18.4.3 Example 556\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 19 Digital Phase-Locked Loops 561\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e19.1 The Phase Detector 563\u003c\/p\u003e \u003cp\u003e19.1.1 The XOR Phase Detector 563\u003c\/p\u003e \u003cp\u003e19.1.2 The Phase Frequency Detector 567\u003c\/p\u003e \u003cp\u003e19.2 The Voltage-Controlled Oscillator 570\u003c\/p\u003e \u003cp\u003e19.2.1 The Current-Starved VCO 570\u003c\/p\u003e \u003cp\u003e19.2.2 Source-Coupled VCOs 574\u003c\/p\u003e \u003cp\u003e19.3 The Loop Filter 576\u003c\/p\u003e \u003cp\u003e19.3.1 XOR DPLL 577\u003c\/p\u003e \u003cp\u003e19.3.2 PFD DPLL 583\u003c\/p\u003e \u003cp\u003e19.4 System Concerns 590\u003c\/p\u003e \u003cp\u003e19.4.1 Clock Recovery from NRZ Data 593\u003c\/p\u003e \u003cp\u003e19.5 Delay-Locked Loops 600\u003c\/p\u003e \u003cp\u003e19.6 Some Examples 603\u003c\/p\u003e \u003cp\u003e19.6.1 A 2 GHz DLL 603\u003c\/p\u003e \u003cp\u003e19.6.2 A 1 Gbit\/s Clock-Recovery Circuit 609\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 20 Current Mirrors 621\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e20.1 The Basic Current Mirror 621\u003c\/p\u003e \u003cp\u003e20.1.1 Long-Channel Design 622\u003c\/p\u003e \u003cp\u003e20.1.2 Matching Currents in the Mirror 624\u003c\/p\u003e \u003cp\u003e20.1.3 Biasing the Current Mirror 628\u003c\/p\u003e \u003cp\u003e20.1.4 Short-Channel Design 634\u003c\/p\u003e \u003cp\u003e20.1.5 Temperature Behavior 638\u003c\/p\u003e \u003cp\u003e20.1.6 Biasing in the Subthreshold Region 642\u003c\/p\u003e \u003cp\u003e20.2 Cascoding the Current Mirror 643\u003c\/p\u003e \u003cp\u003e20.2.1 The Simple Cascode 643\u003c\/p\u003e \u003cp\u003e20.2.2 Low-Voltage (Wide-Swing) Cascode 645\u003c\/p\u003e \u003cp\u003e20.2.3 Wide-Swing, Short-Channel Design 648\u003c\/p\u003e \u003cp\u003e20.2.4 Regulated Drain Current Mirror 651\u003c\/p\u003e \u003cp\u003e20.3 Biasing Circuits 653\u003c\/p\u003e \u003cp\u003e20.3.1 Long-Channel Biasing Circuits 653\u003c\/p\u003e \u003cp\u003e20.3.2 Short-Channel Biasing Circuits 656\u003c\/p\u003e \u003cp\u003e20.3.3 A Final Comment 657\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 21 Amplifiers 671\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e21.1 Gate-Drain Connected Loads 671\u003c\/p\u003e \u003cp\u003e21.1.1 Common-Source (CS) Amplifiers 671\u003c\/p\u003e \u003cp\u003e21.1.2 The Source Follower (Common-Drain Amplifier) 683\u003c\/p\u003e \u003cp\u003e21.1.3 Common Gate Amplifier 684\u003c\/p\u003e \u003cp\u003e21.2 Current Source Loads 685\u003c\/p\u003e \u003cp\u003e21.2.1 Common-Source Amplifier 685\u003c\/p\u003e \u003cp\u003e21.2.2 The Cascode Amplifier 698\u003c\/p\u003e \u003cp\u003e21.2.3 The Common-Gate Amplifier 702\u003c\/p\u003e \u003cp\u003e21.2.4 The Source Follower (Common-Drain Amplifier) 702\u003c\/p\u003e \u003cp\u003e21.3 The Push-Pull Amplifier 710\u003c\/p\u003e \u003cp\u003e21.3.1 DC Operation and Biasing 711\u003c\/p\u003e \u003cp\u003e21.3.2 Small-Signal Analysis 714\u003c\/p\u003e \u003cp\u003e21.3.3 Distortion 716\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 22 Differential Amplifiers 735\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e22.1 The Source-Coupled Pair 735\u003c\/p\u003e \u003cp\u003e22.1.1 DC Operation 735\u003c\/p\u003e \u003cp\u003e22.1.2 AC Operation 741\u003c\/p\u003e \u003cp\u003e22.1.3 Common-Mode Rejection Ratio 745\u003c\/p\u003e \u003cp\u003e22.1.4 Matching Considerations 746\u003c\/p\u003e \u003cp\u003e22.1.5 Noise Performance 749\u003c\/p\u003e \u003cp\u003e22.1.6 Slew-Rate Limitations 750\u003c\/p\u003e \u003cp\u003e22.2 The Source Cross-Coupled Pair 750\u003c\/p\u003e \u003cp\u003e22.2.1 Current Source Load 754\u003c\/p\u003e \u003cp\u003e22.3 Cascode Loads (The Telescopic Diff-Amp) 756\u003c\/p\u003e \u003cp\u003e22.4 Wide-Swing Differential Amplifiers 758\u003c\/p\u003e \u003cp\u003e22.4.1 Current Differential Amplifier 760\u003c\/p\u003e \u003cp\u003e22.4.2 Constant Transconductance Diff-Amp 760\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 23 Voltage References 773\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e23.1 MOSFET-Resistor Voltage References 774\u003c\/p\u003e \u003cp\u003e23.1.1 The Resistor-MOSFET Divider 774\u003c\/p\u003e \u003cp\u003e23.1.2 The MOSFET-Only Voltage Divider 777\u003c\/p\u003e \u003cp\u003e23.1.3 Self-Biased Voltage References 778\u003c\/p\u003e \u003cp\u003e23.2 Parasitic Diode-Based References 784\u003c\/p\u003e \u003cp\u003e23.2.1 Long-Channel BGR Design 787\u003c\/p\u003e \u003cp\u003e23.2.2 Short-Channel BGR Design 795\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 24 Operational Amplifiers I 803\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e24.1 The Two-Stage Op-Amp 804\u003c\/p\u003e \u003cp\u003e24.2 An Op-Amp with Output Buffer 822\u003c\/p\u003e \u003cp\u003e24.3 The Operational Transconductance Amplifier (OTA) 824\u003c\/p\u003e \u003cp\u003e24.4 Gain-Enhancement 835\u003c\/p\u003e \u003cp\u003e24.5 Some Examples and Discussions 839\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 25 Dynamic Analog Circuits 857\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e25.1 The MOSFET Switch 857\u003c\/p\u003e \u003cp\u003e25.1.1 Sample-and-Hold Circuits 861\u003c\/p\u003e \u003cp\u003e25.2 Fully-Differential Circuits 864\u003c\/p\u003e \u003cp\u003e25.2.1 A Fully-Differential Sample-and-Hold 866\u003c\/p\u003e \u003cp\u003e25.3 Switched-Capacitor Circuits 869\u003c\/p\u003e \u003cp\u003e25.3.1 Switched-Capacitor Integrator 871\u003c\/p\u003e \u003cp\u003e25.4 Circuits 879\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 26 Operational Amplifiers II 889\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e26.1 Biasing for Power and Speed 889\u003c\/p\u003e \u003cp\u003e26.1.1 Device Characteristics 890\u003c\/p\u003e \u003cp\u003e26.1.2 Biasing Circuit 891\u003c\/p\u003e \u003cp\u003e26.2 Basic Concepts 892\u003c\/p\u003e \u003cp\u003e26.3 Basic Op-Amp Design 900\u003c\/p\u003e \u003cp\u003e26.4 Op-Amp Design Using Switched-Capacitor CMFB 920\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 27 Nonlinear Analog Circuits 933\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e27.1 Basic CMOS Comparator Design 933\u003c\/p\u003e \u003cp\u003e27.1.1 Characterizing the Comparator 939\u003c\/p\u003e \u003cp\u003e27.1.2 Clocked Comparators 942\u003c\/p\u003e \u003cp\u003e27.1.3 Input Buffers Revisited 943\u003c\/p\u003e \u003cp\u003e27.2 Adaptive Biasing 943\u003c\/p\u003e \u003cp\u003e27.3 Analog Multipliers 946\u003c\/p\u003e \u003cp\u003e27.3.1 The Multiplying Quad 947\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 28 Data Converter Fundamentals by Harry Li 955\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e28.1 Analog Versus Discrete Time Signals 955\u003c\/p\u003e \u003cp\u003e28.2 Converting Analog Signals to Digital Signals 956\u003c\/p\u003e \u003cp\u003e28.3 Sample-and-Hold (S\/H) Characteristics 959\u003c\/p\u003e \u003cp\u003e28.4 Digital-to-Analog Converter (DAC) Specifications 961\u003c\/p\u003e \u003cp\u003e28.5 Analog-to-Digital Converter (ADC) Specifications 970\u003c\/p\u003e \u003cp\u003e28.6 Mixed-Signal Layout Issues 979\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 29 Data Converter Architectures by Harry Li 987\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e29.1 DAC Architectures 987\u003c\/p\u003e \u003cp\u003e29.1.1 Digital Input Code 987\u003c\/p\u003e \u003cp\u003e29.1.2 Resistor String 987\u003c\/p\u003e \u003cp\u003e29.1.3 R-2R Ladder Networks 992\u003c\/p\u003e \u003cp\u003e29.1.4 Current Steering 995\u003c\/p\u003e \u003cp\u003e29.1.5 Charge-Scaling DACs 999\u003c\/p\u003e \u003cp\u003e29.1.6 Cyclic DAC 1003\u003c\/p\u003e \u003cp\u003e29.1.7 Pipeline DAC 1005\u003c\/p\u003e \u003cp\u003e29.2 ADC Architectures 1006\u003c\/p\u003e \u003cp\u003e29.2.1 Flash 1006\u003c\/p\u003e \u003cp\u003e29.2.2 The Two-Step Flash ADC 1010\u003c\/p\u003e \u003cp\u003e29.2.3 The Pipeline ADC 1014\u003c\/p\u003e \u003cp\u003e29.2.4 Integrating ADCs 1018\u003c\/p\u003e \u003cp\u003e29.2.5 The Successive Approximation ADC 1022\u003c\/p\u003e \u003cp\u003e29.2.6 The Oversampling ADC 1027\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 30 Implementing Data Converters 1043\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e30.1 R-2R Topologies for DACs 1043\u003c\/p\u003e \u003cp\u003e30.1.1 The Current-Mode R-2R DAC 1044\u003c\/p\u003e \u003cp\u003e30.1.2 The Voltage-Mode R-2R DAC 1045\u003c\/p\u003e \u003cp\u003e30.1.3 A Wide-Swing Current-Mode R-2R DAC 1047\u003c\/p\u003e \u003cp\u003e30.1.4 Topologies Without an Op-Amp 1057\u003c\/p\u003e \u003cp\u003e30.2 Op-Amps in Data Converters 1063\u003c\/p\u003e \u003cp\u003e30.2.1 Op-Amp Gain 1066\u003c\/p\u003e \u003cp\u003e30.2.2 Op-Amp Unity Gain Frequency 1067\u003c\/p\u003e \u003cp\u003e30.2.3 Op-Amp Offset 1067\u003c\/p\u003e \u003cp\u003e30.3 Implementing ADCs 1070\u003c\/p\u003e \u003cp\u003e30.3.1 Implementing the S\/H 1071\u003c\/p\u003e \u003cp\u003e30.3.2 The Cyclic ADC 1077\u003c\/p\u003e \u003cp\u003e30.3.3 The Pipeline ADC 1084\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 31 Feedback Amplifiers with Harry Li 1115\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e31.1 The Feedback Equation 1115\u003c\/p\u003e \u003cp\u003e31.2 Properties of Negative Feedback on Amplifier Design 1117\u003c\/p\u003e \u003cp\u003e31.2.1 Gain Desensitivity 1117\u003c\/p\u003e \u003cp\u003e31.3 Recognizing Feedback Topologies 1120\u003c\/p\u003e \u003cp\u003e31.3.1 Input Mixing 1121\u003c\/p\u003e \u003cp\u003e31.3.2 Output Sampling 1121\u003c\/p\u003e \u003cp\u003e31.3.3 The Feedback Network 1122\u003c\/p\u003e \u003cp\u003e31.3.4 Calculating Open-Loop Parameters 1125\u003c\/p\u003e \u003cp\u003e31.3.5 Calculating Closed-Loop Parameters 1127\u003c\/p\u003e \u003cp\u003e31.4 The Voltage Amp (Series-Shunt Feedback) 1128\u003c\/p\u003e \u003cp\u003e31.5 The Transimpedance Amp (Shunt-Shunt Feedback) 1134\u003c\/p\u003e \u003cp\u003e31.5.1 Simple Feedback Using a Gate-Drain Resistor 1140\u003c\/p\u003e \u003cp\u003e31.6 The Transconductance Amp (Series-Series Feedback) 1142\u003c\/p\u003e \u003cp\u003e31.7 The Current Amplifier (Shunt-Series Feedback) 1146\u003c\/p\u003e \u003cp\u003e31.8 Stability 1148\u003c\/p\u003e \u003cp\u003e31.8.1 The Return Ratio 1151\u003c\/p\u003e \u003cp\u003e31.9 Design Examples 1154\u003c\/p\u003e \u003cp\u003e31.9.1 Voltage Amplifiers 1154\u003c\/p\u003e \u003cp\u003e31.9.2 A Transimpedance Amplifier 1158\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 32 Hysteretic Power Converters 1175\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e32.1 A Review of Power and Energy Basics 1176\u003c\/p\u003e \u003cp\u003e32.1.1 Energy Storage in Inductors and Capacitors 1177\u003c\/p\u003e \u003cp\u003e32.1.2 Energy Use in Transmitting Data 1180\u003c\/p\u003e \u003cp\u003e32.1.3 Selection and use of Switches 1181\u003c\/p\u003e \u003cp\u003e32.2 Switching Power Supplies: Some Examples 1189\u003c\/p\u003e \u003cp\u003e32.2.1 The Buck SPS 1189\u003c\/p\u003e \u003cp\u003e32.2.2 The Boost SPS 1196\u003c\/p\u003e \u003cp\u003e32.2.3 The Flyback SPS 1200\u003c\/p\u003e \u003cp\u003e32.2.4 Pulse Width Modulation: A Control Loop Example 1204\u003c\/p\u003e \u003cp\u003e32.3 Hysteretic Control 1210\u003c\/p\u003e \u003cp\u003e32.3.1 Topologies 1211\u003c\/p\u003e \u003cp\u003e32.3.2 Examples 1212\u003c\/p\u003e \u003cp\u003eIndex 1219\u003c\/p\u003e \u003cp\u003eAbout the Author 1235\u003c\/p\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default 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