{"product_id":"a-practical-guide-to-veriloga-9781484263501","title":"A Practical Guide to VerilogA","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cdiv\u003e\n\u003cdiv\u003eDiscover how Verilog-A is particularly designed to describe behavior and connectivity of circuits and system components for analog SPICE-class simulators, or for continuous time (SPICE-based) kernels in Verilog-AMS simulators. With continuous updates since it''s release 30 years ago, this practical guide provides a comprehensive foundation and understanding to the  modeling language in its most recent standard formulation. \u003c\/div\u003e\n\u003cdiv\u003e\u003cbr\u003e\u003c\/div\u003e\n\u003cdiv\u003eWith the introduction of language extensions to support compact device modeling, the Verilog-A has become today de facto standard language in the electronics industry for coding compact models of active and passive semiconductor devices. You''ll gain an in depth look at how analog circuit simulators work, solving system equations, modeling of components from other physical domains, and modeling the same physical circuits and systems at various levels of detail and at different levels of abstraction.\u003cbr\u003e\n\u003c\/div\u003e\n\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003eChapter 1: IntroductionChapter Goal: Verilog-A delineation. Comparison to other HDLs and modeling languages. Book organization.\u003cbr\u003eChapter 2: The Lexical Basis of Verilog-AChapter Goal: Introducing Verilog-A lexical tokens, token separators as well as basic token groups and token containers.\u003cbr\u003eChapter 3: Basic Types and ExpressionsChapter Goal: Introducing integer, real and string data types and how expressions are assembled for different types using operators.\u003cbr\u003eChapter 4: Nets and SignalsChapter Goal: Introducing the concept of nets and signals defined by nature and net_discipline types.\u003cbr\u003eChapter 5: Modules and NetlistsChapter Goal: Introducing modules, as basic units of hierarchy in Verilog-A language, and their instantiation in SPICE and Verilog-A netlists.\u003cbr\u003eChapter 6: Parameters and ParamsetsChapter Goal: Introducing the concept of parameters, customization of modules by passing parameters into a module at instantiation and the concept of instance and model parameters defined via paramsets.\u003cbr\u003eChapter 7: Branch Contribution StatementsChapter Goal: Introducing the concept of analog branch assignments and signal access mechanisms.\u003cbr\u003eChapter 8: Procedural StatementsChapter Goal: Introducing analog procedural block and procedural control statements.\u003cbr\u003eChapter 9: Derivative and Integral OperatorsChapter Goal: Detailed description of analog functions used to perform differentiation and integration in time.\u003cbr\u003eChapter 10: Built-in Mathematical FunctionsChapter Goal: Define all Verilog-A standard mathematical function.\u003cbr\u003eChapter 11: User Defined FunctionsChapter Goal: Describe how to write modular, maintainable and reusable models in Verilog-A using user defined functions.\u003cbr\u003eChapter 12: Analog Filter FunctionsChapter Goal: Introducing Verilog-A time and frequency domain filter functions and their usage with constant and dynamic arguments.\u003cbr\u003eChapter 13: Look-Up Table ModelsChapter Goal: Describing how to create a multidimensional interpolation lookup-up table models in Verilog-A\u003cbr\u003eChapter 14: Small Signal and Noise SourcesChapter Goal: Introducing Verilog-A functions supporting small signal and noise analysis in SPICE simulators.\u003cbr\u003eChapter 15: EventsChapter Goal: Introducing methods to control analog behaviour of the component models in Verilog-A.\u003cbr\u003eChapter 16: Input and OutputChapter Goal: Describe methods and functions to read and write formatted data.\u003cbr\u003eChapter 17: Simulator Query and Control MethodsChapter Goal: Describing the methods to access the simulator kernel parameters in the Verilog-A model.\u003cbr\u003eChapter 18: AttributesChapter Goal: Introducing attributes as a mechanism for specifying properties about objects, statements and groups of statements in the Verilog-A source that can be used by the simulator.\u003cbr\u003eChapter 19: Compiler DirectivesChapter Goal: Introducing compiler directives that dictate Verilog-A compiler behaviour in a pre-processingcompilation phase.\u003cbr\u003eChapter 20: SPICE CompatibilityChapter Goal: Describes the degree of compatibility with SPICE-like simulators which Verilog-A provides and the approach taken to provide that compatibility.\u003c\/div\u003e","brand":"APress","offers":[{"title":"Default Title","offer_id":53187695313239,"sku":"9781484263501","price":46.74,"currency_code":"GBP","in_stock":true}],"url":"https:\/\/bookcurl.com\/products\/a-practical-guide-to-veriloga-9781484263501","provider":"Book Curl","version":"1.0","type":"link"}