{"title":"Embedded systems Books","description":"","products":[{"product_id":"security-of-biochip-cyberphysical-systems-9783030932763","title":"Security of Biochip Cyberphysical Systems","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eThis book provides readers with a valuable guide to understanding security and the interplay of computer science, microfluidics, and biochemistry in a biochip cyberphysical system (CPS).  The authors uncover new, potential threat and trust-issues to address, as this emerging technology is poised to be adapted at a large scale. Readers will learn how to secure biochip CPS by leveraging the available resources in different application contexts, as well as how to ensure intellectual property (IP) is protected against theft and counterfeits. This book enables secure biochip CPS design by helping bridge the knowledge gap at the intersection of the multi-disciplinary technology that drives biochip CPS.\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eIntroduction.- Threat landscape.- Architecture for Security.- Tools for Security.- Watermarking of Bio-IP.- Obfuscation of Bio-IP.- Conclusion.\u003c\/p\u003e","brand":"Springer Nature Switzerland AG","offers":[{"title":"Default Title","offer_id":48743059358039,"sku":"9783030932763","price":49.49,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9783030932763.jpg?v=1720063933"},{"product_id":"flexible-bioelectronics-with-power-autonomous-sensing-and-data-analytics-9783030985400","title":"Flexible Bioelectronics with Power Autonomous","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eThis book provides readers with an introduction to the materials and devices necessary for flexible sensors and electronics, followed by common techniques for fabrication of such devices and system-level integration. Key insights into fabrication and processing will guide readers through the tradeoff choices in designing such platforms. A comprehensive review of two specific, flexible bioelectronic platforms, related to smart bandages for wound monitoring and thread-based diagnostics for wearable health, will demonstrate practical application at the system level.  The book also provides a unique electrical engineering perspective by reviewing circuit architectures for low noise signal conditioning of weak signals from sensors,, and for low power analog to digital converters for signal acquisition. To achieve energy autonomy, authors provide several example of CMOS energy harvesting front end circuits and voltage boosters. Beyond circuit architectures, the book also provides a review of the modern theory of sampling and recovery of sparse signals, also known as compressed sensing. They then highlight how these principles can be leveraged for design and implementation of efficient signal acquisition hardware and reliable processing of acquired data for flexible electronic platforms.\u003cbr\u003e\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eChapter 1. Materials and Processing for Flexible Bioelectronics.- Chapter 2. Sensors and Platforms for Flexible Bioelectronics.- Chapter 3. Low-noise CMOS Signal Conditioning Circuits.- Chapter 4. Data Converters for Wearable Sensor Applications.- Chapter 5. Power Management Circuits for Energy Harvesting.- Chapter 6. Sampling and recovery of signals with spectral sparsity.- Chapter 7. Compressed Sensing.\u003cbr\u003e\u003c\/p\u003e","brand":"Springer Nature Switzerland AG","offers":[{"title":"Default Title","offer_id":48743061619031,"sku":"9783030985400","price":54.99,"currency_code":"GBP","in_stock":true}]},{"product_id":"soc-physical-design-a-comprehensive-guide-9783030981143","title":"SoC Physical Design: A Comprehensive Guide","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003ci\u003eSoC Physical Design \u003c\/i\u003eis a comprehensive practical guide for VLSI designers that thoroughly examines and explains the practical physical design flow of system on chip (SoC). The book covers the rationale behind making design decisions on power, performance, and area (PPA) goals for SoC and explains the required design environment algorithms, design flows, constraints, handoff procedures, and design infrastructure requirements in achieving them. The book reveals challenges likely to be faced at each design process and ways to address them in practical design environments. Advanced topics on 3D ICs, EDA trends, and SOC trends are discussed in later chapters. Coverage also includes advanced physical design techniques followed for deep submicron SOC designs. The book provides aspiring VLSI designers, practicing design engineers, and electrical engineering students with a solid background on the complex physical design requirements of SoCs which are required to contribute effectively in design roles.\u003cbr\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003eIntroduction.- SoC Physical Design Flow and Algorithms.- Physical Design Floor Plan and Placement.- Clock, Reset, and HFN.- Physical Design Routing.- Physical Design Verification.","brand":"Springer Nature Switzerland AG","offers":[{"title":"Default Title","offer_id":48743063126359,"sku":"9783030981143","price":66.49,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9783030981143.jpg?v=1720063947"},{"product_id":"electric-circuit-analysis-with-easyeda-9783031002946","title":"Electric Circuit Analysis with EasyEDA","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eThis book explains and focuses on analysis of electric circuits using an up-to-date software package. The book is filled with examples that students will see throughout a standard electric circuit course. This book is a good source to accompany and complete theoretical work of professors. The author provides a single-source for anyone who needs to analyse an electric circuit.\u003cbr\u003e\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eIntroduction.- Basic Concepts.- Three Phase Circuits and Magnetic Coupling.- Frequency Response and DC Sweep Analysis.- Exercises.- References for Further Study.\u003c\/p\u003e  \u003cp\u003e\u003cbr\u003e\u003c\/p\u003e  \u003cp\u003e\u003ci\u003e \u003c\/i\u003e\u003ci\u003e  \u003c\/i\u003e\u003c\/p\u003e  \u003cp\u003e\u003cbr\u003e\u003c\/p\u003e  \u003cp\u003e\u003cbr\u003e\u003c\/p\u003e","brand":"Springer International Publishing AG","offers":[{"title":"Default Title","offer_id":48743064699223,"sku":"9783031002946","price":44.99,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9783031002946.jpg?v=1720063955"},{"product_id":"embedded-systems-design-using-the-msp430fr2355-launchpad-9783031208874","title":"Embedded Systems Design using the MSP430FR2355","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eThis textbook for courses in Embedded Systems introduces students to necessary concepts, through a hands-on approach.\u003c\/p\u003e  \u003cp\u003eLEARN BY EXAMPLE – This book is designed to teach the material the way it is learned, through example. Every concept is supported by numerous programming examples that provide the reader with a step-by-step explanation for how and why the computer is doing what it is doing.\u003c\/p\u003e  \u003cp\u003eLEARN BY DOING – This book targets the Texas Instruments MSP430 microcontroller. This platform is a widely popular, low-cost embedded system that is used to illustrate each concept in the book. The book is designed for a reader that is at their computer with an \u003ci\u003eMSP430FR2355 LaunchPad\u003csup\u003eTM\u003c\/sup\u003e Development Kit\u003c\/i\u003e plugged in so that each example can be coded and run as they learn.\u003c\/p\u003e  \u003cp\u003eLEARN BOTH ASSEMBLY AND C – The book teaches the basic operation of an embedded computer using assembly language so that the computer operation can be explored at a low-level. Once more complicated systems are introduced (i.e., timers, analog-to-digital converters, and serial interfaces), the book moves into the C programming language. Moving to C allows the learner to abstract the operation of the lower-level hardware and focus on understanding how to “make things work”.\u003c\/p\u003e  \u003cp\u003eBASED ON SOUND PEDAGOGY - This book is designed with learning outcomes and assessment at its core. Each section addresses a specific learning outcome that the student should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure student performance on each outcome.\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003eCHAPTER 1. INTRODUCTION TO EMBEDDED SYSTEMS.- CHAPTER 2. DIGITAL LOGIC BASICS CHAPTER 3. COMPUTER SYSTEMSCHAPTER 4. THE MSP430CHAPTER 5. GETTING STARTED PROGRAMMING THE MSP430 IN ASSEMBLY.- CHAPTER 6. DATA MOVEMENT INSTRUCTIONS.- CHAPTER 7. DATA MANIPULATION INSTRUCTIONS.- CHAPTER 8. PROGRAM FLOW INSTRUCTIONS.- CHAPTER 9. DIGITAL I\/O.- CHAPTER 10. THE STACK AND SUBROUTINES.- CHAPTER 11. INTRODUCTION TO INTERRUPTS.- CHAPTER 12. INTRODUCTION TO TIMERS.- CHAPTER 13. SWITCHING TO THE C LANGUAGE.- CHAPTER 14. SERIAL COMMUNICATION IN C.- CHAPTER 15. ANALOG TO DIGITAL CONVERTERS.- CHAPTER 16. THE CLOCK SYSTEM.- CHAPTER 17. LOW-POWER MODES.- APPENDIX A. CONCEPT CHECK SOLUTIONS.","brand":"Springer International Publishing AG","offers":[{"title":"Default Title","offer_id":48743075807575,"sku":"9783031208874","price":53.99,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9783031208874.jpg?v=1720064003"},{"product_id":"introductory-programs-with-the-32bit-pic-microcontroller-9781484290507","title":"Introductory Programs with the 32bit PIC","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eEmbark on a journey into the world of embedded programming. This book introduces you to the 32bit PIC and will teach you how the main functions of C programming work and can be used with a PIC micro.\u003cp\u003eA one-stop reference for the would-be embedded programmer, you''ll explore the electronics needed for a variety of programs as well as how to use different devices with the PIC. The book starts with downloading the environment and creating a simple project, one that uses different oscillators, Phase Lock Loop, and circuitry needed to create the different system clocks-an easy entry point to this exciting environment. You''ll also review the MPLABX integrated development environment (IDE) and see how to program the 32Bit PIC, which can be adapted to different PICs.\u003c\/p\u003e\u003cp\u003eThroughout subsequent chapters, you''ll learn how to use a range of programs that use PIC modules such as the SPI, I2C, UART communication modules, the ADC module, the Capture, Compare, and Pulse Width Modulatio\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp\u003e\u003cb\u003eChapter 1 Creating Our First Project\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003eThis will take the reader through the process of creating a project in MPLABX and how to configure the different clock frequencies that are used in the 32bit PIC. You will start a simple program that allows the user to turn on and off a single LED connected to the PIC.\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eChapter 2 Header Files and Delays\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003eThis will take the reader through the important aspect of creating and using local and global header files. We will then look at creating a variable delay subroutine that we will use in a simple traffic lights program.\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eChapter 3 The Seven Segment Display\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003eThis will explain what a seven-segment display is and how they work. Then we will go on to write a program that controls the display.\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eChapter 4 The LCD\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003eThis will introduce the reader to the LCD, Liquid Crystal Display. It will explain how they work and how we can create a program to write to the display. It will then move on to explain how we can create and use special characters to display on the LCD.\u003c\/p\u003e  \u003cp\u003eIt will also introduce the reader into the concept of arrays. \u003c\/p\u003e  \u003cp\u003e\u003cb\u003eChapter 5 The Dot Matrix Display\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003eThis will introduce the reader into the use of a single 8by8 dot matrix display. It will explain how we can use the MAX 7219 driver IC to control the 8by8 matrix display. It will then go on to explain how to control a series of 4 dot matrix displays cascaded together.\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eChapter 6 Communication\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003eThis will look at how we can use the SPI module of the PIC to communicate with some EPROM to store data on. It will also move on to explain how we can use the UART terminal to communicate with a terminal.\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eChapter 7 \u003c\/b\u003e\u003cb\u003eI2C Communication\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003eThis will move on to explain what the I2C communication protocol is and how we can create a program to use I2C. It will then move on to show how we can program an I2C expander module to control the display on a LCD.\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eChapter 8 Using Interrupts\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003eThis will introduce the reader into interrupts. It will explain what they are and how we can set up the 32bit PIC to use single vectored and multi-vectored interrupts. It will also explain why and how we can set the interrupts to use different priority levels.\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eChapter 9 The RTC\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003eThis will cover using the external crystal oscillator and interrupts to create an accurate clock signal. This will then display the time of day using the TM1637 IC on four 7 segment displays.\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eChapter 10 The RTC and the DS3231\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003eThis will look at a real time clock using interrupts and an external crystal. It will then look at the DS3231 RTC Module.\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eChapter 11 The RTCC Module of the 32 bit PIC.\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003eIn this chapter we will look at using the RTCC module of the 32 bit PIC. It will explain how to create an alarm with the RTCC module. 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It will look at creating a voltmeter with the PIC and using the TC107A temperature transducer on the 16-explorer development board. \u003c\/p\u003e  \u003cp\u003e\u003cb\u003eChapter 13 \u003c\/b\u003e\u003cb\u003eThe DHT11\u003c\/b\u003e\u003cb\u003e\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003eThis will look at the DHT11 humidity and temperature sensor. \u003c\/p\u003e  \u003cp\u003eThis will look at SPI and I\u003csup\u003e2\u003c\/sup\u003eC comms.\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eChapter 14 Creating a Square Wave\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003eThis will look at creating a square wave with a fixed 50\/50 duty cycle using the compare module of the PIC. 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Readers will develop the insight needed to interpret, assess, and design switched inductor power ICs, which almost all electronic systems need, yet no other book addresses this way.\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003e1. Diodes \u0026amp; BJTs\u003c\/p\u003e  \u003cp\u003e2, Field-Effect Transistors\u003c\/p\u003e  \u003cp\u003e3. Switched Inductors\u003c\/p\u003e  \u003cp\u003e4. Power Losses\u003c\/p\u003e  \u003cp\u003e5. Frequency Response\u003c\/p\u003e  \u003cp\u003e6. Feedback Control\u003c\/p\u003e  \u003cp\u003e7. Control Loops\u003c\/p\u003e  \u003cp\u003e8. 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Its conceptual clarity, the style of explanations and the examples make the abstract concepts accessible for a wide audience.\"\u003cbr\u003eJanos Sztipanovits, Director\u003cbr\u003eE. Bronson Ingram Distinguished Professor of Engineering\u003cbr\u003eInstitute for Software Integrated Systems\u003cbr\u003eVanderbilt University\u003c\/p\u003e\u003cp\u003e\u003ci\u003eReal-Time Systems\u003c\/i\u003e focuses on hard real-time systems, which are computing systems that must meet their temporal specification in all anticipated load and fault scenarios. The book stresses the system aspects of distributed real-time applications, treating the issues of real-time, distribution and fault-tolerance from an integral point of view. A unique cross-fertilization of ideas and concepts between the academic and industrial worlds has led to the inclusion of many insightful examples from industry to explain the fundamental scientific concepts in a real-world setting.  Compared to the Second Edition, new developments in communication standards for time-sensitive networks, such as TSN and Time-Triggered Ethernet are addressed. Furthermore, this edition includes a new chapter on real-time aspects in cloud and fog computing.\u003c\/p\u003e\u003cp\u003eThe book is written as a standard textbook for a high-level undergraduate or graduate course on real-time embedded systems or cyber-physical systems.  Its practical approach to solving real-time problems, along with numerous summary exercises, makes it an excellent choice for researchers and practitioners alike.\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003eChapter. 1 The Real-Time EnvironmentChapter. 2 SimplicityChapter. 3 Global TimeChapter. 4 Real-Time (RT) ModelChapter. 5 Temporal RelationsChapter. 6 DependabilityChapter. 7 Real-Time CommunicationChapter. 8 Power and Energy AwarenessChapter. 9 Real-Time Operating SystemsChapter. 10 Real-Time SchedulingChapter. 11 System DesignChapter. 12 ValidationChapter. 13 Internet of ThingsChapter. 14 Cloud and Fog Computing","brand":"Springer International Publishing AG","offers":[{"title":"Default Title","offer_id":49372689793367,"sku":"9783031119910","price":999.99,"currency_code":"GBP","in_stock":false}]},{"product_id":"embedded-linux-systems-with-the-yocto-project-9780133443240","title":"Embedded Linux Systems with the Yocto Project","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003e\u003cstrong\u003eRudolf J. Streif\u003c\/strong\u003e has more than twenty years of experience in software engineering as a developer and as a manager leading cross-functional engineering teams with more than one hundred members. He previously served as the Linux Foundation's Director of Embedded Solutions, coordinating the Foundation's efforts for Linux in embedded. Rudolf developed the Linux Foundation's training course on the Yocto Project, which he delivered multiple times to companies and in a crash course variant during Linux Foundation events. He lives in El Cajon, California.\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003e\u003cem\u003eForeword xv\u003c\/em\u003e\u003c\/p\u003e \u003cp\u003e\u003cem\u003ePreface xvii\u003c\/em\u003e\u003c\/p\u003e \u003cp\u003e\u003cem\u003eAcknowledgments xxi\u003c\/em\u003e\u003c\/p\u003e \u003cp\u003e\u003cem\u003eAbout the Author xxiii\u003c\/em\u003e\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eChapter 1: Linux for Embedded Systems 1\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e1.1 Why Linux for Embedded Systems? 1\u003c\/p\u003e \u003cp\u003e1.2 Embedded Linux Landscape 3\u003c\/p\u003e \u003cp\u003e1.3 A Custom Linux Distribution–Why Is It Hard? 8\u003c\/p\u003e \u003cp\u003e1.4 A Word about Open Source Licensing 9\u003c\/p\u003e \u003cp\u003e1.5 Organizations, Relevant Bodies, and Standards 11\u003c\/p\u003e \u003cp\u003e1.6 Summary 13\u003c\/p\u003e \u003cp\u003e1.7 References 14\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eChapter 2: The Yocto Project 15\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e2.1 Jumpstarting Your First Yocto Project Build 15\u003c\/p\u003e \u003cp\u003e2.2 The Yocto Project Family 26\u003c\/p\u003e \u003cp\u003e2.3 A Little Bit of History 28\u003c\/p\u003e \u003cp\u003e2.4 Yocto Project Terms 31\u003c\/p\u003e \u003cp\u003e2.5 Summary 33\u003c\/p\u003e \u003cp\u003e2.6 References 34\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eChapter 3: OpenEmbedded Build System 35\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e3.1 Building Open Source Software Packages 35\u003c\/p\u003e \u003cp\u003e3.2 OpenEmbedded Workflow 39\u003c\/p\u003e \u003cp\u003e3.3 OpenEmbedded Build System Architecture 45\u003c\/p\u003e \u003cp\u003e3.4 Summary 56\u003c\/p\u003e \u003cp\u003e3.5 References 57\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eChapter 4: BitBake Build Engine 59\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e4.1 Obtaining and Installing BitBake 59\u003c\/p\u003e \u003cp\u003e4.2 Running BitBake 61\u003c\/p\u003e \u003cp\u003e4.3 BitBake Metadata 70\u003c\/p\u003e \u003cp\u003e4.4 Metadata Syntax 71\u003c\/p\u003e \u003cp\u003e4.5 Source Download 86\u003c\/p\u003e \u003cp\u003e4.6 HelloWorld–BitBake Style 95\u003c\/p\u003e \u003cp\u003e4.7 Dependency Handling 99\u003c\/p\u003e \u003cp\u003e4.8 Version Selection 102\u003c\/p\u003e \u003cp\u003e4.9 Variants 103\u003c\/p\u003e \u003cp\u003e4.10 Default Metadata 103\u003c\/p\u003e \u003cp\u003e4.11 Summary 107\u003c\/p\u003e \u003cp\u003e4.12 References 108\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eChapter 5: Troubleshooting 109\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e5.1 Logging 110\u003c\/p\u003e \u003cp\u003e5.2 Task Execution 116\u003c\/p\u003e \u003cp\u003e5.3 Analyzing Metadata 119\u003c\/p\u003e \u003cp\u003e5.4 Development Shell 120\u003c\/p\u003e \u003cp\u003e5.5 Dependency Graphs 121\u003c\/p\u003e \u003cp\u003e5.6 Debugging Layers 122\u003c\/p\u003e \u003cp\u003e5.7 Summary 124\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eChapter 6: Linux System Architecture 127\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e6.1 Linux or GNU\/Linux? 127\u003c\/p\u003e \u003cp\u003e6.2 Anatomy of a Linux System 128\u003c\/p\u003e \u003cp\u003e6.3 Bootloader 129\u003c\/p\u003e \u003cp\u003e6.4 Kernel 134\u003c\/p\u003e \u003cp\u003e6.5 User Space 141\u003c\/p\u003e \u003cp\u003e6.6 Summary 143\u003c\/p\u003e \u003cp\u003e6.7 References 144\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eChapter 7: Building a Custom Linux Distribution 145\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e7.1 Core Images–Linux Distribution Blueprints 146\u003c\/p\u003e \u003cp\u003e7.2 Building Images from Scratch 160\u003c\/p\u003e \u003cp\u003e7.3 Image Options 161\u003c\/p\u003e \u003cp\u003e7.4 Distribution Configuration 169\u003c\/p\u003e \u003cp\u003e7.5 External Layers 181\u003c\/p\u003e \u003cp\u003e7.6 Hob 181\u003c\/p\u003e \u003cp\u003e7.7 Summary 184\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eChapter 8: Software Package Recipes 185\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e8.1 Recipe Layout and Conventions 185\u003c\/p\u003e \u003cp\u003e8.2 Writing a New Recipe 196\u003c\/p\u003e \u003cp\u003e8.3 Recipe Examples 212\u003c\/p\u003e \u003cp\u003e8.4 Devtool 218\u003c\/p\u003e \u003cp\u003e8.5 Summary 224\u003c\/p\u003e \u003cp\u003e8.6 References 224\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eChapter 9: Kernel Recipes 225\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e9.1 Kernel Configuration 226\u003c\/p\u003e \u003cp\u003e9.2 Kernel Patches 231\u003c\/p\u003e \u003cp\u003e9.3 Kernel Recipes 233\u003c\/p\u003e \u003cp\u003e9.4 Out-of-Tree Modules 251\u003c\/p\u003e \u003cp\u003e9.5 Device Tree 257\u003c\/p\u003e \u003cp\u003e9.6 Summary 258\u003c\/p\u003e \u003cp\u003e9.7 References 259\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eChapter 10: Board Support Packages 261\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e10.1 Yocto Project BSP Philosophy 261\u003c\/p\u003e \u003cp\u003e10.2 Building with a BSP 265\u003c\/p\u003e \u003cp\u003e10.3 Inside a Yocto Project BSP 277\u003c\/p\u003e \u003cp\u003e10.4 Creating a Yocto Project BSP 282\u003c\/p\u003e \u003cp\u003e10.5 Tuning 289\u003c\/p\u003e \u003cp\u003e10.6 Creating Bootable Media Images 290\u003c\/p\u003e \u003cp\u003e10.7 Summary 299\u003c\/p\u003e \u003cp\u003e10.8 References 299\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eChapter 11: Application Development 301\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e11.1 Inside a Yocto Project ADT 302\u003c\/p\u003e \u003cp\u003e11.2 Setting Up a Yocto Project ADT 304\u003c\/p\u003e \u003cp\u003e11.3 Building Applications 315\u003c\/p\u003e \u003cp\u003e11.4 Eclipse Integration 317\u003c\/p\u003e \u003cp\u003e11.5 Application Development Using an Emulated Target 331\u003c\/p\u003e \u003cp\u003e11.6 Summary 333\u003c\/p\u003e \u003cp\u003e11.7 References 334\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eChapter 12: Licensing and Compliance 335\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e12.1 Managing Licenses 335\u003c\/p\u003e \u003cp\u003e12.2 Managing Source Code 341\u003c\/p\u003e \u003cp\u003e12.3 Summary 343\u003c\/p\u003e \u003cp\u003e12.4 References 344\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eChapter 13: Advanced Topics 345\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e13.1 Toaster 345\u003c\/p\u003e \u003cp\u003e13.2 Build History 358\u003c\/p\u003e \u003cp\u003e13.3 Source Mirrors 366\u003c\/p\u003e \u003cp\u003e13.4 Autobuilder 368\u003c\/p\u003e \u003cp\u003e13.5 Summary 374\u003c\/p\u003e \u003cp\u003e13.6 References 375\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eAppendix A: Open Source Licenses 377\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003eA.1 MIT License (MIT) 377\u003c\/p\u003e \u003cp\u003eA.2 GNU General Public License (GPL) Version 2 378\u003c\/p\u003e \u003cp\u003eA.3 GNU General Public License (GPL) Version 3 384\u003c\/p\u003e \u003cp\u003eA.4 Apache License Version 2.0 397\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eAppendix B: Metadata Reference 403\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e\u003cem\u003eIndex 429\u003c\/em\u003e\u003c\/p\u003e","brand":"Pearson Education (US)","offers":[{"title":"Default Title","offer_id":49396171866455,"sku":"9780133443240","price":999.99,"currency_code":"GBP","in_stock":false}]},{"product_id":"embedded-systems-9781119457503","title":"Embedded Systems","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003e\u003cb\u003eEmbedded Systems: A Contemporary Design Tool, Second Edition\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eEmbedded systems are one of the foundational elements of today?s evolving and growing computer technology. From operating our cars, managing our smart phones, cleaning our homes, or cooking our meals, the special computers we call embedded systems are quietly and unobtrusively making our lives easier, safer, and more connected. While working in increasingly challenging environments, embedded systems give us the ability to put increasing amounts of capability into ever-smaller and more powerful devices.\u003c\/p\u003e \u003cp\u003e\u003ci\u003eEmbedded Systems: A Contemporary Design Tool, Second Edition \u003c\/i\u003eintroduces you to the theoretical hardware and software foundations of these systems and expands into the areas of signal integrity, system security, low power, and hardware-software co-design. The text builds upon earlier material to show you how to apply reliable, robust solutions to a wide range of applications operating in today?s of\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp\u003eAbout the Author xxxiii\u003c\/p\u003e \u003cp\u003eForeword xxxv\u003c\/p\u003e \u003cp\u003ePreface xlix\u003c\/p\u003e \u003cp\u003eAcknowledgment lix\u003c\/p\u003e \u003cp\u003eAbout the Companion Website lxi\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 1 Hardware and Software Infrastructure\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1 The Hardware Side – Part 1: An Introduction 1\u003c\/p\u003e \u003cp\u003e2 The Hardware Side – Part 2: Combinational Logic – A Practical View 55\u003c\/p\u003e \u003cp\u003e3 The Hardware Side – Part 3: Storage Elements and Finite-State Machines – A Practical View 111\u003c\/p\u003e \u003cp\u003e4 Memories and the Memory Subsystem 165\u003c\/p\u003e \u003cp\u003e5 An Introduction to Software Modeling 215\u003c\/p\u003e \u003cp\u003e6 The Software Side – Part 1: The C Program 243\u003c\/p\u003e \u003cp\u003e7 The Software Side – Part 2: Pointers and Functions 279\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 2 Developing the Foundation\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8 Safety, Security, Reliability, and Robust Design 331\u003c\/p\u003e \u003cp\u003e9 Embedded Systems Design and Development – Hardware– Software Co-Design 403\u003c\/p\u003e \u003cp\u003e10 Hardware Test and Debug 507\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 3 Doing the Work\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11 Real-Time Kernels and Operating Systems 541\u003c\/p\u003e \u003cp\u003e12 Tasks and Task Management 573\u003c\/p\u003e \u003cp\u003e13 Deadlocks 625\u003c\/p\u003e \u003cp\u003e14 Performance Analysis and Optimization 645\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart 4 Developing the Foundation\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e15 Working Outside of the Processor I: A Model of Interprocess Communication 715\u003c\/p\u003e \u003cp\u003e16 Working Outside of the Processor I: Refining the Model of Interprocess Communication 733\u003c\/p\u003e \u003cp\u003e17 Working Outside of the Processor II: Interfacing to Local Devices 789\u003c\/p\u003e \u003cp\u003e18 Working Outside of the Processor III: Interfacing to Remote Devices 837\u003c\/p\u003e \u003cp\u003e19 Programmable Logic Devices 869\u003c\/p\u003e \u003cp\u003e20 Practical Considerations Signal Behavior in the Real World – Part 1 – Noise and Crosstalk 893\u003c\/p\u003e \u003cp\u003e21 Practical Considerations Signal Behavior in the Real World – Part 2 – High-Speed Signaling 909\u003c\/p\u003e \u003cp\u003eA Verilog Overview: The Verilog Hardware Description Language 949\u003c\/p\u003e \u003cp\u003eFurther Reading 981\u003c\/p\u003e \u003cp\u003eIndex 991\u003c\/p\u003e","brand":"John Wiley \u0026 Sons Inc","offers":[{"title":"Default Title","offer_id":49407059132759,"sku":"9781119457503","price":97.8,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9781119457503.jpg?v=1730498029"},{"product_id":"getting-started-with-intel-edison-9781457187599","title":"Getting Started with Intel Edison","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eThis book, written by Stephanie Moyerman, a research scientist with Intel's Smart Device Innovation Team, teaches you everything you need to know to get started making things with Edison, the compact and powerful Internet of Things platform.","brand":"O'Reilly Media","offers":[{"title":"Default Title","offer_id":49408620659031,"sku":"9781457187599","price":16.99,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9781457187599.jpg?v=1730503568"},{"product_id":"node-js-for-embedded-systems-9781491928998","title":"Node.js for Embedded Systems","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eThis practical guide shows hardware and software engineers, makers, and web developers how to talk in JavaScript with a variety of hardware platforms. Authors Patrick Mulder and Kelsey Breseman also delve into the basics of microcontrollers, single-board computers, and other hardware components.","brand":"O'Reilly Media","offers":[{"title":"Default Title","offer_id":49409189642583,"sku":"9781491928998","price":19.19,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9781491928998.jpg?v=1730505851"},{"product_id":"embedded-systems-analysis-and-modeling-with-sysml-uml-and-aadl-9781848215009","title":"Embedded Systems: Analysis and Modeling with","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eSince the construction of the first embedded system in the 1960s, embedded systems have continued to spread. They provide a continually increasing number of services and are part of our daily life. The development of these systems is a difficult problem which does not yet have a global solution. Another difficulty is that systems are plunged into the real world, which is not discrete (as is generally understood in computing), but has a richness of behaviors which sometimes hinders the formulation of simplifying assumptions due to their generally autonomous nature and they must face possibly unforeseen situations (incidents, for example), or even situations that lie outside the initial design assumptions.\u003c\/p\u003e \u003cp\u003e\u003ci\u003eEmbedded Systems\u003c\/i\u003e presents the state of the art of the development of embedded systems and, in particular, concentrates on the modeling and analysis of these systems by looking at “model-driven engineering”, (MDE2): SysML, UML\/MARTE and AADL. A case study (based on a pacemaker) is presented which enables the reader to observe how the different aspects of a system are addressed using the different approaches. All three systems are important in that they provide the reader with a global view of their possibilities and demonstrate the contributions of each approach in the different stages of the software lifecycle. Chapters dedicated to analyzing the specification and code generation are also presented.\u003c\/p\u003e \u003cp\u003eContents\u003c\/p\u003e \u003cp\u003eForeword, Brian R. Larson.\u003cbr\u003eForeword, Dominique Potier.\u003cbr\u003eIntroduction, Fabrice Kordon, Jérôme Hugues, Agusti Canals and Alain Dohet.\u003cbr\u003ePart 1. General Concepts\u003cbr\u003e1. Elements for the Design of Embedded Computer Systems, Fabrice Kordon, Jérôme Hugues, Agusti Canals and Alain Dohet.\u003cbr\u003e2. Case Study: Pacemaker, Fabrice Kordon, Jérôme Hugues, Agusti Canals and Alain Dohet.\u003cbr\u003ePart 2. SysML\u003cbr\u003e3. Presentation of SysML Concepts, Jean-Michel Bruel and Pascal Roques.\u003cbr\u003e4. Modeling of the Case Study Using SysML, Loïc Fejoz, Philippe Leblanc and Agusti Canals.\u003cbr\u003e5. Requirements Analysis, Ludovic Apvrille and Pierre De Saqui-Sannes.\u003cbr\u003ePart 3. MARTE\u003cbr\u003e6. An Introduction to MARTE Concepts, Sébastien Gérard and François Terrier.\u003cbr\u003e7. Case Study Modeling Using MARTE, Jérôme Delatour and Joël Champeau.\u003cbr\u003e8. Model-Based Analysis, Frederic Boniol, Philippe Dhaussy, Luka Le Roux and Jean-Charles Roger.\u003cbr\u003e9. Model-Based Deployment and Code Generation, Chokri Mraidha, Ansgar Radermacher and Sébastien Gérard.\u003cbr\u003ePart 4. AADL\u003cbr\u003e10. Presentation of the AADL Concepts, Jérôme Hugues and Xavier Renault.\u003cbr\u003e11. Case Study Modeling Using AADL, Etienne Borde.\u003cbr\u003e12. Model-Based Analysis, Thomas Robert and Jérôme Hugues.\u003cbr\u003e13. Model-Based Code Generation, Laurent Pautet and Béchir Zalila.\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eForeword xiii\u003cbr\u003e \u003ci\u003eBrian R. LARSON\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003eForeword xv\u003cbr\u003e \u003ci\u003eDominique POTIER\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003eIntroduction xix\u003cbr\u003e \u003ci\u003eFabrice KORDON, Jérôme HUGUES, Agusti CANALS and Alain DOHET\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART 1. General Concepts 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 1. Elements for the Design of Embedded Computer Systems 3\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eFabrice KORDON, Jérôme HUGUES, Agusti CANALS and Alain DOHET\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e1.1. Introduction 3\u003c\/p\u003e \u003cp\u003e1.2. System modeling 5\u003c\/p\u003e \u003cp\u003e1.3. A brief presentation of UML 6\u003c\/p\u003e \u003cp\u003e1.3.1. The UML static diagrams 7\u003c\/p\u003e \u003cp\u003e1.3.2. The UML dynamic diagrams 9\u003c\/p\u003e \u003cp\u003e1.4. Model-driven development approaches 10\u003c\/p\u003e \u003cp\u003e1.4.1. The concepts 10\u003c\/p\u003e \u003cp\u003e1.4.2. The technologies 11\u003c\/p\u003e \u003cp\u003e1.4.3. The context of the wider field 12\u003c\/p\u003e \u003cp\u003e1.5. System analysis 14\u003c\/p\u003e \u003cp\u003e1.5.1. Formal verification via proving 15\u003c\/p\u003e \u003cp\u003e1.5.2. Formal verification by model-checking 15\u003c\/p\u003e \u003cp\u003e1.5.3. The languages to express specifications 16\u003c\/p\u003e \u003cp\u003e1.5.4. The actual limits of formal approaches 19\u003c\/p\u003e \u003cp\u003e1.6. Methodological aspects of the development of embedded computer systems 20\u003c\/p\u003e \u003cp\u003e1.6.1. The main technical processes 22\u003c\/p\u003e \u003cp\u003e1.6.2. The importance of the models 23\u003c\/p\u003e \u003cp\u003e1.7. Conclusion 24\u003c\/p\u003e \u003cp\u003e1.8. Bibliography 25\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 2. Case Study: Pacemaker 29\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eFabrice KORDON, Jérôme HUGUES, Agusti CANALS and Alain DOHET\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e2.1. Introduction 29\u003c\/p\u003e \u003cp\u003e2.2. The heart and the pacemaker 30\u003c\/p\u003e \u003cp\u003e2.2.1. The heart 30\u003c\/p\u003e \u003cp\u003e2.2.2. Presentation of a pacemaker 32\u003c\/p\u003e \u003cp\u003e2.3. Case study specification 33\u003c\/p\u003e \u003cp\u003e2.3.1. System definition 34\u003c\/p\u003e \u003cp\u003e2.3.2. System lifecycle 35\u003c\/p\u003e \u003cp\u003e2.3.3. System requirements 36\u003c\/p\u003e \u003cp\u003e2.3.4. Pacemaker behavior 39\u003c\/p\u003e \u003cp\u003e2.4. Conclusion 42\u003c\/p\u003e \u003cp\u003e2.5. Bibliography 43\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART 2. SysML 45\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 3. Presentation of SysML Concepts 47\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eJean-Michel BRUEL and Pascal ROQUES\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e3.1. Introduction 47\u003c\/p\u003e \u003cp\u003e3.2. The origins of SysML 48\u003c\/p\u003e \u003cp\u003e3.3. General overview: the nine types of diagrams 49\u003c\/p\u003e \u003cp\u003e3.4. Modeling the requirements 50\u003c\/p\u003e \u003cp\u003e3.4.1. Use case diagram 50\u003c\/p\u003e \u003cp\u003e3.4.2. Requirement diagram 51\u003c\/p\u003e \u003cp\u003e3.5. Structural modeling 53\u003c\/p\u003e \u003cp\u003e3.5.1. Block definition diagram 54\u003c\/p\u003e \u003cp\u003e3.5.2. Internal block diagram 56\u003c\/p\u003e \u003cp\u003e3.5.3. Package diagram 58\u003c\/p\u003e \u003cp\u003e3.6. Dynamic modeling 59\u003c\/p\u003e \u003cp\u003e3.6.1. Sequence diagram 59\u003c\/p\u003e \u003cp\u003e3.6.2. State machine diagram 61\u003c\/p\u003e \u003cp\u003e3.6.3. Activity diagram 63\u003c\/p\u003e \u003cp\u003e3.7. Transverse modeling 65\u003c\/p\u003e \u003cp\u003e3.7.1. Parametric diagram 65\u003c\/p\u003e \u003cp\u003e3.7.2. Allocation and traceability 67\u003c\/p\u003e \u003cp\u003e3.8. Environment and tools 68\u003c\/p\u003e \u003cp\u003e3.9. Conclusion 68\u003c\/p\u003e \u003cp\u003e3.10. Bibliography 68\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 4. Modeling of the Case Study Using SysML 71\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eLoïc FEJOZ, Philippe LEBLANC and Agusti CANALS\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e4.1. Introduction 71\u003c\/p\u003e \u003cp\u003e4.2. System specification 73\u003c\/p\u003e \u003cp\u003e4.2.1. Context 73\u003c\/p\u003e \u003cp\u003e4.2.2. Requirements model and operational scenarios 75\u003c\/p\u003e \u003cp\u003e4.2.3. Requirements model 78\u003c\/p\u003e \u003cp\u003e4.3. System design 80\u003c\/p\u003e \u003cp\u003e4.3.1. Functional model 81\u003c\/p\u003e \u003cp\u003e4.3.2. Domain-specific data 83\u003c\/p\u003e \u003cp\u003e4.3.3. Logical architectural model 86\u003c\/p\u003e \u003cp\u003e4.3.4. Physical architectural model 90\u003c\/p\u003e \u003cp\u003e4.4. Traceability and allocations 90\u003c\/p\u003e \u003cp\u003e4.4.1. “Technical needs: divers” traceability diagram 90\u003c\/p\u003e \u003cp\u003e4.4.2. Traceability diagram “technical needs: behavior of the pacemaker” 91\u003c\/p\u003e \u003cp\u003e4.4.3. Allocation diagram 92\u003c\/p\u003e \u003cp\u003e4.5. Test model 93\u003c\/p\u003e \u003cp\u003e4.5.1. Traceability diagram “system test: requirements verification” 93\u003c\/p\u003e \u003cp\u003e4.5.2. Sequence diagram for the test game TC-PM-07 94\u003c\/p\u003e \u003cp\u003e4.5.3. Diagrams presenting a general view of the requirements 94\u003c\/p\u003e \u003cp\u003e4.6. Conclusion 95\u003c\/p\u003e \u003cp\u003e4.7. Bibliography 97\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 5. Requirements Analysis 99\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eLudovic APVRILLE and Pierre DE SAQUI-SANNES\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e5.1. Introduction 99\u003c\/p\u003e \u003cp\u003e5.2. The AVATAR language and the TTool tool 100\u003c\/p\u003e \u003cp\u003e5.2.1. Method 101\u003c\/p\u003e \u003cp\u003e5.2.2. AVATAR language and SysML standard 101\u003c\/p\u003e \u003cp\u003e5.2.3. The TEPE language for expressing properties 102\u003c\/p\u003e \u003cp\u003e5.2.4. TTool 103\u003c\/p\u003e \u003cp\u003e5.3. An AVATAR expression of the SysML model of the enhanced pacemaker 103\u003c\/p\u003e \u003cp\u003e5.3.1. Functioning of the pacemaker and modeling hypotheses 103\u003c\/p\u003e \u003cp\u003e5.3.2. Requirements diagram 104\u003c\/p\u003e \u003cp\u003e5.4. Architecture 105\u003c\/p\u003e \u003cp\u003e5.5. Behavior 106\u003c\/p\u003e \u003cp\u003e5.6. Formal verification of the VVI mode 107\u003c\/p\u003e \u003cp\u003e5.6.1. General properties 108\u003c\/p\u003e \u003cp\u003e5.6.2. Expressing properties using TEPE 108\u003c\/p\u003e \u003cp\u003e5.6.3. The use of temporal logic 109\u003c\/p\u003e \u003cp\u003e5.6.4. Observer-guided verification 111\u003c\/p\u003e \u003cp\u003e5.6.5. Coming back to the model 112\u003c\/p\u003e \u003cp\u003e5.7. Related work 113\u003c\/p\u003e \u003cp\u003e5.7.1. Languages 113\u003c\/p\u003e \u003cp\u003e5.7.2. Tools 114\u003c\/p\u003e \u003cp\u003e5.8. Conclusion 115\u003c\/p\u003e \u003cp\u003e5.9. Appendix: TTool 116\u003c\/p\u003e \u003cp\u003e5.10. Bibliography 116\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART 3. MARTE 119\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 6. An Introduction to MARTE Concepts 121\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eSébastien GÉRARD and François TERRIER\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e6.1. Introduction 121\u003c\/p\u003e \u003cp\u003e6.2. General remarks 121\u003c\/p\u003e \u003cp\u003e6.2.1. Possible uses of MARTE 122\u003c\/p\u003e \u003cp\u003e6.2.2. How should we read the norm? 123\u003c\/p\u003e \u003cp\u003e6.2.3. The MARTE architecture 124\u003c\/p\u003e \u003cp\u003e6.2.4. MARTE and SysML 127\u003c\/p\u003e \u003cp\u003e6.2.5. An open source support 128\u003c\/p\u003e \u003cp\u003e6.3. Several MARTE details 128\u003c\/p\u003e \u003cp\u003e6.3.1. Modeling non-functional properties 128\u003c\/p\u003e \u003cp\u003e6.3.2. A components model for the real-time embedded system 133\u003c\/p\u003e \u003cp\u003e6.4. Conclusion 137\u003c\/p\u003e \u003cp\u003e6.5. Bibliography 137\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 7. Case Study Modeling Using MARTE 139\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eJérôme DELATOUR and Joël CHAMPEAU\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e7.1. Introduction 139\u003c\/p\u003e \u003cp\u003e7.1.1. Hypotheses used in modeling 139\u003c\/p\u003e \u003cp\u003e7.1.2. The modeling methodology used 140\u003c\/p\u003e \u003cp\u003e7.1.3. Chapter layout 141\u003c\/p\u003e \u003cp\u003e7.2. Software analysis 141\u003c\/p\u003e \u003cp\u003e7.2.1. Use case and interface characterization 141\u003c\/p\u003e \u003cp\u003e7.2.2. The sphere of application 144\u003c\/p\u003e \u003cp\u003e7.3. Preliminary software design – the architectural component 145\u003c\/p\u003e \u003cp\u003e7.3.1. The candidate architecture 146\u003c\/p\u003e \u003cp\u003e7.3.2. Identifying the components 146\u003c\/p\u003e \u003cp\u003e7.3.3. Presentation of the candidate architecture 148\u003c\/p\u003e \u003cp\u003e7.3.4. A presentation of the detailed interfaces 150\u003c\/p\u003e \u003cp\u003e7.4. Software preliminary design – behavioral component 151\u003c\/p\u003e \u003cp\u003e7.4.1. The controller 151\u003c\/p\u003e \u003cp\u003e7.4.2. The cardiologist 153\u003c\/p\u003e \u003cp\u003e7.4.3. The operating modes of the cardiologist 153\u003c\/p\u003e \u003cp\u003e7.5. Conclusion 155\u003c\/p\u003e \u003cp\u003e7.6. Bibliography 156\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 8. Model-Based Analysis 157\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eFrederic BONIOL, Philippe DHAUSSY, Luka LE ROUX and Jean-Charles ROGER\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e8.1. Introduction 157\u003c\/p\u003e \u003cp\u003e8.2. Model and requirements to be verified 161\u003c\/p\u003e \u003cp\u003e8.2.1. The UML-MARTE model that needs to be translated in Fiacre 161\u003c\/p\u003e \u003cp\u003e8.2.2. Fiacre language 162\u003c\/p\u003e \u003cp\u003e8.2.3. The translation principles of the UML model in Fiacre 163\u003c\/p\u003e \u003cp\u003e8.2.4. Requirements 165\u003c\/p\u003e \u003cp\u003e8.3. Model-checking of the requirements 166\u003c\/p\u003e \u003cp\u003e8.3.1. Use case 166\u003c\/p\u003e \u003cp\u003e8.3.2. Properties 167\u003c\/p\u003e \u003cp\u003e8.3.3. Property check 170\u003c\/p\u003e \u003cp\u003e8.3.4. First assessment 172\u003c\/p\u003e \u003cp\u003e8.4. Context exploitation 172\u003c\/p\u003e \u003cp\u003e8.4.1. Identifying the context scenarios 173\u003c\/p\u003e \u003cp\u003e8.4.2. Automatic partitioning of the context graphs 174\u003c\/p\u003e \u003cp\u003e8.4.3. CDL language 175\u003c\/p\u003e \u003cp\u003e8.4.4. CDL model exploitation in a model-checker 177\u003c\/p\u003e \u003cp\u003e8.4.5. Description of a CDL context 178\u003c\/p\u003e \u003cp\u003e8.4.6. Results 179\u003c\/p\u003e \u003cp\u003e8.5. Assessment 180\u003c\/p\u003e \u003cp\u003e8.6. Conclusion 181\u003c\/p\u003e \u003cp\u003e8.7. Bibliography 182\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 9. Model-Based Deployment and Code Generation 185\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eChokri MRAIDHA, Ansgar RADERMACHER and Sébastien GÉRARD\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e9.1. Introduction 185\u003c\/p\u003e \u003cp\u003e9.2. Input models 187\u003c\/p\u003e \u003cp\u003e9.2.1. Description of the executable component-based model 187\u003c\/p\u003e \u003cp\u003e9.2.2. Description of the platform model 188\u003c\/p\u003e \u003cp\u003e9.2.3. Description of the deployment model 189\u003c\/p\u003e \u003cp\u003e9.3. Generation of the implementation model 190\u003c\/p\u003e \u003cp\u003e9.3.1. Main concepts 191\u003c\/p\u003e \u003cp\u003e9.3.2. Connector pattern 191\u003c\/p\u003e \u003cp\u003e9.3.3. Container pattern 193\u003c\/p\u003e \u003cp\u003e9.3.4. Implementation of the components 195\u003c\/p\u003e \u003cp\u003e9.3.5. Resulting implementation components 197\u003c\/p\u003e \u003cp\u003e9.4. Code generation 197\u003c\/p\u003e \u003cp\u003e9.4.1. Deployment of the components 198\u003c\/p\u003e \u003cp\u003e9.4.2. Transformation into an object-oriented model 199\u003c\/p\u003e \u003cp\u003e9.4.3. Generating code 200\u003c\/p\u003e \u003cp\u003e9.5. Support tools 201\u003c\/p\u003e \u003cp\u003e9.6. Conclusion 202\u003c\/p\u003e \u003cp\u003e9.7. Bibliography 202\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART 4. AADL 205\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 10. Presentation of the AADL Concepts 207\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eJérôme HUGUES and Xavier RENAULT\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e10.1. Introduction 207\u003c\/p\u003e \u003cp\u003e10.2. General ADL concepts 207\u003c\/p\u003e \u003cp\u003e10.3. AADLv2, an ADL for design and analysis 208\u003c\/p\u003e \u003cp\u003e10.3.1. A history of the AADL 208\u003c\/p\u003e \u003cp\u003e10.3.2. A brief introduction to AADL 209\u003c\/p\u003e \u003cp\u003e10.3.3. Tools 211\u003c\/p\u003e \u003cp\u003e10.4. Taxonomy of the AADL entities 211\u003c\/p\u003e \u003cp\u003e10.4.1. Language elements: the components 212\u003c\/p\u003e \u003cp\u003e10.4.2. Connections between the components 214\u003c\/p\u003e \u003cp\u003e10.4.3. Language elements: attributes 215\u003c\/p\u003e \u003cp\u003e10.4.4. Language elements: extensions and refinements 219\u003c\/p\u003e \u003cp\u003e10.5. AADL annexes 220\u003c\/p\u003e \u003cp\u003e10.5.1. Data modeling annex 220\u003c\/p\u003e \u003cp\u003e10.6. Analysis of AADL models 221\u003c\/p\u003e \u003cp\u003e10.6.1. Structural properties 222\u003c\/p\u003e \u003cp\u003e10.6.2. Qualitative properties 222\u003c\/p\u003e \u003cp\u003e10.6.3. Quantitative properties 223\u003c\/p\u003e \u003cp\u003e10.7. Conclusion 224\u003c\/p\u003e \u003cp\u003e10.8. Bibliography 225\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 11. Case Study Modeling Using AADL 227\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eEtienne BORDE\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e11.1. Introduction 227\u003c\/p\u003e \u003cp\u003e11.2. Review of the structure of a pacemaker 229\u003c\/p\u003e \u003cp\u003e11.3. AADL modeling of the structure of the pacemaker 230\u003c\/p\u003e \u003cp\u003e11.3.1. Decomposition of the system into several subsystems 230\u003c\/p\u003e \u003cp\u003e11.3.2. Execution and communication infrastructure 233\u003c\/p\u003e \u003cp\u003e11.4. Overview of the functioning of the pacemaker 235\u003c\/p\u003e \u003cp\u003e11.4.1. The operational modes of the pacemaker 235\u003c\/p\u003e \u003cp\u003e11.4.2. The operational sub-modes of the pacemaker 235\u003c\/p\u003e \u003cp\u003e11.4.3. Some functionalities of the pacemaker 237\u003c\/p\u003e \u003cp\u003e11.5. AADL modeling of the software architecture of the pulse generator 240\u003c\/p\u003e \u003cp\u003e11.5.1. AADL modeling of the operational modes of the pulse generator 240\u003c\/p\u003e \u003cp\u003e11.5.2. AADL modeling of the features of the pulse generator in the permanent mode 242\u003c\/p\u003e \u003cp\u003e11.6. Modeling of the deployment of the pacemaker 247\u003c\/p\u003e \u003cp\u003e11.7. Conclusion 249\u003c\/p\u003e \u003cp\u003e11.8. Bibliography 250\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 12. Model-Based Analysis 251\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eThomas ROBERT and Jérôme HUGUES\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e12.1. Introduction 251\u003c\/p\u003e \u003cp\u003e12.2. Behavioral validation, per mode and global 252\u003c\/p\u003e \u003cp\u003e12.2.1. Validation context and fine tuning of the requirements 253\u003c\/p\u003e \u003cp\u003e12.2.2. Translation of the behavioral automata into UPPAAL 253\u003c\/p\u003e \u003cp\u003e12.2.3. Refining requirements 22-23\/P 258\u003c\/p\u003e \u003cp\u003e12.2.4. Study of the permanent\/VVT mode 260\u003c\/p\u003e \u003cp\u003e12.2.5. Study of the changing of the permanent\/VVT→Magnet\/VOO mode 261\u003c\/p\u003e \u003cp\u003e12.3. Conclusion 262\u003c\/p\u003e \u003cp\u003e12.4. Bibliography 263\u003c\/p\u003e \u003cp\u003e\u003cb\u003eChapter 13. Model-Based Code Generation 265\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eLaurent PAUTET and Béchir ZALILA\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e13.1. Introduction 265\u003c\/p\u003e \u003cp\u003e13.2. Software component generation 268\u003c\/p\u003e \u003cp\u003e13.2.1. Data conversion 269\u003c\/p\u003e \u003cp\u003e13.2.2. Conversion of subprograms 272\u003c\/p\u003e \u003cp\u003e13.2.3. Conversion of execution threads 275\u003c\/p\u003e \u003cp\u003e13.2.4. Conversion of the instances of shared data 283\u003c\/p\u003e \u003cp\u003e13.3. Middleware components generation 283\u003c\/p\u003e \u003cp\u003e13.4. Configuration and deployment of middleware components 284\u003c\/p\u003e \u003cp\u003e13.4.1. Deployment 284\u003c\/p\u003e \u003cp\u003e13.5. Integration of the compilation chain 285\u003c\/p\u003e \u003cp\u003e13.6. Conclusion 287\u003c\/p\u003e \u003cp\u003e13.7. Bibliography 287\u003c\/p\u003e \u003cp\u003eList of Authors 289\u003c\/p\u003e \u003cp\u003eIndex 291\u003c\/p\u003e","brand":"ISTE Ltd and John Wiley \u0026 Sons Inc","offers":[{"title":"Default Title","offer_id":49413713166679,"sku":"9781848215009","price":132.0,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9781848215009.jpg?v=1730521134"},{"product_id":"inductive-links-for-wireless-power-transfer-fundamental-concepts-for-designing-high-efficiency-wireless-power-transfer-links-9783030654764","title":"Inductive Links for Wireless Power Transfer:","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eThis book presents a system-level analysis of inductive wireless power transfer (WPT) links. The basic requirements, design parameters, and utility of key building blocks used in inductive WPT links are presented, followed by detailed theoretical analysis, design, and optimization procedure, while considering practical aspects for various application domains. Readers are provided with fundamental, yet easy to follow guidelines to help them design high-efficiency inductive links, based on a set of application-specific target specifications. The authors discuss a wide variety of recently proposed approaches to achieve the maximum efficiency point, such as the use of additional resonant coils, matching networks, modulation of the load quality factor (Q-modulation), and adjustable DC-DC converters. Additionally, the attainability of the maximum efficiency point together with output voltage regulation is addressed in a closed-loop power control mechanism. Numerous examples, including MATLAB\/Octave calculation scripts and LTspice simulation files, are presented throughout the book. This enables readers to check their own results and test variations, facilitating a thorough understanding of the concepts discussed.  The book concludes with real examples demonstrating the practical application of topics discussed.\u003cbr\u003e\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cul\u003e\n\u003cli\u003eCovers both introductory and advanced levels of theory and practice, providing readers with required knowledge and tools to carry on from simple to advanced wireless power transfer concepts and system designs;\u003c\/li\u003e\n\u003cli\u003eProvides theoretical foundation throughout the book to address different design aspects;\u003c\/li\u003e\n\u003cli\u003ePresents numerous examples throughout the book to complement the analysis and designs;\u003c\/li\u003e\n\u003cli\u003eIncludes supplementary material (numerical and circuit simulation files) that provide a \"hands-on\" experience for the reader;\u003c\/li\u003e\n\u003cli\u003eUses real examples to demonstrate the practical application of topics discussed.\u003c\/li\u003e\n\u003c\/ul\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eIntroduction to Wireless Power Transfer.- Inductive Wireless Power Transfer.- Inductive Link: Practical Aspects.- Back telemetry.- Achieving the Optimum Operating Point (OOP).- Adaptive circuits to track the Optimum Operating Point (OOP).- Closed-loop WPT links.- System Design Examples.\u003c\/p\u003e","brand":"Springer Nature Switzerland AG","offers":[{"title":"Default Title","offer_id":49415627833687,"sku":"9783030654764","price":94.99,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9783030654764.jpg?v=1730527567"},{"product_id":"security-of-biochip-cyberphysical-systems-9783030932732","title":"Security of Biochip Cyberphysical Systems","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eThis book provides readers with a valuable guide to understanding security and the interplay of computer science, microfluidics, and biochemistry in a biochip cyberphysical system (CPS).  The authors uncover new, potential threat and trust-issues to address, as this emerging technology is poised to be adapted at a large scale. Readers will learn how to secure biochip CPS by leveraging the available resources in different application contexts, as well as how to ensure intellectual property (IP) is protected against theft and counterfeits. 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Readers learn about the physical implications of using heterogeneous 3D technologies for SoC integration, while also learning to maximize the 3D-technology gains, through a physical-effect-aware architecture design. The book provides a deep theoretical background covering all abstraction-levels needed to research and architect tomorrow’s 3D-integrated circuits, an extensive set of optimization methods (for power, performance, area, and yield), as well as an open-source optimization and simulation framework for fast exploration of novel designs.\u003cbr\u003e\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cb\u003ePart I Introduction\u003c\/b\u003e\u003cp\u003e\u003cb\u003e1 Introduction to 3D Technologies \u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e1.1 Motivation for Heterogenous 3D ICs\u003c\/p\u003e  \u003cp\u003e1.2 3D Technologies\u003c\/p\u003e  \u003cp\u003e1.3 TSV Capacitances—A Problem Resistant to Scaling\u003c\/p\u003e  \u003cp\u003e1.4 Conclusion\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e2 Interconnect Architectures for 3D Technologies\u003c\/b\u003e\u003c\/p\u003e  2.1 Interconnect Architectures\u003cp\u003e\u003c\/p\u003e  \u003cp\u003e2.2 Overview of Interconnect Architectures for 3D ICs\u003c\/p\u003e  \u003cp\u003e2.3 Three-dimensional Networks on chips\u003c\/p\u003e  \u003cp\u003e2.4 Conclusion\u003c\/p\u003e  \u003cp\u003e\u003cb\u003ePart II 3D Technology Modeling\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e3 Power and Performance Formulas\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e3.1 High-Level Formula for the Power Consumption\u003c\/p\u003e  3.2 High-Level Formula for the Propagation Delay\u003cp\u003e\u003c\/p\u003e  \u003cp\u003e3.3 Matrix Formulations\u003c\/p\u003e  \u003cp\u003e3.4 Evaluation\u003c\/p\u003e  \u003cp\u003e3.5 Conclusion\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e4 Capacitance Estimation\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e4.1 Existing Capacitance Models\u003c\/p\u003e  \u003cp\u003e4.2 Edge and MOS Effects on the TSV Capacitances\u003c\/p\u003e  \u003cp\u003e4.3 TSV Capacitance Model\u003c\/p\u003e  \u003cp\u003e4.4 Evaluation\u003c\/p\u003e  \u003cp\u003e4.5 Conclusion\u003c\/p\u003e  \u003cp\u003e\u003cb\u003ePart III System Modeling\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003exiii\u003c\/p\u003e  \u003cp\u003exiv Contents\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e5 Application and Simulation Models\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e5.1 Overview of the Modeling Approach\u003c\/p\u003e  5.2 Application Traffic Model\u003cp\u003e\u003c\/p\u003e  \u003cp\u003e5.3 Simulation Model of 3D NoCs\u003c\/p\u003e  \u003cp\u003e5.4 Simulator Interfaces\u003c\/p\u003e  \u003cp\u003e5.5 Conclusion\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e6 Bit-level Statistics\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e6.1 Existing Approaches to Estimate the Bit-Level Statistics for\u003c\/p\u003e  \u003cp\u003eSingle Data Streams\u003c\/p\u003e  \u003cp\u003e6.2 Data-Stream Multiplexing\u003c\/p\u003e  \u003cp\u003e6.3 Bit-Level Statistics with Data-Stream Multiplexing\u003c\/p\u003e  \u003cp\u003e6.4 Evaluation\u003c\/p\u003e  \u003cp\u003e6.5 Conclusion\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e7 Ratatoskr Framework\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e7.1 \u003ci\u003eRatatoskr \u003c\/i\u003efor Practitioners\u003c\/p\u003e  \u003cp\u003e7.2 Implementation\u003c\/p\u003e  \u003cp\u003e7.3 Evaluation\u003c\/p\u003e  7.4 Case Study: Link Power Estimation and Optimization\u003cp\u003e\u003c\/p\u003e  \u003cp\u003e7.5 Conclusion\u003c\/p\u003e  \u003cp\u003e\u003cb\u003ePart IV 3D-Interconnect Optimization\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e8 Low-Power Technique for 3D Interconnects\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e8.1 Fundamental Idea\u003c\/p\u003e  \u003cp\u003e8.2 Power-Optimal TSV assignment\u003c\/p\u003e  \u003cp\u003e8.3 Systematic Net-to-TSV Assignments\u003c\/p\u003e  8.4 Combination with Traditional Low-Power Codes\u003cp\u003e\u003c\/p\u003e  \u003cp\u003e8.5 Evaluation\u003c\/p\u003e  \u003cp\u003e8.6 Conclusion\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e9 Low-Power Technique for High-Performance 3D\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eInterconnects\u003c\/b\u003e.\u003c\/p\u003e  \u003cp\u003e9.1 Edge-Effect-Aware Crosstalk Classification\u003c\/p\u003e  \u003cp\u003e9.2 Existing Approaches and Their Limitations\u003c\/p\u003e  9.3 Proposed Technique\u003cp\u003e\u003c\/p\u003e  \u003cp\u003e9.4 Extension to a Low-Power 3D CAC\u003c\/p\u003e  \u003cp\u003e9.5 Evaluation\u003c\/p\u003e  \u003cp\u003e9.6 Conclusion\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e10 Low-Power Technique for High-Performance 3D\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eInterconnects (Misaligned)\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e10.1 Temporal-Misalignment Effect on the Crosstalk\u003c\/p\u003e  \u003cp\u003e10.2 Exploiting Misalignment to Improve the Performance\u003c\/p\u003e  \u003cp\u003e10.3 Effect on the TSV Power Consumption\u003c\/p\u003e  \u003cp\u003eContents xv\u003c\/p\u003e  \u003cp\u003e10.4 Evaluation\u003c\/p\u003e  \u003cp\u003e10.5 Conclusion\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e11 Low-Power Technique for Yield-Enhanced 3D Interconnects\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e11.1 Existing TSV Yield-Enhancement Techniques\u003c\/p\u003e  \u003cp\u003e11.2 Preliminaries—Logical Impact of TSV Faults\u003c\/p\u003e  \u003cp\u003e11.3 Fundamental Idea\u003c\/p\u003e  \u003cp\u003e11.4 Formal Problem Description\u003c\/p\u003e  \u003cp\u003e11.5 TSV Redundancy Schemes\u003c\/p\u003e  \u003cp\u003e11.6 Evaluation\u003c\/p\u003e  \u003cp\u003e11.7 Case Study\u003c\/p\u003e  \u003cp\u003e11.8 Conclusion\u003c\/p\u003e  \u003cp\u003e\u003cb\u003ePart V NoC Optimization for Heterogeneous 3D Integration\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e12 Heterogeneous Buffering for 3D NoCs\u003c\/b\u003e251\u003c\/p\u003e  \u003cp\u003e12.1 Buffer Distributions and Depths\u003c\/p\u003e  \u003cp\u003e12.2 Routers with Optimized Buffer Distribution\u003c\/p\u003e  \u003cp\u003e12.3 Routers with Optimized Buffer Depths\u003c\/p\u003e  \u003cp\u003e12.4 Evaluation\u003c\/p\u003e  \u003cp\u003e12.5 Discussion\u003c\/p\u003e  \u003cp\u003e12.6 Conclusion\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e13 Heterogeneous Routing for 3D NoCs\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e13.1 Heterogeneity and Routing\u003c\/p\u003e  \u003cp\u003e13.2 Modeling Heterogeneous Technologies\u003c\/p\u003e  \u003cp\u003e13.3 Modeling Communication\u003c\/p\u003e  13.4 Routing Limitations from Heterogeneity\u003cp\u003e\u003c\/p\u003e  \u003cp\u003e13.5 Heterogeneous Routing Algorithms\u003c\/p\u003e  \u003cp\u003e13.6 Heterogeneous Router Architectures\u003c\/p\u003e  \u003cp\u003e13.7 Low-Power Routing in Heterogeneous 3D ICs\u003c\/p\u003e  \u003cp\u003e13.8 Evaluation\u003c\/p\u003e  \u003cp\u003e13.9 Discussion\u003c\/p\u003e  \u003cp\u003e13.10Conclusion\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e14 Heterogeneous Virtualisation for 3D NoCs\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e14.1 Problem Description\u003c\/p\u003e  \u003cp\u003e14.2 Heterogeneous Microarchitectures Exploiting Traffic Imbalance\u003c\/p\u003e  \u003cp\u003e14.3 Evaluation\u003c\/p\u003e  14.4 Conclusion\u003cp\u003e\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e15 Network Synthesis and SoC Floor Planning\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e15.1 Fundamental Idea\u003c\/p\u003e  \u003cp\u003e15.2 Modelling and Optimization\u003c\/p\u003e  \u003cp\u003e15.3 Mixed-Integer Linear Program\u003c\/p\u003e  \u003cp\u003e15.4 Heuristic Solution\u003c\/p\u003e  \u003cp\u003exvi Contents\u003c\/p\u003e  \u003cp\u003e15.5 Evaluation\u003c\/p\u003e  \u003cp\u003e15.6 Conclusion\u003c\/p\u003e  \u003cp\u003e\u003cb\u003ePart VI Finale\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e\u003cb\u003e16 Conclusion\u003c\/b\u003e\u003c\/p\u003e  16.1 Putting it all together\u003cp\u003e\u003c\/p\u003e  \u003cp\u003e16.2 Impact on Future Work\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eA Appendix\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eB Pseudo Codes\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eC Method to Calculate the Depletion-Region Widths\u003c\/b\u003e\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eD Modeling Logical OR Relations\u003c\/b\u003e\u003c\/p\u003e","brand":"Springer Nature Switzerland AG","offers":[{"title":"Default Title","offer_id":49415670759767,"sku":"9783030982287","price":94.99,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9783030982287.jpg?v=1730527734"},{"product_id":"machine-learning-applications-in-electronic-design-automation-9783031130762","title":"Machine Learning Applications in Electronic","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003e​This book serves as a single-source reference to key machine learning (ML) applications and methods in digital and analog design and verification. Experts from academia and industry cover a wide range of the latest research on ML applications in electronic design automation (EDA), including analysis and optimization of digital design, analysis and optimization of analog design, as well as functional verification, FPGA and system level designs, design for manufacturing (DFM), and design space exploration. The authors also cover key ML methods such as classical ML, deep learning models such as convolutional neural networks (CNNs), graph neural networks (GNNs), generative adversarial networks (GANs) and optimization methods such as reinforcement learning (RL) and Bayesian optimization (BO). All of these topics are valuable to chip designers and EDA developers and researchers working in digital and analog designs and verification.  \u003c\/p\u003e\u003cbr\u003e\u003cp\u003e\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e1. Introduction2. Analysis of Digital Design: Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning3. RouteNet: Routability Prediction for Mixed-size Designs Using Convolutional Neural Network4. High Performance Graph Convolutional networks with Applications in Testability Analysis5. MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification6. GRANNITE: Graph Neural Network Inference for Transferable Power Estimation7. Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation at Advanced Process Nodes8. Optimization of Digital Design: Chip Placement with Deep Reinforcement learning9. DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement10. TreeNet: Deep Point Cloud Embedding for Routing Tree Construction11. Asynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing12. Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes13. PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning14. GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization15. Analysis and Optimization of Analog Design: Machine Learning Techniques in Analog Layout Automation16. Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks17. ParaGraph: Layout parasitics and device parameter prediction using graph neural network18. GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learn19. Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization20. Logic and Physical Verification: Deep Predictive Coverage Collection\/ Dynamically Optimized Test Generation Using Machine Learning21. Novelty-Driven Verification: Using Machine Learning to Identify Novel Stimuli and Close Coverage22. Using Machine Learning Clustering To Find Large Coverage Holes.- GAN-OPC: Mask optimization with lithography-guided generative adversarial nets.- Layout hotspot detection with feature tensor generation and deep biased learning.","brand":"Springer International Publishing AG","offers":[{"title":"Default Title","offer_id":49415686390103,"sku":"9783031130762","price":55.99,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9783031130762.jpg?v=1730527788"},{"product_id":"quality-of-service-aware-design-and-management-of-embedded-mixed-criticality-systems-9783031389597","title":"Quality-of-Service Aware Design and Management of","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eThis book addresses the challenges associated with efficient Mixed-Criticality (MC) system design. We focus on application analysis through execution time analysis and task scheduling analysis in order to execute more low-criticality tasks in the system, i.e., improving the Quality-of-Service (QoS), while guaranteeing the correct execution of high-criticality tasks. Further, this book addresses the challenge of enhancing QoS using parallelism in multi-processor hardware platforms. \u003c\/p\u003e\u003cbr\u003e\u003cp\u003e\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eIntroduction.- Preliminaries and Literature Reviews.- Bounding Time in Mixed-Criticality Systems.- Safety- and Task-Drop-Aware Mixed-Criticality Task Scheduling.- Learning-Based Drop-Aware Mixed-Criticality Task Scheduling.- Fault-Tolerance and Power-Aware Multi-Core Mixed-Criticality System Design.- QoS- and Power-Aware Run-Time Scheduler for Multi-Core Mixed-Criticality Systems.- Conclusion.\u003c\/p\u003e\u003cp\u003e\u003cbr\u003e\u003c\/p\u003e","brand":"Springer International Publishing AG","offers":[{"title":"Default Title","offer_id":49415715324247,"sku":"9783031389597","price":80.99,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9783031389597.jpg?v=1730527883"},{"product_id":"sensor-networks-in-theory-and-practice-successfully-realize-embedded-systems-projects-9783658395759","title":"Sensor networks in theory and practice:","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eThe book provides an important foundation for understanding the Internet of Things by offering insight into common networking protocols from the microcontroller world and introducing important sensors and other devices, as well as their use and programming. All concepts shown are illustrated with practical circuit and programming examples from the authors' many years of experience. In addition, open libraries for controlling the devices presented in the book are available for readers to download from the publisher's home page. The second edition includes some new devices, especially in the area of networks, a more detailed description of the operating principles of some sensors as well as further tips and tricks for programming.\u003cbr\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003e\u003cbr\u003e\u003c\/p\u003e","brand":"Springer Fachmedien Wiesbaden","offers":[{"title":"Default Title","offer_id":49420145459543,"sku":"9783658395759","price":52.24,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9783658395759.jpg?v=1730540943"},{"product_id":"evolution-in-signal-processing-and-telecommunication-networks-proceedings-of-sixth-international-conference-on-microelectronics-electromagnetics-and-telecommunications-icmeet-2021-volume-2-9789811685538","title":"Evolution in Signal Processing and","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eThis book discusses the latest developments and outlines future trends in the fields of microelectronics, electromagnetics and telecommunication. It contains original research works presented at the International Conference on Microelectronics, Electromagnetics and Telecommunication (ICMEET 2021), held in Bhubaneswar, Odisha, India during 27–28 August, 2021. The papers were written by scientists, research scholars and practitioners from leading universities, engineering colleges and R\u0026amp;D institutes from all over the world and share the latest breakthroughs in and promising solutions to the most important issues facing today’s society.\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003eAnalysis of Throughput \u0026amp; Spectral Efficiency of the CR Users with Channel Allocation.- On Performance Improvement of Wireless Push Systems Via Smart Antennas.- Hybridization of RF Switch and Related Aspects.- Estimation of Gender using Convolutional Neural Network.- Human Abnormal Activity Detection in the ATM Surveillance Video.- Moving object Detection using Optical Flow and HSV.- Propagation of Data Using Free Space Under Different Weather Conditions.- BEP Analysis of Filter Bank Multicarrier UnderIQ Imbalance.- Optical Character Recognition for Roman-Text .- Visual Words based Static Indian Sign Language Alphabet Recognition using KAZE Descriptors.","brand":"Springer Verlag, Singapore","offers":[{"title":"Default Title","offer_id":49427835814231,"sku":"9789811685538","price":197.99,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9789811685538.jpg?v=1730565841"},{"product_id":"artificial-intelligence-and-sustainable-computing-proceedings-of-icsiscet-2021-9789811916526","title":"Artificial Intelligence and Sustainable","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eThis book presents high-quality research papers presented at 3rd International Conference on Sustainable and Innovative Solutions for Current Challenges in Engineering and Technology (ICSISCET 2021) held at Madhav Institute of Technology \u0026amp; Science (MITS), Gwalior, India, from November 13–14, 2021. The book extensively covers recent research in artificial intelligence (AI) that knits together nature-inspired algorithms, evolutionary computing, fuzzy systems, computational intelligence, machine learning, deep learning, etc., which is very useful while dealing with real problems due to their model-free structure, learning ability, and flexible approach. These techniques mimic human thinking and decision-making abilities to produce systems that are intelligent, efficient, cost-effective, and fast. The book provides a friendly and informative treatment of the topics which makes this book an ideal reference for both beginners and experienced researchers.\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003eDemand based Land Suitability Prediction Model for Sustainable Agriculture.- Power Generation Forecasting of Wind Farms using Machine Learning Algorithms.- Music Recommendation System Based on Emotion Detection.- Service Analytics on ITSM Processes using Time Series.- Comparative Analysis of Color-based Segmentation Methods Used for Smartphone Camera Captured Fingerphotos.- Prediction of Heart Disease through KNN, Random Forest and Decision Tree Classifier using K-Fold Cross Validation.- Distance Matrix Generation for Dynamic Vehicle Routing Optimization in Transport Fleets Management.- Enhancing Weighted Support Vector Machine for Noise Classification.- Optimized Hysteresis Region Authenticated Handover for 5G HetNets.- Performance Improvement of CTNR Protocol in Wireless Sensor Network Using Machine Learning.","brand":"Springer Verlag, Singapore","offers":[{"title":"Default Title","offer_id":49427844333911,"sku":"9789811916526","price":170.99,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9789811916526.jpg?v=1730565869"},{"product_id":"memory-allocation-problems-in-embedded-systems-optimization-methods-9781848214286","title":"Memory Allocation Problems in Embedded Systems:","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eEmbedded systems are everywhere in contemporary life and are supposed to make our lives more comfortable. In industry, embedded systems are used to manage and control complex systems (e.g. nuclear power plants, telecommunications and flight control) and they are also taking an important place in our daily activities (e.g. smartphones, security alarms and traffic lights).\u003cbr\u003e In the design of embedded systems, memory allocation and data assignment are among the main challenges that electronic designers have to face. In fact, they impact heavily on the main cost metrics (power consumption, performance and area) in electronic devices. Thus designers of embedded systems have to pay careful attention in order to minimize memory requirements, thus improving memory throughput and limiting the power consumption by the system’s memory. Electronic designers attempt to minimize memory requirements with the aim of lowering the overall system costs.\u003cbr\u003e A state of the art of optimization techniques for memory management and data assignment is presented in this book.\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eIntroduction ix\u003c\/p\u003e \u003cp\u003eChapter 1. Context 1\u003c\/p\u003e \u003cp\u003e1.1. Embedded systems 2\u003c\/p\u003e \u003cp\u003e1.1.1. Main components of embedded systems 3\u003c\/p\u003e \u003cp\u003e1.2. Memory management for decreasing power consumption, performance and area in embedded systems 4\u003c\/p\u003e \u003cp\u003e1.3. State of the art in optimization techniques for memory management and data assignment 8\u003c\/p\u003e \u003cp\u003e1.3.1. Software optimization 9\u003c\/p\u003e \u003cp\u003e1.3.2. Hardware optimization 11\u003c\/p\u003e \u003cp\u003e1.3.3. Data binding  16\u003c\/p\u003e \u003cp\u003e1.3.3.1. Memory partitioning problem for low energy 17\u003c\/p\u003e \u003cp\u003e1.3.3.2. Constraints on memory bank capacities and number of accesses to variables 18\u003c\/p\u003e \u003cp\u003e1.3.3.3. Using external memory 19\u003c\/p\u003e \u003cp\u003e1.4. Operations research and electronics 21\u003c\/p\u003e \u003cp\u003e1.4.1. Main challenges in applying operations research to electronics 23\u003c\/p\u003e \u003cp\u003eChapter 2. Unconstrained Memory Allocation Problem 27\u003c\/p\u003e \u003cp\u003e2.1. Introduction 28\u003c\/p\u003e \u003cp\u003e2.2. An ILP formulation for the unconstrained memory allocation problem 31\u003c\/p\u003e \u003cp\u003e2.3. Memory allocation and the chromatic number 32\u003c\/p\u003e \u003cp\u003e2.3.1. Bounds on the chromatic number 33\u003c\/p\u003e \u003cp\u003e2.4. An illustrative example 35\u003c\/p\u003e \u003cp\u003e2.5. Three new upper bounds on the chromatic number 38\u003c\/p\u003e \u003cp\u003e2.6. Theoretical assessment of three upper bounds 45\u003c\/p\u003e \u003cp\u003e2.7. Computational assessment of three upper bounds 49\u003c\/p\u003e \u003cp\u003e2.8. Conclusion 53\u003c\/p\u003e \u003cp\u003eChapter 3. Memory Allocation Problem With Constraint on the Number of Memory Banks 57\u003c\/p\u003e \u003cp\u003e3.1. Introduction 58\u003c\/p\u003e \u003cp\u003e3.2. An ILP formulation for the memory allocation problem with constraint on the number of memory banks 61\u003c\/p\u003e \u003cp\u003e3.3. An illustrative example 64\u003c\/p\u003e \u003cp\u003e3.4. Proposed metaheuristics 65\u003c\/p\u003e \u003cp\u003e3.4.1. A tabu search procedure 66\u003c\/p\u003e \u003cp\u003e3.4.2. A memetic algorithm 69\u003c\/p\u003e \u003cp\u003e3.5. Computational results and discussion 71\u003c\/p\u003e \u003cp\u003e3.5.1. Instances 72\u003c\/p\u003e \u003cp\u003e3.5.2. Implementation 72\u003c\/p\u003e \u003cp\u003e3.5.3. Results 73\u003c\/p\u003e \u003cp\u003e3.5.4. Discussion 75\u003c\/p\u003e \u003cp\u003e3.6. Conclusion 75\u003c\/p\u003e \u003cp\u003eChapter 4. General Memory\u003c\/p\u003e \u003cp\u003eAllocation Problem 77\u003c\/p\u003e \u003cp\u003e4.1. Introduction 78\u003c\/p\u003e \u003cp\u003e4.2. ILP formulation for the general memory allocation problem 80\u003c\/p\u003e \u003cp\u003e4.3. An illustrative example 84\u003c\/p\u003e \u003cp\u003e4.4. Proposed metaheuristics 85\u003c\/p\u003e \u003cp\u003e4.4.1. Generating initial solutions 86\u003c\/p\u003e \u003cp\u003e4.4.1.1. Random initial solutions 86\u003c\/p\u003e \u003cp\u003e4.4.1.2. Greedy initial solutions 86\u003c\/p\u003e \u003cp\u003e4.4.2. A tabu search procedure 89\u003c\/p\u003e \u003cp\u003e4.4.3. Exploration of neighborhoods 91\u003c\/p\u003e \u003cp\u003e4.4.4. A variable neighborhood search hybridized with a tabu search 93\u003c\/p\u003e \u003cp\u003e4.5. Computational results and discussion 94\u003c\/p\u003e \u003cp\u003e4.5.1. Instances used 95\u003c\/p\u003e \u003cp\u003e4.5.2. Implementation 95\u003c\/p\u003e \u003cp\u003e4.5.3. Results 96\u003c\/p\u003e \u003cp\u003e4.5.4. Discussion 97\u003c\/p\u003e \u003cp\u003e4.5.5. Assessing TabuMemex 101\u003c\/p\u003e \u003cp\u003e4.6. Statistical analysis 105\u003c\/p\u003e \u003cp\u003e4.6.1. Post hoc paired comparisons 106\u003c\/p\u003e \u003cp\u003e4.7. Conclusion 107\u003c\/p\u003e \u003cp\u003eChapter 5. Dynamic Memory Allocation Problem 109\u003c\/p\u003e \u003cp\u003e5.1. Introduction 110\u003c\/p\u003e \u003cp\u003e5.2. ILP formulation for dynamic memory allocation problem 113\u003c\/p\u003e \u003cp\u003e5.3. An illustrative example 116\u003c\/p\u003e \u003cp\u003e5.4. Iterative metaheuristic approaches 119\u003c\/p\u003e \u003cp\u003e5.4.1. Long-term approach 119\u003c\/p\u003e \u003cp\u003e5.4.2. Short-term approach 122\u003c\/p\u003e \u003cp\u003e5.5. Computational results and discussion 123\u003c\/p\u003e \u003cp\u003e5.5.1. Results 124\u003c\/p\u003e \u003cp\u003e5.5.2. Discussion 125\u003c\/p\u003e \u003cp\u003e5.6. Statistical analysis 128\u003c\/p\u003e \u003cp\u003e5.6.1. Post hoc paired comparisons 129\u003c\/p\u003e \u003cp\u003e5.7. Conclusion . 130\u003c\/p\u003e \u003cp\u003eChapter 6. MemExplorer: Cases Studies 131\u003c\/p\u003e \u003cp\u003e6.1. The design flow 131\u003c\/p\u003e \u003cp\u003e6.1.1. Architecture used 131\u003c\/p\u003e \u003cp\u003e6.1.2. MemExplorer design flow 132\u003c\/p\u003e \u003cp\u003e6.1.3. Memory conflict graph 134\u003c\/p\u003e \u003cp\u003e6.2. Example of MemExplorer utilization 139\u003c\/p\u003e \u003cp\u003eChapter 7. General Conclusions and Future Work 147\u003c\/p\u003e \u003cp\u003e7.1. Summary of the memory allocation problem versions 147\u003c\/p\u003e \u003cp\u003e7.2. Intensification and diversification 149\u003c\/p\u003e \u003cp\u003e7.2.1. Metaheuristics for memory allocation\u003c\/p\u003e \u003cp\u003eproblem with constraint on the number of memory banks 149\u003c\/p\u003e \u003cp\u003e7.2.1.1. Tabu-Allocation 149\u003c\/p\u003e \u003cp\u003e7.2.1.2. Evo-Allocation 151\u003c\/p\u003e \u003cp\u003e7.2.2. Metaheuristic for general memory allocation problem 151\u003c\/p\u003e \u003cp\u003e7.2.3. Approaches for dynamic memory allocation problem 152\u003c\/p\u003e \u003cp\u003e7.3. Conclusions 152\u003c\/p\u003e \u003cp\u003e7.4. Future work 154\u003c\/p\u003e \u003cp\u003e7.4.1. Theoretical perspectives 154\u003c\/p\u003e \u003cp\u003e7.4.2. Practical perspectives 156\u003c\/p\u003e \u003cp\u003eBibliography 159\u003c\/p\u003e \u003cp\u003eIndex 181\u003c\/p\u003e","brand":"ISTE Ltd and John Wiley \u0026 Sons Inc","offers":[{"title":"Default Title","offer_id":49535808209239,"sku":"9781848214286","price":132.0,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9781848214286.jpg?v=1731899642"},{"product_id":"embedded-machine-learning-with-microcontrollers-9783031709111","title":"Embedded Machine Learning with Microcontrollers","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e","brand":"Springer","offers":[{"title":"Default Title","offer_id":50470490702167,"sku":"9783031709111","price":49.49,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9783031709111.jpg?v=1744898485"},{"product_id":"embedded-machine-learning-with-microcontrollers-9783031694202","title":"Embedded Machine Learning with Microcontrollers","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eBy covering traditional and neural network-based machine learning methods implemented on microcontrollers, the text is designed for use in courses on microcontrollers and embedded machine learning systems.","brand":"Springer International Publishing AG","offers":[{"title":"Default Title","offer_id":51043584999767,"sku":"9783031694202","price":999.99,"currency_code":"GBP","in_stock":false}]},{"product_id":"applied-tinyml-9789365890716","title":"Applied TinyML","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e","brand":"Unknown","offers":[{"title":"Default Title","offer_id":51360815743319,"sku":"9789365890716","price":29.92,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9789365890716.jpg?v=1754128510"},{"product_id":"application-and-theory-of-petri-nets-and-concurrency-43rd-international-conference-petri-nets-2022-bergen-norway-june-19-24-2022-proceedings-9783031066528","title":"Application and Theory of Petri Nets and Concurrency: 43rd International Conference, PETRI NETS 2022, Bergen, Norway, June 19–24, 2022, Proceedings","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eThis book constitutes the proceedings of the 43rd International Conference on Application and Theory of Petri Nets and Concurrency, PETRI NETS 2022, which was held virtually in June 2021.\u003c\/p\u003e  \u003cp\u003eThe 19 full papers presented in this volume were carefully reviewed and selected from 35 submissions. The papers are categorized into the following topical sub-headings: application of concurrency to system design; timed models; tools; applications; synthesis; petri nets architecture; and process mining.\u003c\/p\u003e","brand":"Springer International Publishing AG","offers":[{"title":"Default Title","offer_id":51742893080919,"sku":"9783031066528","price":58.49,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0817\/1739\/5799\/files\/9783031066528.jpg?v=1758387180"},{"product_id":"the-engineering-of-reliable-embedded-systems-9780993035531","title":"The Engineering of Reliable Embedded Systems","description":"","brand":"SafeTTy Systems Ltd","offers":[{"title":"Default Title","offer_id":52084153745751,"sku":"9780993035531","price":48.75,"currency_code":"GBP","in_stock":true}]},{"product_id":"design-a-z80-computer-9780995707221","title":"Design a Z80 computer","description":"","brand":"Oldfangled Publishing","offers":[{"title":"Default Title","offer_id":52084176912727,"sku":"9780995707221","price":24.7,"currency_code":"GBP","in_stock":true}]},{"product_id":"digital-logic-and-design-mastering-the-fundamentals-9781446660096","title":"Digital Logic and Design  Mastering the Fundamentals","description":"","brand":"Lulu.com","offers":[{"title":"Default Title","offer_id":52084930511191,"sku":"9781446660096","price":12.16,"currency_code":"GBP","in_stock":true}]},{"product_id":"architecting-high-performance-embedded-systems-design-and-build-high-performance-real-time-digital-systems-based-on-fpgas-and-custom-circuits-9781789955965","title":"Architecting High-Performance Embedded Systems: Design and build high-performance real-time digital systems based on FPGAs and custom circuits","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003e\u003cb\u003eExplore the complete process of developing systems based on field-programmable gate arrays (FPGAs), including the design of electronic circuits and the construction and debugging of prototype embedded devices\u003c\/b\u003e\u003c\/p\u003eKey Features\u003cul\u003e\n\u003cli\u003eLearn the basics of embedded systems and real-time operating systems\u003c\/li\u003e\n\u003cli\u003eUnderstand how FPGAs implement processing algorithms in hardware\u003c\/li\u003e\n\u003cli\u003eDesign, construct, and debug custom digital systems from scratch using KiCad\u003c\/li\u003e\n\u003c\/ul\u003eBook Description\u003cp\u003eModern digital devices used in homes, cars, and wearables contain highly sophisticated computing capabilities composed of embedded systems that generate, receive, and process digital data streams at rates up to multiple gigabits per second. This book will show you how to use Field Programmable Gate Arrays (FPGAs) and high-speed digital circuit design to create your own cutting-edge digital systems.\u003c\/p\u003e \u003cp\u003eArchitecting High-Performance Embedded Systems takes you through the fundamental concepts of embedded systems, including real-time operation and the Internet of Things (IoT), and the architecture and capabilities of the latest generation of FPGAs. Using powerful free tools for FPGA design and electronic circuit design, you'll learn how to design, build, test, and debug high-performance FPGA-based IoT devices. The book will also help you get up to speed with embedded system design, circuit design, hardware construction, firmware development, and debugging to produce a high-performance embedded device – a network-based digital oscilloscope. You'll explore techniques such as designing four-layer printed circuit boards with high-speed differential signal pairs and assembling the board using surface-mount components.\u003c\/p\u003e \u003cp\u003eBy the end of the book, you'll have a solid understanding of the concepts underlying embedded systems and FPGAs and will be able to design and construct your own sophisticated digital devices.\u003c\/p\u003eWhat you will learn\u003cul\u003e\n\u003cli\u003eUnderstand the fundamentals of real-time embedded systems and sensors\u003c\/li\u003e\n\u003cli\u003eDiscover the capabilities of FPGAs and how to use FPGA development tools\u003c\/li\u003e\n\u003cli\u003eLearn the principles of digital circuit design and PCB layout with KiCad\u003c\/li\u003e\n\u003cli\u003eConstruct high-speed circuit board prototypes at low cost\u003c\/li\u003e\n\u003cli\u003eDesign and develop high-performance algorithms for FPGAs\u003c\/li\u003e\n\u003cli\u003eDevelop robust, reliable, and efficient firmware in C\u003c\/li\u003e\n\u003cli\u003eThoroughly test and debug embedded device hardware and firmware\u003c\/li\u003e\n\u003c\/ul\u003eWho this book is for\u003cp\u003eThis book is for software developers, IoT engineers, and anyone who wants to understand the process of developing high-performance embedded systems. You'll also find this book useful if you want to learn about the fundamentals of FPGA development and all aspects of firmware development in C and C++. Familiarity with the C language, digital circuits, and electronic soldering is necessary to get started.\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003eTable of Contents\u003col\u003e\n\u003cli\u003eArchitecting high-performance embedded systems\u003c\/li\u003e\n\u003cli\u003eSensing the world\u003c\/li\u003e\n\u003cli\u003eOperating in real time\u003c\/li\u003e\n\u003cli\u003eDeveloping your first FPGA program\u003c\/li\u003e\n\u003cli\u003eImplementing systems with FPGAs \u003c\/li\u003e\n\u003cli\u003eDesigning circuits with KiCad\u003c\/li\u003e\n\u003cli\u003eBuilding high-performance digital devices\u003c\/li\u003e\n\u003cli\u003eBringing up the board for the first time\u003c\/li\u003e\n\u003cli\u003eThe firmware development process\u003c\/li\u003e\n\u003cli\u003eTesting and debugging the embedded system\u003c\/li\u003e\n\u003c\/ol\u003e","brand":"Packt Publishing Limited","offers":[{"title":"Default Title","offer_id":52085554118999,"sku":"9781789955965","price":45.27,"currency_code":"GBP","in_stock":true}]},{"product_id":"embedded-systems-architecture-design-and-write-software-for-embedded-devices-to-build-safe-and-connected-systems-9781803239545","title":"Embedded Systems Architecture: Design and write software for embedded devices to build safe and connected systems","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003e\u003cp\u003e\u003cb\u003eDesign safe and reliable software for embedded systems and explore the internals of device drivers, RTOS, and TEE\u003c\/b\u003e\u003c\/p\u003eKey Features\u003cul\u003e\n\u003cli\u003eIdentify and overcome challenges in embedded environments\u003c\/li\u003e\n\u003cli\u003eUnderstand and implement the steps required to increase the security of IoT solutions\u003c\/li\u003e\n\u003cli\u003eBuild safety-critical and memory-safe parallel and distributed embedded systems\u003c\/li\u003e\n\u003c\/ul\u003eBook Description\u003cp\u003eEmbedded Systems Architecture begins with a bird's-eye view of embedded development and how it differs from the other systems that you may be familiar with. This book will help you get the hang of the internal working of various components in real-world systems.\u003c\/p\u003e\u003cp\u003eYou'll start by setting up a development environment and then move on to the core system architectural concepts, exploring system designs, boot-up mechanisms, and memory management. As you progress through the topics, you'll explore the programming interface and device drivers to establish communication via TCP\/IP and take measures to increase the security of IoT solutions. Finally, you'll be introduced to multithreaded operating systems through the development of a scheduler and the use of hardware-assisted trusted execution mechanisms.\u003c\/p\u003e\u003cp\u003eWith the help of this book, you will gain the confidence to work with embedded systems at an architectural level and become familiar with various aspects of embedded software development on microcontrollers—such as memory management, multithreading, and RTOS—an approach oriented to memory isolation.\u003c\/p\u003eWhat you will learn\u003cul\u003e\n\u003cli\u003eParticipate in the design and definition phase of an embedded product\u003c\/li\u003e\n\u003cli\u003eGet to grips with writing code for ARM Cortex-M microcontrollers\u003c\/li\u003e\n\u003cli\u003eBuild an embedded development lab and optimize the workflow\u003c\/li\u003e\n\u003cli\u003eSecure embedded systems with TLS\u003c\/li\u003e\n\u003cli\u003eDemystify the architecture behind the communication interfaces\u003c\/li\u003e\n\u003cli\u003eUnderstand the design and development patterns for connected and distributed devices in the IoT\u003c\/li\u003e\n\u003cli\u003eMaster multitasking parallel execution patterns and real-time operating systems\u003c\/li\u003e\n\u003cli\u003eBecome familiar with Trusted Execution Environment (TEE)\u003c\/li\u003e\n\u003c\/ul\u003eWho this book is for\u003cp\u003eIf you're a software developer or designer looking to learn about embedded programming, this is the book for you. You'll also find this book useful if you're a beginner or a less experienced embedded programmer on a quest to expand your knowledge on embedded systems.\u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003eTable of Contents\u003col\u003e\n\u003cli\u003eEmbedded Systems – A Pragmatic Approach\u003c\/li\u003e\n\u003cli\u003eWork Environment and Workflow Optimization\u003c\/li\u003e\n\u003cli\u003eArchitectural Patterns\u003c\/li\u003e\n\u003cli\u003eThe Boot-Up Procedure\u003c\/li\u003e\n\u003cli\u003eMemory Management\u003c\/li\u003e\n\u003cli\u003eGeneral-Purpose Peripherals\u003c\/li\u003e\n\u003cli\u003eLocal Bus Interfaces\u003c\/li\u003e\n\u003cli\u003ePower Management and Energy Saving\u003c\/li\u003e\n\u003cli\u003eDistributed Systems and IoT Architecture\u003c\/li\u003e\n\u003cli\u003eParallel Tasks and Scheduling\u003c\/li\u003e\n\u003cli\u003eTrusted Execution Environment\u003c\/li\u003e\n\u003c\/ol\u003e","brand":"Packt Publishing Limited","offers":[{"title":"Default Title","offer_id":52085579907415,"sku":"9781803239545","price":41.31,"currency_code":"GBP","in_stock":true}]},{"product_id":"building-low-latency-applications-with-c-develop-a-complete-low-latency-trading-ecosystem-from-scratch-using-modern-c-9781837639359","title":"Building Low Latency Applications with C++: Develop a complete low latency trading ecosystem from scratch using modern C++","description":"\u003cb\u003eBook Synopsis\u003c\/b\u003e\u003cbr\u003eExplore techniques to design and implement low latency applications and study the impact of latency reduction Purchase of the print or Kindle book includes a free PDF eBook  Key Features  Understand the impact application performance latencies have on different business use cases Develop a deep understanding of C++ features for low latency applications through real-world examples and performance data Learn how to build all the components of a C++ electronic trading system from scratch  Book DescriptionC++ is meticulously designed with efficiency, performance, and flexibility as its core objectives. However, real-time low latency applications demand a distinct set of requirements, particularly in terms of performance latencies. With this book, you’ll gain insights into the performance requirements for low latency applications and the C++ features critical to achieving the required performance latencies. You’ll also solidify your understanding of the C++ principles and techniques as you build a low latency system in C++ from scratch. You’ll understand the similarities between such applications, recognize the impact of performance latencies on business, and grasp the reasons behind the extensive efforts invested in minimizing latencies. Using a step-by-step approach, you’ll embark on a low latency app development journey by building an entire electronic trading system, encompassing a matching engine, market data handlers, order gateways, and trading algorithms, all in C++. Additionally, you’ll get to grips with measuring and optimizing the performance of your trading system. By the end of this book, you’ll have a comprehensive understanding of how to design and build low latency applications in C++ from the ground up, while effectively minimizing performance latencies. What you will learn  Gain insights into the nature of low latency applications across various industries Understand how to design and implement low latency applications Explore C++ design paradigms and features for low latency development Discover which C++ features are best avoided in low latency development Implement best practices and C++ features for low latency Measure performance and improve latencies in the trading system  Who this book is forThis book is for C++ developers who want to gain expertise in low latency applications and effective design and development strategies. C++ software engineers looking to apply their knowledge to low latency trading systems such as HFT will find this book useful to understand which C++ features matter and which ones to avoid. Quantitative researchers in the trading industry eager to delve into the intricacies of low latency implementation will also benefit from this book. Familiarity with Linux and the C++ programming language is a prerequisite for this book.\u003cbr\u003e\u003cbr\u003e\u003cb\u003eTable of Contents\u003c\/b\u003e\u003cbr\u003eTable of Contents\u003col\u003e\n\u003cli\u003eProduct Information Document\u003c\/li\u003e\n\u003cli\u003eIntroducing Low Latency Application Development in C++\u003c\/li\u003e\n\u003cli\u003eDesigning Some Common Low Latency Applications in C++\u003c\/li\u003e\n\u003cli\u003eExploring C++ Concepts from A Low-Latency Application’s Perspective\u003c\/li\u003e\n\u003cli\u003eBuilding the C++ Building Blocks for Low Latency Applications\u003c\/li\u003e\n\u003cli\u003eDesigning Our Trading Ecosystem\u003c\/li\u003e\n\u003cli\u003eBuilding the C++ Matching Engine\u003c\/li\u003e\n\u003cli\u003eCommunicating with Market Participants\u003c\/li\u003e\n\u003cli\u003eProcessing Market Data and Sending Orders to the Exchange in C++\u003c\/li\u003e\n\u003cli\u003eBuilding the C++ Trading Algorithm’s Building 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